Abstract: Systems, methods, and apparatus to identify and prioritize application processes in one or more subsystems. Some embodiments identifying applications and processes associated with each application executing on a system, apply one or more priority rules to the identified applications and processes to generate priority information, and transmit the priority information to a subsystem. The subsystem then matches received requests with the priority information and services the processes according to the priority information.

Abstract: A method and an apparatus that synchronize an application state in a client with a data source in a backend system in an asynchronous manner are described. A response is sent to the client based on a priority determined according to a history of received update requests. When a notification message from a data source in a backend system is received, an update request is selected from a plurality of update requests currently pending to be served according to the priority associated with each update request. A response is sent to the client over a network corresponding to the selected update request. The response includes state updates according to the changes in the data source and the current application state in the corresponding client.

Abstract: An apparatus and method of speculatively decoding non-memory read commands. A command register and decoder, within the apparatus, compares high-order command bits provided on a serial bus with corresponding bits of recognized non-memory read commands. An early non-memory read command is asserted when incoming command bits match a non-memory read command. Early responsive data is prepared speculatively during the time the remainder of command bits is received and decoded. A determination of command speculation correctness is made after receipt of the full command. If the full command received is not the speculated non-memory read command, the prepared data is discarded. Earlier prepared data is produced as the subsystem response if the full command matches the speculative non-memory read command. For incoming commands with operands, such as an address, the same speculative determination based on high-order operand bits is performed.

Abstract: A method for controlling the sequence of a plurality of functions which are executable on at least two interacting devices is provided, first of the functions being implemented on a first device and the second of the functions being implemented on a second device. A system for implementing the method is provided, including an administrative unit which controls a sequence of the functions in such a manner that it prevents a first function and a second function which interfere with one another from simultaneously running.

Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.

Abstract: According to the present invention, an information processing apparatus which has a recognition function for recognizing connected peripheral devices and can make the connected peripheral devices available, comprises a holding unit adapted to hold the upper limit of device drivers to be installed, and an install controlling unit adapted to install device drivers by the upper limit held by the holding unit when device drivers corresponding to peripheral devices recognized by the recognition function are installed.

Abstract: An I/O address translation method for specifying relaxed ordering for I/O accesses are provided. With the apparatus and method, storage ordering (SO) bits are provided in an I/O address translation data structure, such as a page table or segment table. These SO bits define the order in which reads and/or writes initiated by an I/O device may be performed. These SO bits are combined with an ordering bit, e.g., the Relaxed Ordering Attribute bit of PCI Express, on the I/O interface. The weaker ordering indicated either in the I/O address translation data structure or in the I/O interface relaxed ordering bit is used to control the order in which I/O operations may be performed.

Abstract: In a device that can execute multiple media applications, but only one at a time, a media server coordinates among applications, but neither the media server nor the individual applications maintain rules regarding all of the different applications. Each connection used by an application is assigned a priority and communicates that priority to the media server when the connection is established. When an application requests to begin playback, the request is granted if no other application is playing, or if another application is playing on a connection having a priority at most equal to that of the connection used by the requesting application, but is denied if the connection already in use has a higher priority. Resumption of an application that was interrupted by another application on a connection with higher priority is determined by the interrupted application after the interruption ends, based on information communicated by the media server.

Abstract: An I/O-request processing system which is capable of reducing the maximum value of the time required until the I/O request of each external device is registered. An I/O-request receiving section (501) receives an I/O request issued from an external device (600). A process-information storage section (510) stores an I/O-request delay time (512) for each external device (600). A priority-process judgment section (520) registers the I/O request having a maximum I/O-request delay time (512) among the I/O requests which have been registered into an I/O-request cue (540).

Abstract: Methods and associated structure to assure correct order in delivery of SATA frames over a SAS wide port. In one aspect hereof, new connection requests from a SATA device are rejected until prior frames residing in receive buffers of the SAS/SATA controller are properly processed. In another aspect, when a device is already connected to the controller, the SAS/SATA controller may prevent return of a receiver ready primitive in response to a transmitter ready primitive until previously received frames are removed from the receive buffers.

Abstract: An input/output device stores host status information about the status of a host, and controls the input/output of data. By referring to the input/output information and the host status information, the device performs optimization control of selecting notification either by an interrupt process or a non-interrupt process. When a notification by the interrupt process is selected, data transfer control is performed to the host, and the data is transferred to the host by an interrupt. When a notification by the non-interrupt process is selected, data transfer control is performed to the host, and notification control is performed to transfer the data to the host by polling.

Abstract: A method and system are provided for updating software on a handheld computer in communication with a client computer system operable to connect to a network. Software installed on the handheld computer is identified with the client computer. Moreover, information on the identified software is transmitted from the client computer to a server connected to the network. Further, updated versions of the software installed on the handheld computer are transferred from the server to the client computer based on the identified software that is installed on the handheld computer. Still yet, the software installed on the handheld computer is updated with the updated versions transferred to the client computer.

Abstract: A system includes an integrated encoder comprising an optical storage controller for coupling to an optical storage medium, and a data encoder for coding input data coupled to the optical storage controller, a first external memory coupled to a first memory controller in the integrated encoder, and a second external memory coupled to a second memory controller in the integrated encoder. In one aspect, the integrated encoder further comprises a first memory arbiter for selectively directing access to the first external memory by the optical storage controller and the data encoder, and a second memory arbiter for selectively directing access to the second external memory by the optical storage controller and the data encoder.

Abstract: A method for controlling data traffic within a storage area network can be provided. The method can comprise analyzing data for a path in a storage area network to determine whether the path should be identified as a less preferred path, and controlling data traffic routing to avoid use of a path identified as a less preferred path. In some embodiments, the data can be obtained from a host bus adaptor in the path. In some embodiments, the controlling can comprise throttling traffic over a path identified as a less preferred path.

Abstract: For controlling a wave field synthesis renderer arranged in a wave field synthesis system, a scene description, in which not an absolute position or an absolute time instant, but a time span or location span within which the audio object may vary is indicated for a source, is used. Furthermore, there is provided a monitor, which monitors a utilization situation of the wave field synthesis system. An audio object manipulator finally varies the starting point of the audio object to be considered by the wave field synthesis renderer or the actual position of the audio object within the time span and/or location span, in order to avoid capacity bottlenecks on the transmission lines or in the renderer.

Abstract: Media drive control system and method. The media drive control system comprises a player console, a user operation filter, and a plurality of playback management devices. The player console provides an instant user operation (UOP) according to a received user command. The user operation filter comprises a queue and a management device. The queue receives and stores a plurality of UOPs, and outputs stored UOPs as control instructions on a first-in-first-out basis. The management device determines whether the queue is full. If the queue is full, the management device discards at least one of the stored UOPs prior to storing the instant UOP in the queue. Each playback management device receives control instructions for controlling corresponding playback devices.

Abstract: A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapath command from an initiator application for setting a default I/O priority for a specified logical unit, for storing the default I/O priority for the logical unit to a priority store of the storage controller, and selectively responsive to a data transfer command from an initiator application for storing the data transfer command to the storage controller. The storage controller is responsive to the datapath command for storing the I/O priority default value for the logical unit to the priority store; and responsive to the data transfer command with respect to the logical unit for queuing the data transfer command for execution based on the I/O priority default value.

Abstract: In general, the invention relates to a method for storing data. The method includes receiving an Input/Output (I/O) request to store data in a storage pool, determining whether the I/O request is a resilvering I/O request, if the I/O request is a resilvering I/O request: associating the I/O request with a first deadline, wherein the first deadline is associated with a low priority, and determining the quantized deadline for the I/O request using the first deadline. If the I/O request is not the resilvering I/O request: associating the I/O request with a second deadline, determining the quantized deadline for the I/O request using the second deadline, placing the I/O request in the I/O queue using the quantized deadline, and issuing the I/O request to the storage pool using the I/O queue.

Abstract: An information processing apparatus for processing an access request to access a recording medium from an application includes the following elements. A setting unit sets a priority unique to the access request from the application or permission information indicating whether or not processing on the access request from the application is permitted. A queue controller stores the access request provided with the priority or the permission information in a queue. An access request processor processes the access request stored in the queue according to the priority or the permission information.

Abstract: A base address sorting device in a switching device is disclosed that includes an array of base address registers in which each base address register contains a base address, an address shifting device; and a control logic element electrically coupled to the array of base address registers and operable, upon receiving a configuration command comprising a new base address, to implement a method for reconfiguring the contents of the array of base address registers. The method includes determining an insertion point base address register in the array of base address registers into which to write the new base address, shifting the contents of one or more base address registers array to other base address registers to preserve the sorted order, and shifting the contents of the configuration command into the insertion point base address register. The inserting results in preserving the pre-determined order of the register array content.

Abstract: The present invention provides a USB function apparatus which supports a plurality of USB descriptors and which is connected to a host apparatus via a USB to operate as a USB function, the USB function apparatus comprising a descriptor switching device which switches one of the plurality of USB descriptors to be transmitted to the host apparatus, a bus reset generating device which generates a bus reset to initialize communications with the host apparatus, and a control device which, when a descriptor request from the host apparatus is responded with a current USB description but if the host apparatus does not start communications in accordance with the USB descriptor, causes the descriptor switching device to switch the USB descriptor and causes the bus reset generating device to generate a bus reset.

Abstract: A Small Computer System Interface (SCSI) input/output (I/O) coordinator of an apparatus in an example caches in memory local to the SCSI I/O coordinator one or more I/O request contexts stored in memory non-local to the SCSI I/O coordinator.

Abstract: An isolated data acquisition device including a plurality of data acquisition channels, an isolated system management unit coupled to the data acquisition channels, a host system management unit, a serial bus coupled to the host system management unit and the isolated system management unit, and isolation circuitry coupled to the serial bus. The isolation circuitry electrically isolates the host system management unit from the isolated system management unit and the data acquisition channels. During operation, the isolated system management unit and the host system management unit may each store data associated with one or more pending bus transactions. Each of the system management units may select at least one of the pending bus transactions according to a predetermined priority scheme, encode and serialize the data associated with the selected bus transaction, and transmit the serialized data across the isolation circuitry to the other system management unit via the serial bus.

Abstract: One embodiment of the present invention sets forth a technique for mapping a small computer system interface (SCSI) architecture model-3 (SAM-3) task priority to an IEEE Standard 802.1q tag control information (TCI) field. Four bits that define a SAM-3 task priority are mapped to the three user priority bits within a standard 802.1q TCI field. By enabling the SAM-3 task priority of a given SCSI command to determine the user priority within a related IEEE 802.1q Ethernet frame, the Ethernet network is enabled to substantially honor the requested task priority for the SCSI command.

Abstract: A storage management device can receive a write operation that includes a data payload, store a first instance of the data payload at a first storage buffer in the storage management device, and evaluate a first cost equation to identify a second storage buffer in the storage management device, different from the first storage buffer, at which to optimally store a second instance of the data payload.

Abstract: A method transfers data between a memory and peripheral units. The method includes assigning priorities to the data to be transferred, and transferring the data by direct memory access (DMA) control between the memory and the peripheral units in conformity with the priorities assigned in each case.

Abstract: A computer system controls ordered memory operations according to a programmatically-configured ordering class protocol to enable parallel memory access while maintaining ordered read responses. The system includes a memory and/or cache memory including a memory/cache controller, an I/O device for communicating memory access requests from system data sources and a memory controller I/O Interface. Memory access requests from the system data sources provide a respective ordering class value. The memory controller I/O Interface processes each memory access request and ordering class value communicated from a data source through the I/O device in coordination with the ordering class protocol. Preferably, the I/O device includes at least one register for storing ordering class values associated with system data sources that implement memory access requests.

Abstract: Discovery of services between devices is provided prior to establishing a connection between devices, including wireless-enabled devices or devices that are communicatively coupled to wireless access points. Discovering services prior to establishing a connection may facilitate finding a desired service. The services that may be discovered may be, for example, print services, camera services, PDA services or any other suitable services. Services may be discovered using 802.11, UWB or any other suitable wireless technology. As one example, particular services may be requested. As another example, services that are provided by a device may be advertised.

Abstract: The invention classifies volumes (e.g., file systems or LUNS) of a data storage system according to application requirements and allocates space for the volumes on storage devices (e.g., hard disk drives) accordingly. A person such as an IT administrator configures the volumes specifying size, type (e.g., file system or SAN LUN), and priority (e.g., high, medium, low, or archive). The host schedules I/O requests to the storage devices in priority queues using the volume definition to match the application requirements and reduce storage seek time between volumes of different priorities. The host also allocates high performance bands of the storage devices to high performance applications and lower performance bands to lower performance applications. In this manner, the data storage system places data on the band of the storage device that best supports its performance needs.

Abstract: A serial bus controller using a nonvolatile ferroelectric memory is provided. The memory controller structure using a nonvolatile ferroelectric register enables control of variable access time according to addresses when data are exchanged through a serial bus. In the serial bus controller according to an embodiment of the present invention, access latency time by addresses is programmed using a nonvolatile ferroelectric register, and address access time is differently controlled depending on the programmed access latency when data are exchanged between a master and a FRAM chip through a serial bus, thereby improving system performance.

Abstract: A system and method is disclosed for prioritizing requests received from multiple requesters for presentation to a shared resource. The system includes logic that implements multiple priority schemes. This logic may be programmably configured to associate each of the requesters with any of the priority schemes. The priority scheme that is associated with the requester controls how that requester submits requests to the shared resource. The requests that have been submitted by any of the requesters in this manner are then processed in a predetermined order. This order is established using an absolute priority assigned to each of the requesters. This order may further be determined by assigning one or more requesters a priority that is relative to another requester. The absolute and relative priority assignments are programmable.

Abstract: In a particular embodiment, the disclosure is directed to a method of configuring a computer coupled to a residential gateway. The method includes executing resource sharing software on the computer, receiving a message from the residential gateway requesting identification of available resources of the computer, and sending a response message to the residential gateway. The response message identifies a set of available resources of the computer. The method further includes receiving access settings corresponding to each of the set of available resources and configuring the computer to provide access to each of the set of available resources in accordance with the access settings.

Abstract: Operations in a multi-processor, multi-control block environment are timed using timing queues and instruction queues. Upon receipt of a request for a subchannel control block (SCB) to perform an operation that needs to be timed, the SCB is queued on one of multiple timing queues based on an elapsed timeout limit (ETL) of the operation. There is an ETL for each operation, and each one the multiple timing queues is associated with an ETL for completing an operation. The SCB may be placed at the bottom of the timing queue, the timing queue ordered from oldest to youngest which allows for quickly checking large numbers of SCBs without having to check every element queue and without having to dequeuing the elements from this queue. Upon receipt of a request to perform a high-priority operation, the SCB may be queued in a high priority instruction queue. The SCB may remain the timing queue to retain its order and be placed on a high priority instruction queue for retrying an operation.

Abstract: A system and method for enabling users and developers to store data on a number of different types of local and remote devices connected to a multimedia console or a gaming console. The range of available storage devices creates issues that are addressed to avoid apparent inconsistencies in storage performance (e.g. latency). A consistent method of reading and writing data is provided such that end users and developers do not have to be concerned with restrictions and limitations inherent to various devices.

Abstract: Methods and apparatus are disclosed for managing device reservation. In one embodiment, upon receiving a device command from a first host, a device targeted by the device command is reserved for the first host and a reservation time period for expiration of the reservation status is set.

Abstract: An information processor includes: generating section generating a descriptor, the descriptor including positional information, which indicates a packet-by-packet recording position of the data in the memory, and delay time relating to packet-by-packet processing; an extracting section acquiring the descriptor generated by the generating section and extracting the positional information and the delay time from the acquired descriptor; an DMA section reading packet-by-packet data from the memory on the basis of the extracted positional information; and a delaying section delaying processing of at least one of the extracting section and the DMA section by the delay time that has been extracted by the extracting section.

Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

Abstract: A system for processing routing according to priorities of logical interfaces is provided. The system includes a priority setting unit for setting priorities of a plurality of logical interfaces set in a physical interface, and a priority scheduler for determining a priority of a respective logical interface from an input frame, and for outputting the input frame to a driver queue of the physical interface when the input frame is output from a logical interface having the highest priority. Traffic burstiness caused by queuing can be reduced in a network routing system employing at least one logical interface.

Abstract: Various systems and methods for maintaining write order fidelity in a distributed environment are disclosed. One method, which can be performed by each node in a cluster, involves associating a current sequence number with each of several write operations included in a set of independent write operations. In response to detecting that one of the write operations in the set is ready to complete, a new sequence number is selected, and that new sequence number is thereafter used as the current sequence number. None of write operations in the set is allowed to return to the application that initiated the write operations until the new sequence number has been advertised to each other node in the cluster. The method also involves receiving a message advertising a first sequence number from another node in the cluster, and subsequently using the first sequence number as the current sequence number.

Abstract: A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues data transfer requests. The transfer controller includes separate control of data source and data destination in a data transfer corresponding to the data transfer requests. The transfer controller includes a data transfer program register and active source and destination registers. The transfer controller operates from the active source and destination registers. Upon completion of a data transfer the transfer controller writes data transfer parameters from the data transfer program register to the active source and destination registers.

Abstract: A method and apparatus for a multiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of multiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).

Abstract: An information terminal disclosed herein includes a data storage in which data is stored; an internal controller which accesses the data storage by a request from inside the information terminal; and an external controller which accesses the data storage by a request from outside the information terminal. If a request that the internal controller access the data storage is generated while the external controller is accessing the data storage, then the external controller repeatedly transmits a negative reply that data has not been properly received in response to access from the outside and the internal controller accesses the data storage while the external controller repeatedly transmits the negative reply.

Abstract: According to one embodiment, an information processing device includes a plurality of connection ports for connecting devices, a storage device which stores processing priority information of the plurality of connection ports, a control device which controls the devices connected to the plurality of connection ports via the plurality of connection ports, and a processing section which determines, upon occurrence of a processing request from one of the devices other than a predetermined device and the control device during data transfer between the control device and the predetermined device via one of the plurality of connection ports, a processing priority based on the processing priority information of another connection port included in the plurality of connection ports and corresponding to the occurred processing request and processes the processing request according to the determined processing priority.

Abstract: A disk control device stores write requests from a cache memory or reads commands from a host in a queue for a disk drive in chronological order. When the number of write requests stored in the queue for the disk drive is greater than a predetermined value, the storage location of write requests is changed to a queue for an extra disk drive, and the write requests are stored in the queue for the extra disk drive. When the number of write requests stored in the queue for the disk drive becomes smaller than a predetermined threshold, the write requests stored in the extra disk drive are written back to the disk drive.

Abstract: A system and method for selective preclusion of bus access requests are disclosed. In an embodiment, a method includes determining a bus unit access setting at a logic circuit of a processor. The method also includes selectively precluding a bus unit access request based on the bus unit access setting.

Abstract: A DMA system includes at lease one read bus, at least one write bus, at least one buffer memory bus, and a DMA controller. The DMA controller comprises a plurality of channels and a bus arbiter. The channels are electrically connected to the read bus, the write bus, and the buffer memory bus. A source address and a destination address of data for each channel are assigned by a control table. The bus arbiter performs bus arbitration and prioritizes data access among the read bus, the write bus, and the buffer memory bus.

Abstract: A driver for a data storage device includes an access command and a verification command. The access command initiates an access (write, erase or read) of the data storage device while allowing a calling application to continue running without having to wait for the completion of the access. The verification command queries a preceding access. If the query indicates failure of the preceding access, the verification command repeats the preceding access until the preceding access succeeds. The verification command is called by the access command before the access command initiates a new access. The verification command also is called by an application following a sequence of related access command calls. A write access command saves the data to be written in a memory separate from the data storage device, in case the verification command needs that data to repeat a failed write.

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract: Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low priorities from the plurality of lines; and replacing a cache line with a relatively low priority with the new cache line.

Abstract: An apparatus, program product and method of processing access requests for a direct access storage device utilize a “fair elevator” algorithm to schedule access requests from a plurality of requesters desiring access to a direct access storage device (DASD). In particular, a fair elevator algorithm arbitrates requests by taking into account both the requesters with which various requests are associated, as well as the relative positions of the data to be accessed on the DASD. By sorting access requests based upon both requester identity and DASD position, both multitasking performance and DASD throughput are improved in a balanced manner, thus improving overall system performance.