Abstract: Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device.

Abstract: A control mechanism for data bus communications employs channels to which bus transactions are assigned, each channel having independent flow control. The control mechanism enforces an ordering algorithm among channels, whereby at least some transactions may pass other transactions. Channel attributes are programmable to vary the ordering conditions. Preferably, each channel is allocated its own programmable buffer area. The control mechanism independently determines, for each channel, whether buffer space is available and enforces flow control independently for each channel accordingly. Flow control is preferably credit-based, credits representing buffer space or some other capacity of a receiver to receive data. Preferably, the flow control mechanism comprises a central interconnect module controlling internal communications of an integrated circuit chip.

Abstract: Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

Abstract: A method for executing input/output (I/O) operations based on priority involves receiving a first I/O request for a unit of data, receiving a second I/O request for the same unit of data, determining a priority of the first I/O request and a priority of the second I/O request, and executing the first I/O request based on priority, where the first I/O request is executed based on the higher of the priority of the first I/O request and the priority of the second I/O request.

Abstract: According to one aspect of the present invention, a method is provided in which a request submitted by a user via a user-interface is sent from a client to a server for processing. Upon being notified by the server that the request may take a long time to process, inform the user of the status of the request. The user is informed of the progress of the request based upon progress information received from the server.

Abstract: A buffer chip having a first data interface for receiving a data item which is to be written and for sending a data item which has been read, having a conversion unit for parallelizing the received data item and for serializing the data item which is to be sent, having a second data interface for writing the parallelized data item to a memory arrangement via a memory data bus and for receiving the data item read from the memory arrangement via the memory data bus; having a write buffer storage for buffer-storing the data item which is to be written, having a control unit in order, after reception of a data item which is to be written via the first data interface in line with a write command, to interrupt the data from being written from the write buffer storage via the second data interface upon a subsequent read command.

Abstract: A method includes receiving a first memory access request from a first device during a first interval. The first memory access request is to access a first page of a multiple-page memory. The method further includes receiving a second memory access request from the first device during a second interval subsequent to the first interval and receiving a third memory access request from a second device during the second interval. The method additionally includes preferentially selecting the second memory access request over the third memory access request for provision to the multiple-page memory if an indicator indicates the second memory access request is expected to access the first page of the multiple-page memory.

Abstract: Decoding an address in an address space including a plurality of local ranges and a plurality of peripheral ranges is described. Various approaches for decoding an input address include determining decoder address bits of the address space that distinguish local ranges from each other and that distinguish local ranges from peripheral ranges. The local and peripheral ranges are interleaved and have a plurality of sizes. The number of decoder address bits is less than the number of address bits in the address space and less than the number of local ranges plus the number of peripheral ranges. Using the decoder address bits of an input address, it is determined whether the input address is within a portion of the address space that includes one of the local ranges and does not include any of the peripheral ranges nor the local ranges other than the one of the local ranges.

Abstract: A multiprocessor system includes a plurality of processors, a shared bus coupled to the plurality of processors, a resource coupled to the shared bus and shared by the plurality of processors, and an exclusive control unit coupled to the plurality of processors and configured to include a lock flag indicative of a locked/unlocked state regarding exclusive use of the resource, wherein the processors include a special purpose register interface coupled to the exclusive control unit, and are configured to access the lock flag by special purpose register access through the special purpose register interface.

Abstract: A USB controller is provided with multiple logic channels that share same physical address and data bus at an interface between the host system and the USB Host Controller; and dataports used by the host system to read and/or write data to the USB Host Controller. Also provided is a data packet format for transferring data, which comprises of an Endpoint Transfer Descriptor (“ETD”) that includes an EndPoint Descriptor and a Transfer Descriptor, wherein the host system programs the parameters of a communication channel for a particular Endpoint. Also included is a technique for partitioning a memory storage device into a first memory buffer and a second memory buffer; wherein the size of the first and second memory buffer may be programmed by the host system and the first and/or second memory buffer may contain more than one USB packet.

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract: An electronic system includes two or more peripheral devices or units each of which is electronically coupled to the host through a single port of a predetermined bus. By splitting commands from the host to at least one of the two or more peripheral units into subcommands or by repeating commands, the data bus will be released for another command to another device or unit, the overall system efficiency is thus improved.

Abstract: Disclosed is a method A method for controlling a storage system including a host computer; a first storage controller connected communicably to the host computer, for receiving a data frame transmitted from the host computer and executing data input to and data output from a first storage device in response to a data input/output request described in the data frame; and a second storage controller connected communicably to the first storage controller, comprising relaying by the first storage controller, upon receipt of the data frame transmitted from the host computer, the data frame to the second storage controller in response to information described in the data frame.

Abstract: A mechanism for reprioritizing high-latency input/output operations in a file system is provided. The mechanism expands a file access protocol, such as the direct access file system protocol, by including a hurry up command that adjusts the latency of a given input/output operation. The hurry up command can be employed in the Direct Access File System.

Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.

Abstract: Provided are an arbiter capable of improving memory access efficiency in a multi-bank memory, a memory access arbitration system including the arbiter, and an arbitration method thereof, where the arbiter detects requests that are not included in a busy bank, and allows the requests corresponding to a bank receiving the largest number of pending requests priorities; and write request information generated by masters is stored in a predetermined buffer to be output as additional master request information, and provides the corresponding master with an opportunity to generate new request information.

Abstract: A system for controlling I/O transfers includes a host system or initiator including an adapter driver layer; and a storage controller. The storage controller includes a priority store and an operation queue. The adapter driver is selectively responsive to a datapath command from an initiator application for setting a default I/O priority for a specified logical unit, for storing the default I/O priority for the logical unit to a priority store of the storage controller, and selectively responsive to a data transfer command from an initiator application for storing the data transfer command to the storage controller. The storage controller is responsive to the datapath command for storing the I/O priority default value for the logical unit to the priority store; and responsive to the data transfer command with respect to the logical unit for queuing the data transfer command for execution based on the I/O priority default value.

Abstract: In information storage systems in which data retrieval requires movement of at least one physical element, a measurable amount of time is required to reposition that physical element in response to each data write or read request. After selecting one or more data requests for dispatch based solely on an approaching or past due time deadline, additional requests are identified for data to be read or written to locations which are in close proximity to previously scheduled requests, previously selected additional requests, or the present position of the moveable physical element, obviating the need to expend the full amount of time required to accelerate the physical element and then decelerate the physical element to position it over the desired area within the information storage system. In this manner, data may be transferred to or retrieved from an information storage system more efficiently with less expenditure of time.

Abstract: A data transfer device arranged in a node for connection in compliance with a communication standard. The data transfer device includes a request signal generation circuit for generating request signals defined by the communication standard with different levels of priority. A determination circuit determines the request signal having the highest level of priority. Priority is given to the transfer of data corresponding to the request signal determined to have the highest level of priority by the determination circuit. A top priority request signal generation unit generates a top priority request signal that differs from the request signals defined by the communication standard. The determination circuit includes a priority determination table in which the uppermost priority request signal is set to have a level of priority that is higher than the levels of priority of the plurality of existing request signals.

Abstract: A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams become intermixed, a certain amount of latency results from the resulting page “breaks.” These page breaks occur when consecutive requests are from different data streams, requiring accesses to different memory pages. When several separate streams of data are requested by a client, page coherency between requests diminishes. A reordering device regains lost page coherency, thereby reducing the amount of latency and increasing overall system performance.

Abstract: A processing apparatus which is capable of preventing an priority reservation for a particular period from being set for all of a plurality of apparatuses and improving convenience for a general user who does not use an priority reservation service, in a system for which the priority reservation is available. Reservation information about a reservation for priority use of peripherals (MFP-A, B, and C) is stored. The number of peripherals that are not reserved for priority use during a particular period in the peripherals with reference to the reservation information is detected. When the number of peripherals is one, an instruction not to accept a reservation for priority use during the particular period to the single peripheral that are not reserved for priority use during the particular period in the peripheral is issued.

Abstract: In a first aspect, a first method is provided for servicing commands. The first method includes the steps of (1) receiving a first command for servicing in a memory controller including a plurality of memory ports, wherein the first command is of a first priority; (2) receiving a second command for servicing in the memory controller, wherein the second command is of a second priority that is higher than the first priority; (3) determining whether the first and second commands will be serviced through the same memory port; and (4) if the first and second commands will not be serviced through the same memory port, servicing the first and second commands during the same time period. Numerous other aspects are provided.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: A device that is connected to a bus can transmit data to one or more other devices and/or can receive data from other devices, through the bus, includes storage (i.e., memories or memory areas) in which data to be transmitted or received is temporarily stored, and a control device that determines whether or not any data is to be transmitted and, if appropriate, in which storage the data that are to be transmitted next is stored and/or in which storage the received data is to be stored. Information not contained in the data transmitted through the bus is stored in each storage, and is used to allocate a priority level to the respective storage, and the control device takes this information into account to decide the storage in which the next data to be transmitted will be stored and/or the storage in which the received data is to be stored.

Abstract: An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer amount, command importance degree, etc. The information recording apparatus recalculates the priority value regularly or arbitrary, and re-performs login negotiation by requesting re-login to the hosts. The amount of buffer allocated is dynamically changed by this login negotiation, and a buffer allocation state best suited to each occasion is built. Since the present invention can dynamically determine or change the allocation amount of the immediate data buffer in accordance with the condition of each occasion, the performance of an iSCSI apparatus can be improved.

Abstract: A method is provided for on-demand communications in a communication network with support for a plurality of communication units participating in a common communication, which includes multiple signal initiators, each supplying a signal, which are virtually simultaneously conveyed as part of the common communication. At least one example of an on-demand communication includes push to talk. Additionally, a signal initiator is provided, which is adapted to support on-demand communications in a multi-signal initiator environment.

Abstract: A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in a third transfer to the circuit and (D) transmitting the first write signal within a plurality of fourth transfers from the circuit.

Abstract: A method of serializing administrative operations on virtual volumes includes operating a storage system to maintain a plurality of virtual volumes that share a pool of block storage, where each of the virtual volumes containing data stored on one or more physical storage devices. Administrative access to each of the virtual volumes is controlled individually by imposing serialization on administrative operations directed to each virtual volume.

Abstract: An information terminal disclosed herein includes a data storage in which data is stored; an internal controller which accesses the data storage by a request from inside the information terminal; and an external controller which accesses the data storage by a request from outside the information terminal. If a request that the internal controller access the data storage is generated while the external controller is accessing the data storage, then the external controller repeatedly transmits a negative reply that data has not been properly received in response to access from the outside and the internal controller accesses the data storage while the external controller repeatedly transmits the negative reply.

Abstract: Systems, methods, and computer products that improve the performance of computer-implemented I/O operations for complex applications, such as a database, that are ported to target computer systems that are not tailored to support the high-performance services that may benefit applications. Complex applications, such as a database, often manage I/O access operations by a caching mechanism that is tailored to the needs of the application. When porting an application to a target computer system that does not support certain I/O access features, I/O performance of the application may be limited. The present invention may be implemented by introducing specialized I/O access features that are tailored to enhance I/O access performance for complex applications, such as a database.

Abstract: A scalable networking protocol that allows multiple nodes to communicate via a multi-channel network medium is described. The networking protocol allows any node on the network to assign itself as the active network server. The active network server polls client nodes based on a lineup card. The lineup card includes a high priority queue for low-latency devices, and a low priority queue for devices that can tolerate higher latencies. Network information is sent on the channels as fragments. The protocol provides bad-channel detection and retransmission of fragments in a fragment-by-fragment basis. Support for streaming data or asynchronous data is provided by allocating time slots on the network and allowing two intelligent nodes to talk directly to each other during count-limited token sessions, as arbitrated by the active network server.

Abstract: A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.

Abstract: An invention is provided for a reactive placement controller for interfacing with a banked memory storage. The reactive placement controller includes a read/write module, which is coupled to a command control module for a banked memory device. A command queue is included that comprises a plurality of queue entries coupled in series, with a top queue entry coupled to the read/write module. Each queue entry is capable of storing a memory command. Each queue entry includes its own queue control logic that functions to control storage of new memory commands into the command queue to reduce latency of commands in the command queue.

Abstract: Storage requests are divided into high-priority requests generally requiring low response time and low-priority requests generally requiring high throughput. The high-priority requests are further divided into several priorities reflecting different classes of service. The low-priority requests are placed on a low-priority request queue where they are executed in a throughput-optimizing order generally different from their arrival order. For each high-priority request, if there are not more than a predetermined number n (e.g., 1) outstanding requests for execution by the disk drive of greater priority, then the request is placed on a high-priority request queue where it is generally executed ahead of requests on the low-priority request queue. If there are more than n such greater-priority requests outstanding, then the high-priority request is placed on the low priority request queue and included in the throughput optimization along with the low-priority requests.

Abstract: The invention relates to management of I/O in data storage systems. In an embodiment, the invention provides a data storage subsystem processing I/O requests each having a priority, comprising a processor, a memory coupled to the processor, a disk array, an array controller coupled to the processor and the disk array, a network interface, coupled to the processor, to receive an I/O request with a priority, and a program in the memory for managing the I/O request based on the priority, a clip level of the priority, the total workload in the data storage subsystem, and processing I/O requests based on priority, workload clip levels, and fairness levels. The invention also contemplates the use of static and dynamic adjusted clip levels.

Abstract: Remotely obtaining exclusive control of a device by remotely establishing communication with the device over a network, requesting to obtain remote exclusive control of the device's capabilities, and determining whether remote exclusive control of the device's capabilities can be obtained based on whether or not another user already has exclusive control of the device's capabilities. In a first case where it is determined that remote exclusive control can be obtained, authenticating a user requesting to obtain remote exclusive control of the device's capabilities, providing the user remote exclusive control of the device's capabilities after the user has been authenticated, and temporarily deferring requests by users other than the user who has obtained remote exclusive control to perform operations utilizing the device's capabilities during a period in which the user maintains remote exclusive control of the device's capabilities.

Abstract: A system and method for re-ordering store operations from a processor core to a store queue. When a store queue receives a new processor-issued store operation from the processor core, a store queue controller allocates a new entry in the store queue. In response to allocating the new entry in the store queue, the store queue controller determines whether or not the new entry is dependent on at least one other valid entry in the store queue. In response to determining the new entry is dependent on at least one other valid entry in the store queue, the store queue controller inhibits requesting of the new entry to the RC dispatch logic until each valid entry on which the new entry is dependent has been successfully dispatched to an RC machine by the RC dispatch logic.

Abstract: A mixed queue method for managing storage requests directed includes a low-priority request queue on which all low-priority requests are placed and where they are subject to throughput optimization by re-ordering. When a high-priority request limit has not been reached, high-priority requests are placed on a high-priority request queue where they are executed in a pre-emptive manner with respect to the queued low-priority requests, thus experiencing reduced access time. When the high-priority request limit has been reached, the high-priority requests are placed on the low-priority request queue, such that the high-priority requests are included in the throughput optimization along with the low-priority requests on the request queue. Starvation of the low-priority requests is avoided, and the overall throughput of the disk drive is maintained at a relatively high level.

Abstract: Provided are methods, apparatus and computer programs for scheduling storage input and/or output (I/O) requests. A method for scheduling storage access requests determines a request processing sequence calculated to maximize SLA-based revenues achievable from processing a number of requests. A storage controller includes a scheduler which implements a revenue-based scheduling function to determine a revenue-maximizing processing sequence, and then assigns storage access requests to locations in a queue corresponding to the determined sequence. In an on-line mode, the scheduler can adapt to additional received requests, evaluating the revenue function for the additional requests and modifying the schedule if required. The method may include analysing a request stream to predict requests that are likely to be received in the near future, and taking account of the predicted requests when determining a processing schedule.

Abstract: A data transfer control device including: a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer; and a transfer controller which controls data transfer between the pipe regions and corresponding endpoints. The transfer controller performs processing of pausing data transfer between the pipe regions and the endpoints, the buffer controller performs reconstruction processing which includes at least one of deletion, addition, and size change of the pipe regions after the completion of the pause processing, and then the transfer controller resumes the paused data transfer after the reconstruction processing of the pipe regions. Data in the pipe regions before the reconstruction processing is copied to the pipe regions after the reconstruction processing while preventing the data from being erased.

Abstract: In a method of controlling transmitting and receiving buffers of a network controller and a network controller operating under such a method, at least one request for access to a system bus from the transmitting buffer and the receiving buffer is received, and the occupancy level of data in the receiving buffer and the vacancy level of data in the transmitting buffer are determined. Access to the system bus is granted based on the determination result. Buffers in the transmitting and receiving paths are treated as a single virtual transmitting buffer and a single virtual receiving buffer, respectively. Bus priority is determined by the data occupancy level in each virtual buffer and any change in the occupancy level. Therefore, it is possible to prevent or reduce underflow of the transmitting buffer and overflow of the receiving buffer, thereby impartially arbitrating which of the buffers can access the memory.

Abstract: A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

Abstract: A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the transactions bus arbitration priorities to facilitate prioritization and granting of access to an on-chip bus to the contending transactions. In one embodiment, an integrated circuit includes the on-chip bus and a number of the subsystems interacting with each other through transactions across the on-chip bus.

Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.

Abstract: A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: A single chip, embedded symmetric multiprocessor (ESMP) having parallel multiprocessing architecture composed of identical processors includes a single program memory. Program access arbitration logic supplies an instruction to a single requesting central processing unit at a time. Shared memory access arbitration logic can supply data from separate simultaneously accessible memory banks or arbitrate among central processing units for access. The system may simulate an atomic read/modify/write instruction by prohibiting access to the one address by another central processing unit for a predetermined number of memory cycles following a read access to one of a predetermined set of addresses in said shared memory.

Abstract: One or more methods and systems of prioritizing access of physical memory space to bus compliant devices in a computing device is presented. Prioritization is based on real time or non-real time device functionality. In one embodiment, the method of accessing physical memory space for use by a bus compliant device comprises receiving a memory request from the device through a data bus. In addition, the method comprises comparing addresses of the memory request to a range of memory addresses stored in a memory request comparator. In one embodiment, the system for prioritizing the access of physical memory space in response to memory requests comprises one or more device and/or bus drivers, and a memory request comparator. The one or more device and/or bus drivers facilitates implementation of address ranges within said memory request comparator for one or more bus compliant devices.

Abstract: Disclosed is a method A method for controlling a storage system including a host computer; a first storage controller connected communicably to the host computer, for receiving a data frame transmitted from the host computer and executing data input to and data output from a first storage device in response to a data input/output request described in the data frame; and a second storage controller connected communicably to the first storage controller, comprising relaying by the first storage controller, upon receipt of the data frame transmitted from the host computer, the data frame to the second storage controller in response to information described in the data frame.

Abstract: An RF tag 25 is incorporated in a mouse 20, and an RF tag reader 15 is mounted on the main body side of a computer 10. When using the mouse 20 to a specified computer 10, a user moves the mouse close to the reader 15 to read identification information (ID) of the mouse 20, which is included in the RF tag 25. On the main body side of the computer 10, the mouse 20 is designated in accordance with the read ID and communication with the mouse 20 is set. There may be a case where a plurality of computers and peripheral equipment intermingle, but, by making joint use of the ID reader 15 in a short-range, a corresponding relationship between the main body of the computer 10 and the wireless equipment 20 is made clear.

Abstract: Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent arbitrating for control of the loop. The improved communications channel system includes a channel node having one or more ports, each port supporting a fiber-channel arbitrated-loop serial communications channel loop, wherein each port arbitrates for control of that port's attached channel loop. The system also includes an arbitration-and-control apparatus to reduce arbitrated-loop overhead, wherein control of the channel loop, once control is achieved by arbitration, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the node.