Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.

Abstract: In one embodiment of the present invention, a secure storage system includes a removable storage device having a secure storage area for storage of secure data and a public storage area and device port for coupling the removable storage device to a host, the removable storage device appearing, to the host, to be non-removable so that the secure storage area remains hidden and the secure data remains secure.

Abstract: Present invention unity parallel processing systems and methods facilitate flexible utilization of sequential program applications in a distributed multi-computer parallel processing environment. The new unity parallel processing architecture enables multiple processing nodes (e.g., SMPs) to perform multi-thread processing within the multiple processing nodes while providing a shared virtual global memory space. Symmetric multiprocessors run shared memory applications with modified runtime guidance directives that permit the memories to emulate a virtual global memory across the plurality of symmetric multiprocessors. Within each SMP node, programs utilize multiple threads according to directives and library calls. Across multiple SMP nodes, each SMP node is treated as a single process with one-way communication to other SMP nodes.

Abstract: A processor divides resources into secure resources and non-secure resources. Virtual-to-physical address translation page tables may be stored in either secure or non-secure memory.

Abstract: A deque of a local process in a memory work-stealing implementation may use one or more data structures to perform work. If the local process attempts to add a new value to its deque's data structure when the data structure is full (i.e., an overflow condition occurs), the contents of the data structure are copied to a larger allocated data structure (e.g., an array of greater size than an original array). The entries in the original, smaller-sized data structure are copied to exact positions in the now-active, larger-sized data structure. By this technique, the local process is thus provided with space to add the new value.

Abstract: A method for automatically generating a software stack in an information handling system. The information handling system includes a software process partition. The method includes generating a manifest identifying software stack contents, creating a target partition within the information handling system, installing the specified software stack components into the target partition, configuring the target partition as active and bootable and the software process partition as hidden, booting into the target partition, setting up and configuring the software components within the target partition, and configuring the software process partition as active and bootable and the target partition as inactive. The generated software stack optionally may be captured for later use.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

Abstract: A flexible multi-area memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area shared by the first and the second processors. The common area has two ports and thereby simultaneously accessible from the first and the second processors. Each capacity of the first, the second, and the common areas can be set arbitrarily.

Abstract: Methods, systems, and media for managing dynamic memory are disclosed. Embodiments may disclose identifying nodes with having memory for dynamic storage, and reserving a portion of the memory from the identified nodes for a heap pool. After generating a heap pool, embodiments may allocate dynamic storage from the heap pool to tasks received that are associated with one of the identified nodes. More specifically, embodiments identify the node or home node associated with the task, the amount of dynamic storage requested by the task, and create a heap object in the node associated with the task to provide the requested dynamic storage. Some embodiments involve de-allocating the dynamic storage assigned to the task upon receipt of an indication that the task is complete and the dynamic storage is no longer needed for the task. Several of such embodiments return the de-allocated dynamic storage to the heap pool for reuse.

Abstract: A method for implementing security management in a storage area network by controlling access to network resources. Initially, a resource provider communicates with potential resource users, such as host computers, servers, and workstations, to allow the users to discover the resources available on the storage area network. Resource users that have not previously logged in to a particular resource supply identification information to the resource provider, which places the information in a ‘not yet approved entity’ table. The ‘not yet approved entity’ table is made available to a management station. An administrator, using the management station, then determines whether to authorize use of resources. If access to the requested resource is allowed, the resource user identification information is stored in an ‘approved entity’ table. A login is then allowed by the resource user to the selected resource.

Abstract: A cross compare solution running in a multiprocessor configuration, using a multi-port RAM with built-in logic. This provides for a fast and simple data cross compare medium. The multi-port RAM unit can be plugged into the motherboard of the main processor unit, requiring no external hardware or wiring. A method and a system for cross compare has a first layer of buffers with a first storage area for storing information from the first processor and a second storage area for storing information from the second processor, and a second layer of buffers with a third and fourth storage areas, where each storage area stores information from the first and second storage areas. The first, second, third, and fourth storage areas have one or more buffers allocated only for its respective storage area.

Abstract: A deque of a local process in a memory work-stealing implementation may use one or more data structures to perform work. If the local process attempts to add a new value to its deque's circular array when the data structure is full (i.e., an overflow condition occurs), the contents of the data structure are copied to a larger allocated circular array (e.g., a circular array of greater size than the original circular array). The entries in the original, smaller-sized circular array are copied to positions in the now-active, larger-sized circular array, and the system is configured to work with the newly activated circular array. By this technique, the local process is thus provided with space to add the new value.

Abstract: In a memory, first and second data areas are set as an area which stores one data item and a management area which stores determination information used to determine which one of the first and second data areas stores the newest data is additionally set. In the process of writing data into the memory, data is written into one of the data areas which stores data determined not to be the newest data based on the determination information and identification information is updated when the data writing process is correctly terminated.

Abstract: A system and method for enabling prioritized sharing of devices in partitioned environments. The method includes enabling I/O (Input/Output) requests from the partitions to be routed to a resource arbiter. The resource arbiter receives, from a partition, an I/O request for a device to be shared across partitions. The resource arbiter determines whether the device associated with the I/O request is busy. If the device is not busy, the resource arbiter sets a busy flag for the device and processes the I/O request. If the device is busy, the resource arbiter determines whether the device allows for interleaved access. If the device allows for interleaved access, then the resource arbiter queues the I/O request so that the I/O request can be processed using interleaved access.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A logically-partitioned computer system provides support for multiple logical partitions to access a single file system, thereby allowing the logical partitions to share a file without the overhead of communicating over a VLAN. An area of shared memory is defined that multiple logical partitions may access. One or more file control blocks that control access to the files in the file system are then created in the shared memory. Existing mechanisms for locking a file system between processes may then be used across logical partitions to serialize access to the file system by all processes in all logical partitions that share the file system. In this manner the sharing of files in a file system is enabled by leveraging existing technology that is used within a single logical partition to extend across multiple logical partitions.

Abstract: An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer amount, command importance degree, etc. The information recording apparatus recalculates the priority value regularly or arbitrary, and re-performs login negotiation by requesting re-login to the hosts. The amount of buffer allocated is dynamically changed by this login negotiation, and a buffer allocation state best suited to each occasion is built. Since the present invention can dynamically determine or change the allocation amount of the immediate data buffer in accordance with the condition of each occasion, the performance of an iSCSI apparatus can be improved.

Abstract: A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of nodal memory is associated with each processor in the node. A processor may request additional memory, and the other processor(s) may grant or veto the request. If granted, the requested memory is added to the subdivision of the requesting processor. A processor can only access memory within its own subdivision. Preferably, each subdivision contains a daemon which monitors memory usage and generates requests for additional memory.

Abstract: A method of controlling concurrent users of a distributed resource on a network is disclosed. In one aspect, there are one or more local lock managers executing on corresponding hosts and cooperating as a distributed lock manager. The resource is limited to a maximum number of concurrent users. A user identification for each user is associated with one host. In response to a request associated with a particular user associated with a first host, a lock is requested from a first local lock manager process executing on the first host. A related method of handling a request for a count-limited resource includes receiving a request from a client process for the computer resource. If it is determined that the request exceeds a maximum count for the resource, then it is determined whether a current time is within a retry time period of the client's first request.

Abstract: A technique to collectively manage locks by multiple virtual machines and then access shared data protected by the locks. A computer system defines first and second virtual machines and a memory shared by the first and second virtual machines. A lock structure is defined in the shared memory. The lock structure is capable of listing a holder of a lock for shared data in the shared memory. The first virtual machine acquires a lock for the shared data when available by manipulation of the lock structure. After acquiring the lock, the first virtual machine accesses the shared data. The lock structure and the shared data are directly accessible by the first virtual machine. The second virtual machine acquires a lock for the shared data when available by manipulation of the lock structure. After acquiring the lock, the second virtual machine accesses the shared data. The lock structure and shared data are directly accessible by the second virtual machine.

Abstract: A system for sharing memory by heterogeneous processors, each of which is adapted to process its own instruction set, is presented. A common bus is used to couple the common memory to the various processors. In one embodiment, a cache for more than one of the processors is stored in the shared memory. In another embodiment, some of the processors include a local memory area that is mapped to the shared memory pool. In yet another embodiment, local memory included on one or more of the processors is partially shared so that some of the local memory is mapped to the shared memory area, while remaining memory in the local memory is private to the particular processor.

Abstract: A system and methods for sharing configuration information with multiple services, or processes, via shared memory. The configuration information, typically, comprises runtime information utilized by processes during operation, including without limitation, information describing data communication connections between the local computer and other computing resources (i.e., port and wire information), and information defining numeric values or character string values (i.e., genre and record information). The system architecture includes a plurality of APIs which: reside at the local computer; populate, manage, and control access to a shared memory containing the configuration information; and, are executable only by processes executing at the local computer, thereby limiting access to the shared memory. Access to the configuration information is further limited to only those processes identified as having appropriate permission.

Abstract: A central processing unit having: (A) a microprocessor; (B) a main memory; (C) a microprocessor interface. The interface includes: a semiconductor integrated circuit having formed therein: (i) a data rebuffering section disposed in the chip and adapted to couple data from a one of a plurality of data ports to a data port of the microprocessor selectively in accordance with a control signal; and (ii) a main memory interface adapted for coupling to a main memory for the microprocessor, such main memory interface being adapted for coupling to the microprocessor and being coupled to the data rebuffering section for providing control signals to the main memory section for enabling data transfer between the main memory and the microprocessor through the data rebuffering section.

Abstract: One embodiment of the present invention provides a system that logically partitions different classes of translation lookaside buffer (TLB) entries within a single caching structure. Upon receiving a request to lookup an address translation, the system applies a hash function to parameters associated with the request to determine a corresponding location in the single caching structure where a TLB entry for the request can reside. If the corresponding location contains a TLB entry for the request, the system returns data from the TLB entry to facilitate the address translation. This hash function partitions the single caching structure so that different classes of TLB entries are mapped to separate partitions of the single caching structure. In this way, the single caching structure can accommodate different classes of TLB entries at the same time.

Abstract: The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. The locking cache or other fast memory can be used as additional system memory. In an embodiment of the invention, the locking cache is one or more sets of ways, but not all of the sets or ways, of a multiple set associative cache.

Abstract: A method, apparatus and program product for the dynamic reallocation of shared processing resources in a computing system is provided. The method/apparatus/program product attempts to allocate the shared processing resource among the two or more logical partitions in the computing system based on a current utilization of the shared processing resource among each of the two or more logical partitions and a current utilization of shared processing resource for the computing system as a whole. More specifically, the shared processing resource is reallocated from logical partitions having a relatively lower current utilization of their owned portion of the shared processing resource to logical partitions having a relatively high current utilization of their owned portion of the shared processing resource.

Abstract: The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locking cache until it is specifically overwritten under software control. In an embodiment of the invention, a processor can write data to the cache or other fast memory without also writing it to main memory. The portion of the cache or other fast memory can be used as additional system memory.

Abstract: A VLIW processor comprising a plurality of functional units (1, 3, 5, 7), a distributed register file (9, 11, 13, 15) accessible by the functional units (1, 3, 5, 7), a partially connected communication network (17) for coupling the functional units (1, 3, 5, 7) and selected parts of the distributed register file (9, 11, 13, 15), characterized in that the VLIW processor further comprises a communication device (29) for coupling the functional units (1, 3, 5, 7) and the distributed register file (9, 11, 13, 15).

Abstract: Even if a plurality of tasks that access a plurality of data areas each having the different control method are operated in parallel and the access requests are generated almost simultaneously, the simultaneous accesses to the memory device can be prevented and also a plurality of tasks can be operated in parallel while maintaining a real-time characteristic since the access request contained in the tasks are divided into partial request units by the access-request mediating portion to switch the access requests.

Abstract: A Dynamic Storage Subsystem Morphing (DSSM) mechanism (40) is connected to a plurality of storage subsystem resources, which reserve some storage area each non-donor ECU (12), ready for a “slot-down/up” access by a respective non-donor ECU having a storage subsystem (24) breakdown. The slot-down process enables the use of a high physical address range by the non-donor processor provided with addressing capabilities sufficient only for addressing lower ranges.

Abstract: Methods and systems are disclosed for creating and recovering backup copies of computer data in an enterprise. An example method is disclosed for recovering computer data from a plurality sequential access devices. The method includes identifying a plurality of objects to be recovered, identifying a backup corresponding to each identified object to be recovered, and identifying a volume or multi-volume set corresponding to each backup, each backup being stored on the corresponding volume or set of volumes. The method also includes determining a number of sequential access media devices available for use. In accordance with the example method, the plurality of objects may be sorted according to the size of the volume or set of volumes corresponding to each of the identified objects. The method further includes recovering the objects in the order in which they were sorted.

Abstract: A method, system, and apparatus for secure programmable addressing is provided by relocating functions within a multifunctional chip to be distributed across multiple logical partitions and maintaining security over the distribution mechanism. In one embodiment, this invention is used by a data processing system including a system processor connected to a plurality of operating system instances that are allocated individual system functions. Using logical partitioning, each operating system instance's access is limited to its own partition. Address buses to system functions are manipulated to make the functions appear at appropriate memory locations expected by the operating system instances. Accordingly, an inverter can be inserted on the address bus to change the address to a given distance in memory safe from operating system accessibility, for example, a page boundary.

Abstract: A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

Abstract: A file memory stores data corresponding to identifiers of an allocated area in an identifier space. A first memory stores a basis position of the allocated area in the identifier space. A second memory stores a weight of the storage apparatus as a performance degree. A first decision unit decides a space width to divisionally allocate the identifier space with another storage apparatus by using the weight and a weight of another storage apparatus. Another storage apparatus allocates a neighboring area of the allocated area in the identifier space. A second decision unit decides the allocated area of an area between the basis position and a basis position of the neighboring area in the identifier space by using the space width.

Abstract: A method of respectively reading and writing data to and from a plurality of physical disk units in response to I/O requests from a host computing system includes establishing a logical disk group having a number of logical disk elements, mapping each of the logical disk elements to corresponding physical disk units, receiving from the host computing system an I/O request for data to select a one of the number of logical disk elements, accessing the physical disk unit corresponding to the selected one logical disk to access for the data, and transferring the accessed data to the host computing system.

Abstract: In one embodiment, a method of attestation involves a special mode of operation. The method comprises storing an audit log within protected memory of a platform. The audit log is a listing of data representing one or more software modules loaded into the platform. The audit log is retrieved from the protected memory in response to receiving an attestation request. Then, the retrieved audit log is digitally signed to produce a digital signature in response to the attestation request.

Abstract: Multiple non-blocking FIFO queues are concurrently maintained using atomic compare-and-swap (CAS) operations. In accordance with the invention, each queue provides direct access to the nodes stored therein to an application or thread, so that each thread may enqueue and dequeue nodes that it may choose. The prior art merely provided access to the values stored in the node. In order to avoid anomalies, the queue is never allowed to become empty by requiring the presence of at least a dummy node in the queue. The ABA problem is solved by requiring that the next pointer of the tail node in each queue point to a “magic number” unique to the particular queue, such as the pointer to the queue head or the address of the queue head, for example. This obviates any need to maintain a separate count for each node.

Abstract: Methods and apparatus are disclosed for determining if a user-defined software function is a memory allocation function during compile-time. The methods and apparatus determine if a user-defined function returns a new memory object every time the user-defined function is invoked. In addition, the methods and apparatus determine if the memory objects created by the user-defined function are available outside the scope of the user defined function. If the user-defined function returns a new memory object every time the user-defined function is invoked, and the memory objects created by the user-defined function are not available outside the scope of the user defined function, then the user-defined function is determined to be a memory allocation function. Otherwise, the user-defined function is determined to be a non-memory allocation function.

Abstract: Methods, systems, and articles of manufacture consistent with the present invention coordinate distribution of shared memory to threads of control executing in a program by using a cooperative synchronization protocol. The protocol serializes access to memory by competing threads requesting assignment of memory space, while allowing competing threads that have already been assigned memory space, to share access to the memory. A designated area of memory assigns the memory to requesting threads. The protocol is an application level entity and therefore does access the operating system to serialize the memory allocation process.

Abstract: A computer system acquires mapping information of data storage regions in respective layers from a layer of DBMSs to a layer of storage subsystems, grasps correspondence between DB data and storage positions of each storage subsystem on the basis of the mapping information, decides a cache partitioning in each storage subsystem on the basis of the correspondence and sets the cache partitioning for each storage subsystem. When cache allocation in the DBMS or the storage subsystem needs to be changed, information for estimating the cache effect due to the change in cache allocation acquired by the DBMS is used for estimating the cache effect in the storage subsystem.

Abstract: A CPU determines whether the intended use of the image data to be stored in a plurality of HDDs has a first-type purpose, which requires storing temporarily stored image data for carrying out output processing of the image data, or a second-type purpose, which requires long-term preservation of the image data. If the first-type intended use is determined, a first-type mode for saving is selected, wherein the image data to be stored are divided and each divided set of image data is stored into one HDD. If the second-type intended use is determined, a second-type mode for saving is selected, wherein the same image data part is saved in a plurality of storage means.

Abstract: The present invention relates to computer systems and methods for providing a memory buffer for use with native and platform-independent software code. In a particular embodiment, the method includes providing a first software program compiled to platform-independent code for execution in a first process of the computer system, providing a second software program compiled to native code for execution in a second process of the computer system, and sending a message from the first process to the second process to request a memory buffer. In another particular embodiment, the computer system includes a processor and a memory. The computer system includes a first process to execute a first software program coded in a safe language, a second process to execute a second software program coded in an unsafe language, and an inter-process communication mechanism that allows data message communication between the first process and the second process.

Abstract: In a first aspect, a first method is provided for allocating memory bandwidth. The first method includes the steps of (1) assigning a fixed priority of access to the memory bandwidth to one or more direct memory access (DMA) machines; and (2) assigning a programmable priority of access to the memory bandwidth to a processing unit. The programmable priority of the processing unit allows priority allocation between the one or more DMA machines and the processing unit to be adjusted dynamically. Numerous other aspects are provided.

Abstract: A controller-driver, a method of driving the controller-driver, and a method of processing image data enabling scroll or other various functions without adding a storage capacity of a display memory nor increasing power consumption. A built-in display memory having a capacity of one frame (H pixels×V pixels×the number of bits) is partitioned into a plurality of memories according to an image type. High order bits are then stored in a first display memory 7a and high order bits of the next frame or low order bits are stored in a second display memory 7b by using a first selector 8 to a third selector 10 controlled by a memory control circuit 6 before they are read out. Thereby, high-level image data of one frame can be displayed when the scroll function is not used and image data of a plurality of frames can be displayed without accessing an image drawing unit 1 when the scroll function is used, thereby reducing power consumption.

Abstract: A method, apparatus, and system for implementing off-chip cache memory in dual-use static random access memory (SRAM) memory for network processors. An off-chip SRAM memory store is partitioned into a resizable cache region and general-purpose use region (i.e., conventional SRAM use). The cache region is used to store cached data corresponding to portions of data contained in a second off-chip memory store, such as a dynamic RAM (DRAM) memory store or an alternative type of memory store, such as a Rambus DRAM (RDRAM) memory store. An on-chip cache management controller is integrated on the network processor. Various cache management schemes are disclosed, including hardware-based cache tag arrays, memory-based cache tag arrays, content-addressable memory (CAM)-based cache management, and memory address-to-cache line lookup schemes. Under one scheme, multiple network processors are enabled to access shared SRAM and shared DRAM, wherein a portion of the shared SRAM is used as a cache for the shared DRAM.

Abstract: A method and apparatus for testing cache coherency in a multiprocessor data processing arrangement. Selected values are written to memory by a plurality of threads, and consistency of the values in the memory with the values written by the plurality of threads is verified. Performance characteristics of the data processing system are measured while writing the values, and in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads are selectively adjusted.

Abstract: In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.

Abstract: A basic input/output system (BIOS) for use in a computer system having a plurality of processors is described. The BIOS is embodied in a computer readable medium as computer program instructions which are operable to facilitate substantially simultaneous operation of the plurality of processors. According to one embodiment, the processors are simultaneously enabled to test of different portions of the system memory.

Abstract: A plurality of processors share a device using a common PCI bus. Each processor includes a PCI addressable memory area where data sent to or received from the device is stored. Each processor includes a unique identifier and also includes a PCI controller for accessing the PCI bus. Data is sent from a processor to the device by writing the data to the PCI addressable memory area and signaling the device using the processor's unique identifier. The device determines the memory address corresponding to the processor's unique identifier and reads the data. The device sends data to a processor by writing the data to the PCI addressable memory area and signaling the processor using a PCI mailbox assigned to the device and included in the processor's PCI controller. Device parameters are sent by the processors to the device during initialization and the device determines whether a parameter conflict exists.

Abstract: Various embodiments of a method and apparatus for implementing multiple transaction translators that share a single memory in a serial hub are disclosed. For example, in one embodiment, a USB (Universal Serial Bus) hub may include a shared memory device, at least one faster data handler coupled to transfer data between the shared memory device and a faster port, and several slower handlers each coupled to transfer data between the shared memory device and a respective one of several slower ports.