Abstract: A method, computer program product and computer system for virtualizing an SAS storage adapter, so as to allow logical partitions of a computer system to share a storage device. The method, computer program product and computer system includes assigning a logical storage adapter to an operating system of each of the logical partitions; creating a mapping from each of the logical partitions to a set of logical blocks in the storage device; and configuring the logical storage adapter using a hypervisor, so that a select partition can access a select set of logical blocks that the select partition is allowed to access.

Abstract: Migration management is provided for a shared memory logical partition migrating from a source system to a target system. The management approach includes managing migration of the logical partition from the source system to the target system by: transferring a portion of logical partition state information for the migrating logical partition from the source system to the target system by copying at the source system contents of a logical page of the migrating logical partition into a state record buffer for forwarding to the target system; forwarding the state record buffer to the target system; and determining whether the migrating logical partition is suspended at the source system, and if not, copying at the target system contents of the state record buffer to paging storage of the target system, the paging storage being external to physical memory managed by a hypervisor of the target system.

Abstract: Automated paging device management is provided for a shared memory partition data processing system. The automated approach includes managing a paging storage pool defined within one or more storage devices for holding logical memory pages external to physical memory managed by a hypervisor of the processing system. The managing includes: responsive to creation of a logical partition within the processing system, automatically defining a logical volume in the paging storage pool for use as a paging device for the new logical partition, the automatically defining occurring absent use of a filesystem, with the resultant paging device being other than a file in a filesystem; and automatically specifying the logical volume as a paging space device for the new logical partition and binding the paging space device to the new logical partition, wherein the logical volume is sized to accommodate a defined maximum memory size of the new logical partition.

Abstract: Transparent hypervisor pinning of critical memory areas is provided for a shared memory partition data processing system. The transparent hypervisor pinning includes receiving at a hypervisor a hypervisor call initiated by a logical partition to register a logical memory area of the logical partition with the hypervisor. Responsive to this hypervisor call, the hypervisor transparently determines whether the logical memory is a critical memory area for access by the hypervisor. If the logical memory area is a critical memory area, then the hypervisor automatically pins the logical memory area to physical memory of the shared memory partition data processing system, thereby ensuring that the memory area will not be paged-out from physical memory to external storage, and thus ensuring availability of the logic memory area to the hypervisor.

Abstract: Hypervisor managed memory paging is provided in a data processing system having multiple logical partitions. The data processing system includes a shared memory pool defined within physical memory. The shared memory pool includes a volume of physical memory with dynamically adjustable sub-volumes or sets of physical pages associated with the multiple logical partitions. Each sub-volume or set is associated with a particular logical partition and includes mapped logical memory pages for that logical partition. A hypervisor memory manager interfaces the multiple logical partitions and the shared memory pool, and manages access to logical memory pages within the shared memory pool. The hypervisor memory manager further manages page-out and page-in of logical memory pages from the shared memory pool to one or more external paging devices. This page-out and page-in managing by the hypervisor memory manager is transparent to the multiple logical partitions.

Abstract: In response to a hypervisor page fault for memory that is not resident in a shared memory pool, an I/O paging request is sent to an external storage paging space. In response to a paging service partition encountering an I/O paging error, a paging failure indication is sent to the hypervisor. A simulated machine check interrupt instruction is sent from the hypervisor to the shared memory partition and a machine check handler obtains control. The machine check handler performs data analysis utilizing an error log in an attempt to isolate the I/O paging error to a process or a set of processes in the shared memory partition. The process or set of processes associated with the I/O paging error, or the shared memory partition itself, may be terminated. Finally, the shared memory partition may clear or initialize the page associated with the I/O paging error.

Abstract: Controlled partition shut-down is provided within a shared memory partition data processing system including a shared memory partition, a paging service partition, a hypervisor and a shared memory pool within physical memory. The hypervisor manages access to logical pages within the pool and page-out of pages from the pool to external paging storage via the paging service partition. A respective paging service stream exists between the paging service partition and hypervisor for each shared memory partition, with each stream including a stream state. The control method includes: responsive to a shut-down initiating event, notifying the paging service partition to shut down, and determining whether a shared memory partition is currently active, and if so, signaling the hypervisor to complete paging activity for the active memory partition and waiting for its stream state to enter a suspended or a completed state before automatically shutting down the paging service partition.

Abstract: Dynamic control of memory affinity is provided for a shared memory logical partition within a shared memory partition data processing system having a plurality of nodes. The memory affinity control approach includes: determining one or more home node assignments for the shared memory logical partition, with each assigned home node being one node of the plurality of nodes of the system; determining a desired physical page level per node for the shared memory logical partition; and allowing the shared memory partition to run and using the home node assignment(s) and its desired physical page level(s) in the dispatching of tasks to physical processors in the nodes and in hypervisor page memory management to dynamically control memory affinity of the shared memory logical partition in the data processing system.

Abstract: A single chip network controller for interfacing between a physical network and a processing system on the media side of the network controller. The network controller includes a physical layer for receiving data for transmission to the network and encoding the received data for transmission thereto and for receiving data from the network, and for receiving data from the network and decoding the received data. A media layer is provided for interfacing with the processing system for receiving data from the processing system for interface with the physical layer for encoding and transmission thereof and for receiving decoded data from the physical layer and providing access thereto by the processing system. An on-chip non-volatile memory is provided having a first portion associated with configuration information for configuring the operation of the physical layer and the media layer, and a second portion thereof that is accessible by the processing system on the media side of the network controller.

Abstract: The disclosed embodiments relate to an optimized memory registration mechanism that may comprise an upper layer protocol that associates I/O buffers with memory regions and that manages steering tags. The memory regions may be associated with a translation page table. The upper layer protocol may allocate one of the steering tags associated with at least one of the memory regions for a memory operation.

Abstract: A directory of each node in a shared memory multiprocessor is made up of directory entries each including one or more directory bits indicating whether the cache memory of another node stores a copy of a part of a memory region group of the main memory of one node. The memory region group includes memory regions having the same memory address portion including a cache index portion. Each node is assigned one of the directory bits. When accessing the main memory, the node checks whether the directory bits of the directory entry corresponding to a memory region to be accessed are set to a predetermined value, and if one or more of the directory bits of the directory entry are set to the predetermined value, an access address is multicast or broadcast to other nodes to perform coherency control.

Abstract: In a multi-processor system, counting snoop results bottlenecks the broadcast-based snoop protocol. The directory-based protocol delays the latency when remote node caches data. There is a need for shortening the memory access latency using a snoop and cache copy tag information. When the local node's cache copy tag information is available, the memory access latency can be shortened by omitting a process to count snoop results. When memory position information is used to update the cache copy tag during cache replacement, it is possible to increase a ratio to hit a copy tag during reaccess from the local node.

Abstract: A memory administrating method of administrating a memory divided into plural regions each of which consists of consecutive memory addresses, where the method includes the steps of: providing each region of the plural regions with usage information; and when releasing a release target region currently in use, determining usage of the release target region based on the usage information of at least one of neighboring regions positioned before and after the release target region.

Abstract: Techniques that may be utilized in various computing environments are described. In one embodiment, a buffer is configured dynamically, e.g., during runtime. Other embodiments are also disclosed.

Abstract: Systems, methods, apparatus and software can combine information about host access to virtualization functionality and virtualization functionality access to storage, use this information in decisions pertaining to high availability of virtualization in an SAN. Upon detection of the partitioning of a SAN fabric, accessibility information is gathered. That information is analyzed to uncover potential failover scenarios, orchestrate such failovers, and in some cases select best case solutions from among several possible solutions based on access prioritization criteria (e.g., defined priority, maximum access, maximum I/O, etc.).

Abstract: A method and device for varying the size of partitioned areas of a shared memory is disclosed. The present invention resets the size of partitioned areas by expanding the size of a shared area when data that is larger than the writable area of the shared area is to be written, after the storage area of a memory unit is partitioned to a plurality of partitioned areas by a main control unit. The memory unit is coupled with a main control unit and a supplementary control unit through independent ports. With the present invention, the data communication time between control units for processing data can be minimized, and the operation speed of each control unit can be optimized.

Abstract: A data development device includes an LZ77 development part expanding data by referring to a dictionary including previous development result when data same to previous data is output, a PNG inverse filter performing arithmetic operation on development result of the LZ77 development part and image data previously output and outputting the image data, and a shared memory including an internal dictionary area and a line data area, the internal dictionary area storing previous development result referred by the LZ77 development part and the line data area storing the image data which is previously output and used by the PNG inverse filter. The shared memory has capacity for the internal dictionary area and capacity for the line data area set based on analysis result analyzing input data.

Abstract: Coordination between multiple processors presents a set of difficult problems, since most processors are not designed for multi-processing, but for multi-tasking. Additionally, CPUs are increasingly limited by the memory bandwidth bottleneck. The iMEM architecture addresses the multi-processing problem, by simplifying processor access, and the memory bandwidth problem, by distributing intelligence across the memory system. ASCII encoding of task structure and instructions addresses compiler complexities.

Abstract: An improved system and method for removing a storage server in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Storage servers may then be removed and column chunks may be redistributed among the remaining storage servers in the column chunk data store.

Abstract: A system, method and computer program product for providing a shared memory translation facility. The method includes receiving a request for access to a memory address from a requestor at a configuration, the receiving at a shared memory translation mechanism. It is determined if the memory address refers to a shared memory object (SMO), the SMO accessible by a plurality of configurations. In response to determining that the memory address refers to the SMO, it is determined if the configuration has access to the SMO. In response to determining that the configuration has access to the SMO, the requestor is provided a system absolute address for the SMO and access to the SMO. In this manner direct interchange of data between the plurality of configurations is allowed.

Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

Abstract: An information storage apparatus capable of setting the number and sizes of partitioned areas resulting from partitioning a memory area based on a user's intention is provided. For this purpose, an information storage apparatus having a plurality of partitioned areas of different security levels in a memory area is provided with an area control section that controls addresses of partitioned areas in the memory area, an area update condition control section that controls update conditions when the number or sizes of partitioned areas are updated, an area update decision section that decides whether a partition request requesting updating of the number or sizes of partitioned areas satisfies the update conditions and an area update section that executes, when the partition request satisfies the update conditions, updating of the partitioned areas in the memory area according to the partition request.

Abstract: A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

Abstract: A system and method for implementing a CPU/Network Device Interface that reduces the CPU involvement in managing the interface. New data structures in shared memory that are either read-only or write-only by CPU allow the CPU to efficiently utilize techniques such as write-posting and cache prefetching. Additionally, hardware-assisted packet transmission and high-level packet flow control reduce the burden on the CPU. A fair allocation system assures fair access to the receive interface by multiple line cards.

Abstract: A computer system is provided, wherein a storage device having a flash memory as the main medium is given a cache memory with a high hit rate even in a small capacity and less access overheads, high-speed writing to the flash memory is attained, and the number of rewriting is reduced: wherein a processing device, a cache memory and a flash memory for data via the cache memory to be written in response to a request from the processing device are provided; and a line size of an entry to the cache memory is 1/N (note that N is 2 or larger integer) of an actual page size as a writing unit of the flash memory.

Abstract: The disclosed embodiments may relate to memory window access, which may include a memory window and protection domain associated with a process. The memory window access setting or bit may also allow a plurality of memory windows to be associated with a protection domain for a process. The memory window access setting or bit may allow access to the memory window to be for the queue pairs in a certain protection domain or a designated queue pair.

Abstract: The invention relates to a memory unit with at least two memory areas for storing data, first terminals for accessing data within the memory areas, and second terminals for accessing data within the memory areas. To provide multi-purpose access to the memory, the memory unit provides at least two access control means for providing selectively sole addressing and accessing data through one of the terminals, or individual addressing and accessing data through each of the terminals, respectively.

Abstract: An interface unit 20 assigns different SDRAMs 1 and 2 to adjacent drawing blocks in a frame-buffer area. In processing that extends across the adjacent drawing blocks, active commands, for example, are issued alternately to the SDRAMs 1 and 2 to reduce waiting cycles resulting from the issue interval restriction. Furthermore, since individual clock enable signals CKE1 and CKE2 are output to the SDRAMs 1 and 2 so that burst transfers of the SDRAMs 1 and 2 can be stopped individually, no cycle is necessary to stop the burst transfers.

Abstract: The present invention decreases the burden of operation required for specifying the continuity status and the cause of failure of a network storage device. A host computer accepts the specification of the device identifier, that is an identifier of the network storage device in the host protocol which positions in a higher hierarchy than the network communication protocol, and a volume identifier, that is an identifier of the volume. Then based on the specified device identifier, the host computer specifies the network identifier, that is an identifier of the network storage device in the network communication protocol. And continuity is confirmed in the network communication protocol in which the specified network identifier is the destination. Also continuity is confirmed in the host protocol in which the device identifier is the destination. And the volume specified by the volume identifier is accessed.

Abstract: A method and apparatus for partitioning a shared cache of a chip multi-processor are described. In one embodiment, the method includes a request of a cache block from system memory if a cache miss within a shared cache is detected according to a received request from a processor. Once the cache block is requested, a victim block within the shared cache is selected according to a processor identifier and a request type of the received request. In one embodiment, selection of the victim block according to a processor identifier and request type is based on a partition of a set-associative, shared cache to limit the selection of the victim block from a subset of available cache ways according to the cache partition. Other embodiments are described and claimed.

Abstract: A disk array device having a plurality of hard disk units has a large-capacity memory mounted on a controller module which controls the whole device. The large-capacity memory has a system area managed by an OS and a cache area serving as a cache memory, and in addition, it has a table area which stores management/control information of the device and whose area size is changeable at an arbitrary instance. Therefore, it is possible to change the table area according to the state of the device in an active state without ON/OFF of a power source, so that an area not in use in the table area can be released for use as the cache memory. This makes it possible to appropriately varying the sizes of the table area and the cache area in an active state while the device is in operation, thereby realizing effective use of the large-capacity memory.

Abstract: In one aspect, the issues of events that may impact one or more partitions of sub-socket partitioning in one or more sockets can be handled. Specifically, events for partitions can be handled in a socket with sub-socket partitioning, wherein the events may include reset, interrupts, errors and reliability, availability, and serviceability (RAS) management.

Abstract: Dynamically allocated memory is managed in real-time. This real-time management capability enables an invalid access of the dynamically allocated memory to be detected at the time the invalid access occurs, rather than at some later point in time. This real-time management capability can be dynamically activated/deactivated on a per process basis.

Abstract: The storage enclosure includes a number of storage drives, each of which is physically coupled to each of two controllers in the storage enclosure. A memory location associated with the storage enclosure includes a value. The value provides an indicator for grouping the storage drives with one of the two controllers and disabling communications between each storage controller and the storage drives not associated with the controller.

Abstract: In order to access a distributed file system (DFS) of the present invention using a conventional protocol such as the one for an NFS or a CIFS without making a modification on a client side, a gateway unit for receiving a conventional protocol and performing processing in conformity the protocol is provided for a DFS server. The gateway unit emulates a directory structure in a file system such as the NFS or CIFS. When the DFS is a write-once read-many file system, update processing is converted into processing for creating a new generation file, and reference processing is converted into access to a latest generation file in a generation-managed file group. The gateway unit then accesses a DFS file via a DFS processing unit.

Abstract: A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file control memories which store translation control data; groups of disk drives; disk control processors; disk interface units which connect the groups of disk drives and the disk control processors; cache memories; and inter-processor communication units. The storage logically partitions these devices to cause the partitioned devices to operate as two or more virtual NASs.

Abstract: An improved system and method for recovery from failure of a storage server in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Storage servers may then fail and column chunks may be recreated from parity column chunks and redistributed among the remaining storage servers in the column chunk data store.

Abstract: A disc array unit manages a shared memory as a plurality of shared memory blocks, each including a group of cache pages, performs cache control on these cache pages through use of least recently used (LRU) links, and provides an unavailable link as an LRU link to indicate that an area is not available for use as a cache page. When the shared memory block is used not as a cache memory but for another use, the shared memory block is prevented from being used as a cache memory by re-linking all the cache pages belonging to the shared memory block from an LRU link to such unavailable links individually.

Abstract: A device and a method for simulating a hard disk are disclosed. The device has a core logic chip, a main memory module and a setting module. The setting module is used to set the main memory module to have a memory access area and a hard disk access area. The core logic chip has a memory controller and a conversion interface controller for controlling data reading of the memory access area and the hard disk access area, respectively. When the core logic chip receives a read/write signal sent to the main memory module from a computer system, it determines whether this read/write signal is a memory read/write signal or a hard disk read/write signal. If the read/write signal is for memory, it is sent to the memory controller; if the read/write signal is for hard disk, it is sent to the conversion interface controller.

Abstract: A semiconductor integrated circuit device includes a plurality of internal memories, a main processor, which constitutes a first processing unit having a codec function, and a video interface and graphics processor, which constitute a second processing unit for video display processing. The semiconductor integrated circuit device operates while being connected to a CPU, which is an external processing unit, and an external memory. The semiconductor integrated circuit device is provided with a memory configuration controller for controlling the memory allocation to the first, the second, and the external processing unit in accordance with an application.

Abstract: A storage includes: host interface units; file control processors which receives a file input/output request and translates the file input/output request into a data input/output request; file control memories which store translation control data; groups of disk drives; disk control processors; disk interface units which connect the groups of disk drives and the disk control processors; cache memories; and inter-processor communication units. The storage logically partitions these devices to cause the partitioned devices to operate as two or more virtual NASs.

Abstract: A split hardware transaction may split an atomic block of code to be executed using multiple hardware transactions, while logically taking effect as a single atomic transaction. A split hardware transaction may use software to combine the multiple hardware transactions into one logically atomic operation. In some embodiments, a split hardware transaction may allow execution of atomic blocks including non-hardware-transactionable (NHT) operations without resorting to exclusively software transactions. A split hardware transaction may maintain a thread-local buffer logs all memory accesses performed by the split hardware transaction. A split hardware transaction may use a hardware transaction to copy values read from shared memory locations into a local memory buffer.

Abstract: Split hardware transaction techniques may support execution of serial and parallel nesting of code within an atomic block to an arbitrary nesting depth. An atomic block including child code sequences nested within a parent code sequence may be executed using separate hardware transactions for each child, but the execution of the parent code sequence, the child code sequences, and other code within the atomic block may appear to have been executed as a single transaction. If a child transaction fails, it may be retried without retrying the parent code sequence or other child code sequences. Before a child transaction is executed, a determination of memory consistency may be made. If a memory inconsistency is detected, the child transaction may be retried or control may be returned to its parent. Memory inconsistencies between parallel child transactions may be resolved by serializing their execution before retrying at least one of them.

Abstract: Garbage collection in heterogeneous multiprocessor systems is provided. In some illustrative embodiments, garbage collection operations are distributed across a plurality of the processors in the heterogeneous multiprocessor system. Portions of a global mark queue are assigned to processors of the heterogeneous multiprocessor system along with corresponding chunks of a shared memory. The processors perform garbage collection on their assigned portions of the global mark queue and corresponding chunk of shared memory marking memory object references as reachable or adding memory object references to a non-local mark stack. The marked memory objects are merged with a global mark stack and memory object references in the non-local mark stack are merged with a “to be traced” portion of the global mark queue for re-checking using a garbage collection operation.

Abstract: A method for recovering lost cache capacity in a multi core chip having at least one defective core including identifying the cores contained in the chip that are viable cores and identifying at least one core contained in the chip that is defective. The method also includes identifying the cache memory local to the defective core and determining a redistribution of the cache resources local to the at least one defective core among the viable cores. The method also features dividing the cache memory local to the at least one defective core according to the redistribution determination and determining the address information associated with the cache memory local to the at least one defective core. The method also features providing the address information associated with the cache memory associated with the defective core to at least one of the viable cores, facilitating the supplementation of the cache memory local to the viable cores with the cache memory associated with the defective core.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, determine an application server partition based on the context of a request from a client, and send the request to the application server partition if the application server partition exists. If the application server partition does not exist, the application server partition is created based on a creation rule, and the request is then sent to the application server partition if the request context is valid, as determined by a validation rule. Periodically, a remove rule is compared to a condition of the application server partition, and if the remove rule is met, the application server partition is removed. The condition may include, in various embodiments, the usage time and frequency of use of the application server partition or performance criteria. In an embodiment, the validation rule, the creation rule, and the remove rule may change over time.

Abstract: A memory mapping unit requests allocation of a remote memory to memory mapping units of other processor nodes via a second communication unit, and requests creation of a mapping connection to a memory-mapping managing unit of a first processor node via the second communication unit. The memory-mapping managing unit creates the mapping connection between a processor node and other processor nodes according to a connection creation request from the memory mapping unit, and then transmits a memory mapping instruction for instructing execution of a memory mapping to the memory mapping unit via a first communication unit of the first processor node.

Abstract: A storage system is provided that includes a plurality of storage devices and a data structure, accessible to the storage system, that includes a plurality of records corresponding to a plurality of network devices that are coupled to the storage system. Each record includes configuration data that identifies each of the plurality of storage devices to which data access by a respective one of the plurality of network devices is authorized. Each record may further include visibility data that identifies whether certain types of non-data access, such as requests for general information relating to a respective storage device, by a respective one of the plurality of network devices is permitted, even though data access to the respective storage device by the respective one of the plurality of network devices is not authorized.

Abstract: A data storage device has a data storage medium. A data storage capacity of the data storage device is divided into slices. Each slice has a set of sectors. Data storage device firmware is configured to store copies of a system image in the slices on the data storage device. Each of the slices stores a different copy of the system image.

Abstract: A computer system acquires mapping information of data storage regions in respective layers from a layer of DBMSs to a layer of storage subsystems, grasps correspondence between DB data and storage positions of each storage subsystem on the basis of the mapping information, decides a cache partitioning in each storage subsystem on the basis of the correspondence and sets the cache partitioning for each storage subsystem. When cache allocation in the DBMS or the storage subsystem needs to be changed, information for estimating the cache effect due to the change in cache allocation acquired by the DBMS is used for estimating the cache effect in the storage subsystem.