Abstract: Disclosed is a method for automating testing tasks which would otherwise have to be done manually using actual hardware by providing the capability to dynamically create many types of storage devices with different storage media, thus eliminating the need to have test machines with the actual hardware. In one embodiment a virtual storage device driver can be implemented that can be used to simulate various storage devices such as CD-ROM, CD-R, CD-RW, removable disk drives and fixed disk drives. Manual testing tasks such as testing autoplay functionality when a CD is inserted, testing CD burning, and testing CD audio playback can then be automated.

Abstract: A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

Abstract: Consistency for replicating data storage subsystem configurations in accordance with a “golden” configuration file. A data storage subsystem comprises a blade system with a plurality of slots, the blade system configured to support a plurality of blades and a storage system, each arranged in a predetermined slot of the blade system. The storage system arranges a logical configuration of the server blades in accordance with a “golden” configuration file. The server blade slot versus WWN information is collected and provided to the storage system. The storage system converts the “golden” configuration file slot information to WWNs. The server blades are enabled for access to said storage system as they log on with WWNs in accordance with the “golden” configuration file.

Abstract: A system, method and computer program product for efficient sharing of memory between first and second applications running under first and second operating systems on a shared hardware system. The hardware system runs a hypervisor that supports concurrent execution of the first and second operating systems, and further includes a region of shared memory managed on behalf of the first and second applications. Techniques are used to avoid preemption when the first application is accessing the shared memory region. In this way, the second application will not be unduly delayed when attempting to access the shared memory region due to delays stemming from the first application's access of the shared memory region. This is especially advantageous when the second application and operating system are adapted for real-time processing. Additional benefits can be obtained by taking steps to minimize memory access faults.

Abstract: A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Abstract: Provided are a method, system and program for dumping data in processing systems to a shared storage. A plurality of processing systems receive a signal indicating an event. Each of the processing systems write data used by the processing system to a shared storage device in response to receiving the signal, wherein each processing system writes the data to the shared storage device.

Abstract: A multiprocessor computer system has a plurality of processing nodes which use processor state information to determine which coherent caches in the system are required to examine a coherency transaction produced by a single originating processor's storage request. A node of the computer has dynamic coherency boundaries such that the hardware uses only a subset of the total processors in a large system for a single workload at any specific point in time and can optimize the cache coherency as the supervisor software or firmware expands and contracts the number of processors which are being used to run any single workload. Multiple instances of a node can be connected with a second level controller to create a large multiprocessor system. The node controller uses the mode bits to determine which processors must receive any given transaction that is received by the node controller.

Abstract: A method, system and computer-readable media for exchanging information via an electronics communications are provided. A computer includes a memory and an access logic are bi-directionally communicatively coupled with a controller. The memory includes an open memory area and a partitioned memory area, wherein the open area available is for use by the controller upon an initial sale, installation or start-up. The access logic is configured to enable access to the partitioned memory by the controller after a receipt by the access logic of an access purchase confirmation. The computer may be coupled with an electronics communications network, such as the Internet, and the access purchase confirmation may be delivered via the electronics communications network. The access to partitioned area may optionally be enabled on a temporary or a segmented basis.

Abstract: A method of building a computer system is provided. The method comprises determining an average memory storage per virtual machine, determining an average number of virtual machines per host computer, and determining an amount of memory storage per memory pool. The method also comprises determining a maximum number of host computers per memory pool based on the average memory storage per virtual machine, the average number of virtual machines per host computer, and the amount of memory storage per memory pool. The method also includes assembling the appropriate number of host computers and memory storage, organized around memory pools, to handle a specific number of virtual machines.

Abstract: Two data operations, such as write operations, may be processed at a same time in which the two write operations operate on a same address range span. A first of the write operations may write to the first track and the last track in the span but not tracks therebetween. When processing the first write operation, a lock for the first track is obtained and the data is written to the first track data. A lock for the last track is obtained and it is determined whether all tracks between the first and last tracks are unlocked. If so, data is written to the last track. If not, steps of releasing and then reacquiring the lock for the last track and determining whether intervening tracks are locked are repeated until the intervening tracks are not locked. The last track is then written.

Abstract: A method for efficiently managing memory resources in a computer system having a graphics processing unit that runs several processes simultaneously on the same computer system includes using threads to communicate that additional memory is needed to avoid termination or less than optimal performance of a process. If the request indicates that termination will occur then other processes will reduce their memory usage to a minimum to avoid termination but if the request indicates that the process will not run optimally then the other processes will reduce their memory usage to 1/N where N is the count of the total number of running processes. The apparatus includes a computer system using a graphics processing unit and processes with threads that can communicate directly with other threads and with a shared memory which is part of the operating system memory.

Abstract: Methods for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.

Abstract: A photographic printing system includes a film reader for reading photographic image of a photographic film, a printer for printing the photographic image on an image recording medium based on photographic image data obtained through the film reader, a writer for writing at least the photographic image data in a loaded optical disc of the WORM (Write Once Read Many) type, and a controller for controlling the writing process of the writer. The controller allows writing, in the optical disc, of both the image data and a display processing program for displaying the image data written in the optical disc on a monitor when the optical disc has no data pre-written therein and allows writing, in the optical disc, of the image data when the optical disc has such display processing program pre-written therein.

Abstract: An apparatus for serializing concurrent requests to multiple processors includes a signal merging tree structure and a traversal mechanism. The tree structure has a root node and leaf nodes for connecting a data consumer to the root. The tree structure serializes concurrent requests in the presence of race conditions, and connects each request producer from among the processors to a respective leaf node. The mechanism enables a producer to transmit a signal from a corresponding leaf node to the consumer at the root node by setting all nodes on a path from the leaf node to the root node to a Boolean true. The mechanism enables the consumer to trace signal submissions of the producers such that submission traversals by the producers and trace traversals by the consumer can be concurrently performed to allow data races between signal submissions by producers and between signal submissions by producers and the consumer.

Abstract: Methods for dynamically allocating memory in a multiprocessor computer system such as a non-uniform memory access (NUMA) machine having distributed shared memory. The methods include allocating memory by specified node, memory class, or memory pool in response to requests by the system (kernel memory allocation) or a user (application memory allocation). Through these methods memory is allocated more efficiently in a NUMA machine. For example, allocating memory on a specified node in a NUMA machine, such as the same node on which a process requiring the memory is running, reduces memory access time. Allocating memory from a specified memory class allows device drivers with restricted DMA ranges to operate with dynamically allocated memory. Other benefits of these methods include minimizing expensive remote-memory accesses using a distributed reference count mechanism and lock-free cache access.

Abstract: A method of implementing virtualization involves an improved approach to resource management. A virtualizing subsystem is capable of creating separate environments that logically isolate applications from each other. Some of the separate environments share physical resources including physical memory. When a separate environment is configured, properties for the separate environment are defined. Configuring a separate environment may include specifying a physical memory usage cap for the separate environment. A global resource capping background service enforces physical memory caps on any separate environments that have specified physical memory caps.

Abstract: A memory-sharing system device has a shared memory, divided into forward-direction and backward-direction memory areas; a first processor inputting transfer data in the forward direction, writing the data to the forward-direction memory area, reading transfer data in the backward direction from the backward-direction memory area and outputting the data; and a second processor for transferring data in the back-ward direction. The first or second processor sets memory release criteria for the forward-direction and backward-direction memory areas respectively, and, when the used memory area reaches the memory release criterion, performs memory release processing. The first or second processor monitors the forward-direction and the backward-direction data transfer speed, changes the memory release criterion depending on the data transfer speed.

Abstract: In an embodiment, data is partitioned into partitions, which are divided into levels. The levels are ordered by creation times of the levels. A request is received at a current partition, which includes a key that identifies a field in a record and a value for the key. A determination is made whether the value exists in the field in the current partition. If the determination is false, a message is sent from the current partition to a next-older partition, and the message instructs the next-older partition to move the record with the value from the next-older partition to the current partition. If the determination is true, the record with the value in the field is moved from the current partition to a next-newer partition if the next-newer partition sent the request, and the record is deleted from the current partition.

Abstract: A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.

Abstract: An improved system and method for importing update data in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Update data may then be incrementally imported as separate column chunks that may later be merged with the column chunks of the partitioned data table.

Abstract: An information handling system includes a processor and a system memory coupled to the processor. The system has a plurality of persistent mass storage devices including first and second storage devices. A device controller includes a first port operably connected to the first storage device and a second port operably connected to the second storage device. The controller transfers data between system memory and the storage devices. System firmware includes instructions to configure the controller to define a first command list and frame information structure (FIS) associated with the first port and a second command list and FIS associated with the second port where the first and second command lists share a common block of system memory.

Abstract: Method and apparatus for managing memory logic is described. In one example, user logic, virtual port logic, and a processor are provided. The user logic is configured to provide allocation requests for the memory logic, access requests for the memory logic, and de-allocation requests for the memory logic. The virtual port logic is coupled to the user logic and the memory logic. The processor is coupled to the virtual port logic. The virtual port logic is configured to forward the allocation requests and de-allocation requests to the processor, and to process the access requests. The processor is configured to allocate space in the memory logic in response to the allocation requests and de-allocate space in the memory logic in response to the de-allocation requests.

Abstract: A microcomputer capable of reducing a board area, enhancing the security, and improving the usability is provided. A microcomputer to be used in a notebook PC is disclosed, in which programs of a keyboard/power management BIOS and a system BIOS are stored in a built-in flash memory ROM. In order to set read (R)/write (W) protect to the BIOSes stored in the flash memory ROM, a read/write protect setting register is provided, and at initial setting after the release of reset, flags of R/W permission, R permission/W prohibition, W permission/R prohibition, and R/W prohibition are set to this register by a central processing unit CPU. By doing so, it becomes possible to achieve protection such as the prevention of error writing of the BIOS and the like between a host machine and the flash memory ROM via a LPC bus.

Abstract: In one embodiment, a system is provided. The system includes a first client. The system also includes an analysis server coupled to the first client. The system further includes a first customer database of information coupled to the analysis server. The first customer database is to embody forecast data and to receive essentially real-time updates to the forecast data. The first customer database supports an OLAP cube associated with the analysis server.

Abstract: A system, method, and computer-usable medium for probing hypervisor tasks in an asynchronous environment. According to an embodiment of the invention, the partition firmware sends a request for data to the hypervisor. When the hypervisor receives the request for data, the hypervisor returns a taskID that identifies the task allocated to handle the request. Partition firmware records the taskID and a timestamp, which indicates the time in which the hypervisor received the request. A timer is set to measure the amount of time elapsed since the task ID was received by a requesting partition firmware. If the hypervisor has not provided the partition firmware with the requested data after a predetermined time period measured by the timer has elapsed, the partition firmware inquires about the status of the task associated with the taskID. If the task is still running, the partition firmware returns control of the partition to the operating system.

Abstract: A flash memory and a method for utilizing the same are disclosed. The method for utilizing a flash memory includes the steps of: a) providing a flash memory of a single chip; b) formatting the flash memory and marking bad blocks of the flash memory as a bad-block area free of reliably saved data; c) calculating a capacity of an available memory with the flash memory, wherein the available memory excludes the bad-block area of the flash memory; and d) dividing the available memory into a first storing memory and a second storing memory, wherein the first storing memory and the second storing memory have different capacities.

Abstract: Embodiments of a multi-processor platform including multiple, cooperating operating systems are described. Multiple operating systems, each of which may be of a different type or nature, run on different partitions of the multi-processor platform, yet coexist and cooperate. In various embodiments, different specialized operating systems, suitable for particular tasks, run on different partitions of the platform. In one embodiment, a host operating system, using a driver, boots and partitions a portion of the platform running other operating systems, and then communicates with, and shares work with, the other operating systems. In one embodiment, the multi-processor platform includes a host operating system and multiple specialized operating systems, such as real-time operating systems, operating alongside the host operating system. Other embodiments are described and claimed.

Abstract: A process and associated system comprise pre-allocating a portion of memory in a first processor based upon a control input and determining in a second processor if the portion of the pre-allocated memory can satisfy a memory allocation request. Further, if a portion of pre-allocated memory can satisfy a memory allocation request, the technique includes assigning the pre-allocated portion of memory to the allocation request. However, if a portion of pre-allocated memory cannot satisfy a memory allocation request, the technique includes allocating a portion of memory in the first processor to the allocation request.

Abstract: A storage device which limits the partition of the logical memory devices for computers in accordance with properties such as reliability. An access control approves an access only to the logical memory device which was partitioned referring to an access control table. An access control setting control renews the access control table so as to partition the assigned logical memory devices to the assigned computer when the assigned logical memory devices can be partitioned.

Abstract: A hardware Secure Processing Unit (SPU) is described that can perform both security functions and other information appliance functions using the same set of hardware resources. Because the additional hardware required to support security functions is a relatively small fraction of the overall device hardware, this type of SPU can be competitive with ordinary non-secure CPUs or microcontrollers that perform the same functions. A set of minimal initialization and management hardware and software is added to, e.g., a standard CPU/microcontroller. The additional hardware and/or software creates an SPU environment and performs the functions needed to virtualize the SPU's hardware resources so that they can be shared between security functions and other functions performed by the same CPU.

Abstract: A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of nodal memory is associated with each processor in the node. A processor may request additional memory, and the other processor(s) may grant or veto the request. If granted, the requested memory is added to the subdivision of the requesting processor. A processor can only access memory within its own subdivision. Preferably, each subdivision contains a daemon which monitors memory usage and generates requests for additional memory.

Abstract: A method, system and program are disclosed for automatically adjusting the allocation of a plurality of information processing system (IPS) resources among a plurality of logical partitions (LPARs). An LPAR is created on a first central processor complex (CPC) and a first LPAR identifier is generated. A configuration change manager is implemented on the LPAR to communicate changes in the LPAR's identifier to an automated resource manager (ARM). IPS resources are automatically allocated to the LPAR. If the LPAR is migrated a second CPC, a second LPAR identifier is similarly generated, resulting in an LPAR configuration change event. The ARM is notified that the migrated LPAR's identifier has changed and receives the changed LPAR identifier. Comparison operations are performed to determine whether the second LPAR identifier matches the first CPC. If not, resources allocated to the migrated LPAR are released for automated allocation to other LPARs comprising the first CPC.

Abstract: A method for controlling multiple access to partitioned areas of a shared memory and a digital processing apparatus having the shared memory are disclosed. According to embodiments of the present invention, the storage area of a shared memory is partitioned to a plurality of storage areas, and each processor accesses a storage area through each access port to store data and transfers an authority to access the pertinent storage area to the other processor, thereby allowing access by the other processor. With the present invention, the data communication time between the plurality of processors can be minimized, and the process efficiency of each processor can be optimized.

Abstract: One embodiment of the present invention provides a method and a system for tracking memory usage of tasks in a shared heap. The system performs a full garbage-collection operation on the shared heap, during which a base memory usage is determined for each task. The system then periodically samples task state during execution to generate an estimate of newly allocated memory for each task. The base memory usage and the estimate of newly allocated memory for each task are combined to produce an estimate of current memory usage for each task. This estimate of current memory usage is used to determine whether a task is likely to be violating a memory quota. If so, the system triggers a remedial action, which can include: a full garbage-collection operation; a generational garbage-collection operation; or generation of a signal which indicates that a memory quota violation has occurred.

Abstract: A method for determining volume size in a storage system, comprising the steps of receiving a request for a volume assignment from a client host; obtaining client host specification; obtaining storage system specification; based on the client host specification and storage system specification selecting a proper volume size; and assigning a virtual volume to the client host, the virtual volume having the selected proper volume size.

Abstract: Described is a technology by which a new volume or partition may be created on a disk, e.g., by running a shrink program and then reclaiming freed space. Shrink occurs online, while the user or system processes may be otherwise using the disk for reads and writes. Further, the technology operates while protecting snapshot versions of the volume. To shrink, upon receiving a request to shrink a volume to within a boundary, new allocations are restricted such that any allocation is to a volume area within the boundary. Data is moved from outside the boundary to within the boundary, and the shrink is committed when no volume data remains outside the boundary. A reduced-size volume or partition that does not include the specified region is committed when the data has been moved out of the specified region. A new volume or partition may be freed that corresponds to the region.

Abstract: A multiple computer system incorporating redundancy is disclosed. Data to be stored (A, B, C) is distributed (A1, A2, A3, . . . B1, B2, B3, . . . C1, C2, C3, . . . ) amongst a multiplicity of computers (M1, M2, . . . Mn). A parity form (P[A], P[B], . . . ) of the stored data is created by use of a reversible encoding process. The parity form data is preferably cycled amongst the various computers. In the event of failure of one of the computers the lost data can be re-generated.

Abstract: A rebuilder application operates on a dispersed data storage grid and rebuilds stored data segments that have been compromised in some manner. The rebuilder application actively scans for compromised data segments, and is also notified during partially failed writes to the dispersed data storage network, and during reads from the dispersed data storage network when a data slice is detected that is compromised. Records are created for compromised data segments, and put into a rebuild list, which the rebuilder application processes.

Abstract: Embodiments include methods, apparatus, and systems for snapshots in distributed storage systems. One method of software execution includes using a version tree to determine what data blocks are shared between various storage nodes in the version tree in order to create a clone or a snapshot of a storage volume in a distributed storage system that uses quorum-based replication.

Abstract: A technique to store a plurality of addresses and data to address and data buffers, respectively, in an ordered manner. More particularly, one embodiment of the invention stores a plurality of addresses to a plurality of address buffer entries and a plurality of data to a plurality of data buffer entries according to a true least-recently-used (LRU) allocation algorithm.

Abstract: Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address containing a primitive is divided into a parity byte and two or more portions, wherein the parity byte includes at least one bit. A value of the parity byte determines which of the two or more portions is a valid portion and which of them is an invalid portion. The primitive is of a memory size that is larger than a maximum size for atomic operation with the PPE and less than or equal to a maximum size for atomic operation with the SPE. Read with reservation and conditional write instructions are used by both the PPE and SPE to access or update a value of the atomic.

Abstract: In some embodiments, an inter-partition apparatus includes a set of registers to store direct memory access (DMA) controls and to store an access control list visible to two or more operating environments separated by a partition, the set of registers including posted receive buffers and transmit pending buffers. A DMA device streams data in both directions between the two or more operating environments in response to the stored DMA controls and in response to the access control list using the posted receive buffers and the transmit pending buffers. Other embodiments are described and claimed.

Abstract: The method is for activating a device. A communication device (14) is provided that is in communication with a server unit (20) that has a processor for generating a number series (38). An application device (16) has a processor (19) for generating a number series (36). The communication device (14) is not communicating directly with the application device (16). The user sends a message (32) including the identification number (30) to the server (20). The server (20) identifies a code number pointed at by a pointer (44) and sends back the code number. The pointer (44) steps forward in the number series (38) at predetermined time intervals. The user enters the code number into the application device (16). The processor (19) compares the code number with a number pointed at by a pointer (37) and sends an activation signal to an activation device (16) to activate the application device.

Abstract: A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for detecting that a first instruction intended for a first area is a predetermined instruction to be followed by a period during which the first area can receive no other instruction, and third circuitry for, during the period, providing instructions to another memory area.

Abstract: The invention allows multiple application systems to use a single database system. The database system is divided into at least a first memory portion and a second memory portion. The memory portions are disjunctive. The database system stores a first assignment of a first profile to the first memory portion and a second assignment of a second profile to the second memory portion . The first and second profiles are unique and refer to the first and second application systems, respectively. The first application system and the second application system access the first memory portion and the second memory portion, through the respective profiles.

Abstract: Information objects and system firmware for a processor in a partitionable computing system are disclosed. One object comprises information corresponding to components of the computer system. The information comprises entries defining an address and a size for registers normally accessible to other partitions. The registers are capable of defining an address area such that in use the processor is arranged to permit other partitions to access at least one address area defined by the at least one register and to deny other partitions access to address areas other than the at least one accessible address area.

Abstract: An operating system in a shared processor logical partitioned data processing system is given a target percentage. The hypervisor assigns the target processor percentage to the operating system. The operating system also has a predetermined time slice to allot to threads in a multitasking environment. The operating system adjusts the time slice based on a per-virtual-processor percentage.

Abstract: Briefly, in accordance with one embodiment of the invention, a portable communication device may have multiple processors and a memory. Portions of the memory may only be accessible by one of the processors.

Abstract: A system or method to partition data in a memory based at least in part to a data type, and to refresh the memory based at least in part to the data type.

Abstract: One embodiment of the present invention provides a system that facilitates delayed block allocation in a distributed file system. During operation, the system receives a write command at a client, wherein the write command includes a buffer containing data to be written and a file identifier. In response to receiving the write command, the system reserves a set of disk blocks for the file from a virtual pool of disk blocks allocated to the client. The system also transfers the data to be written to the kernel of the client where the data waits to be transferred to the disk.