Abstract: An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first information is selected to be used in translating the address. Further, based on the attribute being a second attribute, second information is selected to be used in translating the address. The selected information is used to translate the address to the another address. The another address indicates one memory location based on the selected information being the selected first information, and another memory location based on the selected information being the selected second information.

Abstract: In one embodiment, when a secondary application on an electronic device is selected for deactivation, the memory associated with the application can be gathered, compacted and compressed into a memory freezer file. The memory freezer file can be stored in non-volatile memory with a reduced storage footprint compared to a memory stored in a conventional swap file. When the selected application is to be reactivated, the compressed memory in the memory freezer file can be quickly restored to process memory.

Abstract: Methods and systems are provided where a memory controller for non-volatile memory transfers data to and from random access memory over a second double data rate bus, and a host system access the random access memory over a first double data rate bus. The memory controller may transfer the data in response to a command received by the memory controller from a host system via a block storage protocol bus. Alternatively or in addition, the memory controller may transfer the data as part of caching data internal to the non-volatile memory.

Abstract: A driver enables a first virtual storage director running in a container maintained by a hypervisor to achieve direct memory access to memory of a second virtual storage director running in a different container. An address space is made available to the first virtual storage director. A first portion of the address space is associated with memory allocated to the first virtual storage director by the container. A second portion of the address space is mapped to memory allocated to the second virtual storage director.

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract: A computer implemented method for assigning workload slices from a workload to upcoming frames to be processed during the rendering of the upcoming frames. The processing time of upcoming frames and workload slices varies at runtime according to system resources The method determines an effective frame rate that estimates the duration of an upcoming frame and also determines an effective slice rate that estimates the time it takes to complete an upcoming workload slice. Based on the effective frame rate and the effective slice rate, the method then calculates the slice-to-frame ratio which defines the rate in which slices are assigned to upcoming frames. The slice-to-frame ratio can dynamically change to accommodate for changes to the processing time of rendered frames and completed workload slices.

Abstract: There are provided a DDR controller, a method for implementing the same and a chip, which are applicable to the field of DDR controller technology. The method includes the steps of: parsing a plurality of buffered commands concurrently (S501); prejudging relationships between a bank and a row of an address to be accessed by each parsed command and a bank and a row of an address for a currently executed command; and transmitting a PRECHARGE command and an ACTIVE command in advance. With the above technical solution, the PRECHARGE command and ACTIVE command which should have been transmitted serially can be transmitted in advance by being hidden in parallel in a Read or WRITE period to thereby make full use of a bandwidth of a DDR device.

Abstract: A method and a system for managing sensor information in a portable terminal are provided. The method includes collecting the sensor information through a sensor unit by a sub-controller, determining whether a main controller is in a sleep state, determining whether the collected sensor information is able to be stored in a sub-memory when the main controller is in the sleep state, storing the collected sensing information in the sub-memory, and waking-up the main controller to move the collected sensor information and sensor information stored in the sub-memory to a main memory to store therein when the collected sensor information is unable to be stored in the sub-memory.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and to the memory, wherein the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations including to receive, via the interface, content retrieval messages for a data object. Then, based on the content retrieval messages for the data object and respectively for each associated data segment, the processing module determines respective groups of unique pillar combinations of at least read threshold number of EDSs, retrieves the respective groups of unique pillar combinations of at least read threshold number of EDSs from storage units (SUs) within the DSN, and provides the respective groups of unique pillar combinations of at least read threshold number of EDSs respectively to recipient device(s).

Abstract: Described systems and methods enable a host system to efficiently perform computer security activities, when operating in a hardware virtualization configuration. A processor is configured to generate a VM suspend event (e.g., a VM exit or a virtualization exception) when a guest instruction executing within a guest VM performs a memory access violation. In some embodiments, the processor is further configured to delay generating the VM suspend event until the execution stage of the pipeline for the guest instruction is complete, and to save results of the execution stage to a specific location (e.g. a specific processor register readable by security software) before generating the event.

Abstract: A command is received to copy a first extent in a source volume to a second extent in a target volume, wherein the source volume and the target volume are in a copy relationship. In response to determining that it takes longer to copy all changed data of the first extent to the second extent than to copy all of the changed data of the first extent to a third extent and to copy all other data from the second extent to the third extent, operations are performed to copy all of the changed data of from the first extent to the third extent and to copy all of the other data from the second extent to the third extent. Operations are also performed to assign the third extent to replace the second extent in the target volume.

Abstract: The present invention relates to a sensing control signal generation circuit and a semiconductor memory device including the same. In an embodiment, a semiconductor memory device may include a memory block suitable for including a plurality of memory cells coupled in series and a plurality of cell strings respectively coupled to a plurality of bit lines, page buffers suitable for being coupled to the respective bit lines in response to a sensing control signal and each suitable for sensing a voltage of each of the bit lines transferred to a sensing node and storing data corresponding to the results of the sensing or temporarily storing data to be programmed into a selected memory cell, and a sensing control signal generation unit suitable for generating the sensing control signal having a form of a ramping signal rising at a constant slope during the program operation.

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Abstract: Disclosed is a memory controller, including: a host interface suitable for queuing a plurality of host commands from a host in a host command queue; a state register storing ready set bits respectively corresponding to the plurality of host commands; a memory command generating unit generating and queuing memory commands and state update information corresponding to the queued host commands in a memory command queue, respectively; and the memory command performing unit performing an operation in response to the queued memory commands. The memory command performing unit obtains state update information corresponding to the performed memory command from the memory command queue, and updates a ready set bit of a host command corresponding to the performed memory command based on the obtained state update information.

Abstract: In a memory system, multiple memory modules communicate over a bus. Each memory module may include a hub and at least one memory storage unit. The hub receives local data from the memory storage units, and downstream data from one or more other memory modules. The hub assembles data to be sent over the bus within a data block structure, which is divided into multiple lanes. An indication is made of where, within the data block structure, a breakpoint will occur in the data being placed on the bus by a first source (e.g., the local or downstream data). Based on the indication, data from a second source (e.g., the downstream or local data) is placed in the remainder of the data block, thus reducing gaps on the bus. Additional apparatus, systems, and methods are disclosed.

Abstract: A method in one example implementation includes intercepting a request associated with an execution of an object (e.g., a kernel module or a binary) in a computer configured to operate in a virtual machine environment. The request is associated with a privileged domain of the computer that operates logically below one or more operating systems. The method also includes verifying an authorization of the object by computing a checksum for the object and comparing the checksum to a plurality of stored checksums in a memory element. The execution of the object is denied if it is not authorized. In other embodiments, the method can include evaluating a plurality of entries within the memory element of the computer, wherein the entries include authorized binaries and kernel modules. In other embodiments, the method can include intercepting an attempt from a remote computer to execute code from a previously authorized binary.

Abstract: There is provided a distributed object storage system that includes several performance optimizations with respect to efficiently storing data objects when coping with a desired concurrent failure tolerance of concurrent failures of storage elements which is greater than two and with respect to optimizing encoding/decoding overhead and the number of input and output operations at the level of the storage elements.

Abstract: A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The buffer memory management method includes allocating a mapping table zone having a first zone and a second zone in the buffer memory, and temporarily storing a plurality of logical address-physical address mapping tables into the first zone and the second zone, and receiving a first write command which indicates writing first data into a first logical address. A first logical address-physical address mapping table to which the first logical address belongs is temporarily stored into a first buffer unit in the second zone. The method also includes updating the first logical address-physical address mapping table, moving the updated first logical address-physical address mapping table into a second buffer unit in the first zone, and marking the second buffer unit as a dirty status.

Abstract: A modular industrial vehicle having one or more modules that communicate with a managing controller to provide an operating mode for the modular industrial vehicle based configuration and technical specifications of the one or more modules.

Abstract: A method begins by a dispersed storage (DS) processing obtaining estimated future availability information for storage units and organizing a plurality of sets of encoded data slices into a plurality of group-sets of encoded data slices. For each of the plurality of group-sets of encoded data slices, the method continues with the DS processing module estimating an approximate storage completion time to produce a plurality of approximate storage completion times. The method continues with the DS processing module establishing a time-availability pattern for writing the plurality of group-sets of encoded data slices to the storage units based on the estimated future availability information and the plurality of approximate storage completion times. The method continues with the DS processing module sending the plurality of group-sets of encoded data slices to at least some of the storage units for storage therein in accordance with the time-availability pattern.

Abstract: A memory device and method of operating a memory device are provided. The memory device comprises global control circuitry configured to receive a clock signal for the memory device and the memory device is configured to perform a double memory access in response to a single edge of the clock signal. A first internal clock pulse for a first access of the double memory access and a second internal clock pulse for a second access of the double memory access are generated in response to the single edge of the clock signal. The global control circuitry generates a comparison signal in dependence on a comparison between a first bank indicated by the first access and a second bank indicated by the second access, and local bank control circuitry of the second bank is configured to generate the second internal clock pulse in dependence on the comparison signal.

Abstract: According to one embodiment, a file system (FS) of a storage system is partitioned into a plurality of FS partitions, where each FS partition stores segments of data files. In response to a request for writing a file to the storage system, the file is stored in a first of the FS partitions that is selected based on a time attribute of the file, such that files having similar time attributes are stored in an identical FS partition.

Abstract: A device has a protection unit for controlling access to a memory. Indirect memory access requests have control data indicative of a memory access control register to be written to provide indirect access to a target memory and requested address data indicative of at least one memory address of the target memory to be accessed. The protection unit contains protection data defining access rights of source units to access specified address ranges of the target memory, and a system bus interface interfacing to a source unit and a memory bus interface interfacing to the target memory via a controller. The protection unit has a control monitor for detecting an indirect memory access request, and an indirect address monitor for comparing requested address data to specified address ranges and subsequently grant the indirect memory access in accordance with access rights of the respective source unit.

Abstract: A method for allocating memory among a plurality of computing systems includes assigning a free memory threshold to each computing system, dynamically varying at least one free memory threshold for at least one computing system based on a past memory usage of the at least one computing system, periodically monitoring each computing system for memory usage and in response to the monitoring determining that an amount of free memory for the computer system is below the free memory threshold for the computing system, allocating memory from the free memory pool to the computing system.

Abstract: A computer implemented method, system, and computer program product for recovering from a crash of a system being replicated, the method comprising determining the amount of recovery time due to the crash of each of a set of hypervisors; wherein each of the hypervisors runs one or more data replication elements selected from the group consisting of a splitter and a replication appliance; wherein each of the splitters and replication appliances replicates one or more volumes, creating an assignment of the one or more volumes to the set of replication appliances and creating an assignment of one or more replication appliances to a set of hypervisors to minimize the amount of recovery time.

Abstract: A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

Abstract: Methods, apparatus and computer program products for a distributed system include dividing logical volume data into data subsets, and defining at least one distributedly storage configuration for the logical volume. Metadata for the logical volume is written to a first set of first metadata tables, and the first set of first metadata tables is divided into metadata subsets having a one-to-one correspondence with the data subsets. The metadata subsets are distributed among the multiple digital information devices, and the metadata is copied from the first set of first metadata tables to a second set of corresponding second metadata tables in a one-to-one correspondence with the first metadata tables, and the second metadata tables are distributed among the multiple digital information devices.

Abstract: A method begins by a dispersed storage (DS) processing detecting unavailability of a storage device of a site of dispersed storage network (DSN) memory to produce an unavailable storage device. The method continues with the DS processing module reassigning a fraction of a logical address sub-range of the unavailable storage device to one or more other storage devices, rebuilding one or more logically addressable data objects to produce one or more rebuilt data objects and storing the one or more rebuilt data objects in the one or more other storage devices. When the unavailable storage device becomes available, the method continues with the DS processing module reallocating the fraction of the logical address sub-range from the one or more other storage devices to the storage device and transferring the one or more rebuilt data objects from the one or more other storage devices to the storage device.

Abstract: The systems and methods of the present invention provide a solution that makes data provably secure and accessible—addressing data security at the bit level—thereby eliminating the need for multiple perimeter hardware and software technologies. Data security is incorporated or weaved directly into the data at the bit level. The systems and methods of the present invention enable enterprise communities of interest to leverage a common enterprise infrastructure. Because security is already woven into the data, this common infrastructure can be used without compromising data security and access control. In some applications, data is authenticated, encrypted, and parsed or split into multiple shares prior to being sent to multiple locations, e.g., a private or public cloud. The data is hidden while in transit to the storage location, and is inaccessible to users who do not have the correct credentials for access.

Abstract: Some implementations include a method of managing a hosted non-volatile random-access memory (NVRAM) based storage subsystem that includes NVRAM devices. The method includes: receiving, at a device driver on the host computing device, write requests each requesting to write a respective unit of data to the NVRAM-based storage subsystem; categorizing the write requests into subgroups of write requests, where write requests within respective subgroups are mutually exclusive; ascertaining a load condition of each of several of the NVRAM devices of the NVRAM-based storage subsystem; identifying a target location on at least one NVRAM device to service a particular subgroup of write requests according to the ascertained load conditions of the NVRAM devices of the NVRAM-based storage subsystem; and servicing the particular subgroup of write requests by writing the corresponding units of data to the identified target location on the at least one NVRAM device of the NVRAM-based storage subsystem.

Abstract: A specification of resource requirements is received. One or more resource configurations for a computing environment that satisfy the specification of resource requirements are generated utilizing a description of available resources in the computing environment. A model is utilized to estimate a level of service for each of the resource configurations, wherein the model predicts behavioral dependencies between attributes of the resources in the computing environment. A given one of the resource configurations is selected based at least in part on the estimated levels of service, and resources in the computing environment are assigned according to the selected configuration of resources.

Abstract: A system identifies a performance bottleneck status in a parallel data processing environment by examining data flow associated with the parallel data processing environment to identify at least one operator, where an operator type is associated with at least one operator, at least one buffer, and a relationship that the buffer has with the operator, where the relationship is associated with the operator type. The system monitors the buffer to determine a buffer status associated with the buffer. The system applies a set of rules to identify an operator bottleneck status associated with the operator. The set of rules is applied to the operator, based on the operator type, the buffer status, and relationship that the buffer has with the operator. The system then determines a performance bottleneck status associated with the parallel data processing environment, based on the operator bottleneck status.

Abstract: Methods, apparatus and computer program products for a distributed system include dividing logical volume data into data subsets, and defining at least one distributedly storage configuration for the logical volume. Metadata for the logical volume is written to a first set of first metadata tables, and the first set of first metadata tables is divided into metadata subsets having a one-to-one correspondence with the data subsets. The metadata subsets are distributed among the multiple digital information devices, and the metadata is copied from the first set of first metadata tables to a second set of corresponding second metadata tables in a one-to-one correspondence with the first metadata tables.

Abstract: A memory controller may receive a plurality of thermal profiles from a plurality of three-dimensional (3D)-stacked memory chips, where the plurality of thermal profiles include thermal profile data for the memory chips, where the thermal profile data includes a memory chip usage data and a location data for each of the memory chips, and where the memory chips include a first memory chip and a second memory chip. The memory controller may generate a first predicted memory chip usage data and location data by analyzing the usage data and location data of the thermal profile data. A second predicted memory chip usage data and location data may be generated. Based on the predicted memory chip, fractional memory chip read propensity data may be generated. The memory controller may distribute, according the first fractional memory chip read propensity distribution, memory chip read operations.

Abstract: Atomically accumulating memory updates in a computer system configured with an accumulator that is memory mapped. The accumulator includes an accumulator memory and an accumulator queue and is configured to communicatively couple to a processor. Included is receiving from the processor, by the accumulator, an accumulation request. The accumulation request includes an accumulation operation identifier and data. Based on determining, by the accumulator, that the accumulator can immediately process the request, immediately processing the request. Processing the request includes atomically updating a value in the accumulator memory, by the accumulator, based on the operation identifier and data of the accumulation request. Based on determining, by the accumulator, that the accumulator is actively processing another accumulation request, queuing, by the accumulator, the accumulation request for later processing.

Abstract: Described herein is a system and method for a scalable crash-consistent snapshot operation. Write requests may be received from an application and a snapshot creation request may further be received. Write requests received before the snapshot creation request may be associated with pre-snapshot tags and write requests received after the snapshot creation request may be associated with post-snapshot tags. Furthermore, in response to the snapshot creation request, logical interfaces may begin to be switched from a pre-snapshot configuration to a post-snapshot configuration. The snapshot may then be created based on the pre-snapshot write requests and the post-snapshot write requests may be suspended until the logical interfaces have switched configuration.

Abstract: In a method of detecting a transmission bandwidth configuration, the method includes monitoring (610) a first set of control channel candidates in a subframe (424) using a first transmission bandwidth and includes monitoring (612) a second set of control channel candidates using a second transmission bandwidth. The method also includes detecting (614) a control channel (428) in one of the first set of control channel candidates and the second set of control channel candidates and includes determining (616) a transmission bandwidth (421, 423) configuration for the subframe based on the detected control channel of one of the first set of control candidates and the second set of control channel candidates.

Abstract: Efficient data deduplication is described herein. A deduplication bit array partition can be created that corresponds to a number of data items in an expected dataset. The deduplication bit array partition can track whether the data items have been received. When a data item in the expected dataset is received, a bit in the deduplication bit array partition corresponding to the received data item can be accessed to determine, based on the value of the bit, if the received data item has already been received. When the value of the bit indicates that the received data item has not already been received, the value can be changed to indicate that the data item has now been received. When the value of the bit indicates that the received data item has already been received, the data item can be deleted or ignored.

Abstract: A reclaim system frees previously allocated, but currently unused, storage space in a thin or virtual provisioning environment. The reclaim system may be used in connection with a maintenance operation performed upon determining that significant allocated space of a thin device is no longer being used or may be performed periodically to analyze a thin device and free appropriate space back to a thin device storage pool. In an embodiment, the reclaim system may run online while user applications are accessing a target storage volume.

Abstract: Security techniques may be selectively performed on data based on a classification of the data. One example technique includes receiving a memory access command specifying a target data block on a storage medium storing both security data and non-security data. The technique further includes determining whether data affected by the access command is security data. Response to such determination, one of multiple data management schemes is selected to implement the memory access command, where each of the data management schemes is adapted to implement the memory access command via a different series of processing operations to provide a different level of security protection for data affected by the memory access command.

Abstract: A memory management system is described herein that receives information from applications describing how memory is being used and that allows an application host to exert more control over application requests for using memory. The system provides an application memory management application-programming interface (API) that allows the application to specify more information about memory allocations that is helpful for managing memory later. The system also provides an ability to statically and/or dynamically analyze legacy applications to give applications that are not modified to work with the system some ability to participate in more effective memory management. The system provides application host changes to leverage the information provided by applications and to manage memory more effectively using the information and hooks into the application's use of memory.

Abstract: An analysis device obtains hash lists from databases of a server cluster. The analysis device determines repetitive hash values and repetitive data blocks. The analysis device deletes the repetitive data blocks from servers of the server cluster.

Abstract: A distributed information processing system comprises first and second sites, which may comprise respective production and replica sites. A snapshot of a first portion of a complex asset is generated at the first site and sent to the second site, and a second portion of the complex asset is replicated at the second site. The complex asset includes one or more virtual machines provided by one or more hypervisors of a virtualization platform of the first site and at least one storage element surfaced through a storage platform of the first site, with the storage platform being external to the virtualization platform. Recovery of the complex asset is implemented at the second site utilizing, for example, a ghost complex asset preconfigured in accordance with current complex asset state information based on the snapshot of the first portion of the complex asset and the replicated second portion of the complex asset.

Abstract: A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

Abstract: A computer node comprises dual hard drives. A method of testing the computer node comprises performing a test of the first hard drive, waiting a specific time period, and performing a test of the second hard drive. Each test comprises isolating the drive being tested, writing data to the drive being tested, removing power from the drive being tested, repowering the drive being tested, and reading data from the drive being tested.

Abstract: Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.

Abstract: A memory system or flash card may include memory maintenance scheduling that improves the endurance of memory. Certain parameters, such as temperature, are measured and used for scheduling maintenance. For example, memory maintenance may be performed or postponed depending on the ambient temperature of the card. The memory maintenance operations may be ranked or classified (e.g. in a memory maintenance queue based on priority) to correspond with threshold values of the parameters for a more efficient scheduling of memory maintenance. For example, at a low temperature threshold, only high priority maintenance operations are performed, while at a higher temperature threshold, any priority maintenance operation is performed.

Abstract: Various embodiments of the invention relate to secure systems and modules, and more particularly, to systems, devices and methods of generating and applying identification elements uniquely associated with memory, memory mapping and encrypted storage. These unique identification elements provide an improved, statistically random source from which keys and memory mappings may be derived. The application of these keys across various architectures result in an improvement in the security of data stored within a system.

Abstract: Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.

Abstract: According to one embodiment, a memory device is connectable to a host device. The memory device includes a first interface unit, a controller unit, a second memory and a second interface. The first interface unit receives a write command from the host device. The controller unit acquires the write-data associated with the write command stored in a first memory area of a first memory in the host device, the write-data being copied from a second memory area of the first memory. The second interface causes the second memory to write the write-data in the second memory.