Abstract: Virtual machines in a computer system cluster, or cloud environment, require access to their assigned storage resources connected to the virtual machines via storage area networks (SAN). Such virtual machines may be independent from associated physical servers in the computer system cluster on which they are deployed. These virtual machines may dynamically migrate among assigned physical servers while maintaining access to their connected storage resources both from the source physical server and the target physical server during the migration.

Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.

Abstract: A storage unit for use within a dispersed storage network comprises an interface and a processing module operable to receive encoded data slices from a dispersed storage network client. The encoded data slices are associated with DSN logical addresses and the storage unit is allocated a range of DSN logical addresses in which the DSN logical addresses are found. The storage unit determines whether to store the encoded data slices in local memory of the storage unit or store them in remote memory. When the storage unit determines to store the encoded data slice to the remote memory it converts the DSN logical address into a local storage unit logical address and outputs the encoded data slices to the remote memory.

Abstract: Apparatuses and methods of data communication between semiconductor chips are described. An example apparatus includes: a first semiconductor chip and a second semiconductor chips that are stacked with each other via through substrate vias (TSVs) provided in one of the first semiconductor chip and the second semiconductor chip. The first semiconductor chip and the second semiconductor chips communicate with each other by use of data bus inversion data that have been encoded using a DBI algorithm.

Abstract: The embodiments of the invention describe settings, commands, command signals, flags, attributes, parameters or the like for signed access prior to allowing data to be written to (e.g., a write access), read from (e.g., a read access) or erased from (e.g., an erase access) protected areas of a memory device (e.g., a region, logical unit, or a portion of memory in the storage module).

Abstract: The embodiments herein relate to a method in a first mobility management node (108a) for handling updated subscriber data associated with a UE (101). The UE (101) is currently unreachable by the first mobility management node (108a). The first mobility management node (108a) receives, from a subscriber database (128), updated subscriber data associated with the UE (101). At least part of the updated subscriber data is modified. The first mobility management node (108a) determines that transmission of the updated subscriber data to a gateway node (110) should be postponed until the UE (101) has become reachable.

Abstract: A probabilistic data structure is generated for efficient query processing using a histogram for unsorted data in a column of a columnar database. A bucket range size is determined for multiples buckets of a histogram of a column in a columnar database table. In at least some embodiments, the histogram may be a height-balanced histogram. A probabilistic data structure is generated to indicate for which particular buckets in the histogram there is a data value stored in the data block. When an indication of a query directed to the column for select data is received, the probabilistic data structure for each of the data blocks storing data for the column may be examined to determine particular ones of the data blocks which do not need to be read in order to service the query for the select data.

Abstract: Systems and methods for managing data input/output operations are described that include virtual machines operating with a shared storage within a host. In such a system, a computer-implemented method is provided for dynamically provisioning cache storage while operating system applications continue to operate, including stalling the virtual machine's local cache storage operations, changing the provision of cache storage size; and resuming the operations of the virtual machine.

Abstract: A non-transitory computer-readable recording medium stores therein an encoding program that causes a computer to execute a process including: first creating a plurality of pieces of encoded data that are obtained by encoding a plurality of files by using a specific encoding format; second creating a plurality of encoded blocks that are obtained by dividing combined encoded data, the combined encoded data being obtained by combining the plurality of pieces of the encoded data into blocks with a fixed length; and third creating an index associated with each of the plurality of the encoded blocks.

Abstract: A method, apparatus, and manufacture for memory device startup is provided. Flash memory devices are configured such that, upon the power supply voltage reaching a pre-determined level, each flash memory is arranged to load the random access memory with instructions for the flash memory, and then execute a first portion of the instructions for the flash memory. After executing the first portion of the instructions for the flash memory, each separate subset of the flash memories waits for a separate, distinct delay period. For each flash memory, after the delay period expires for that flash memory, the flash memory executes a second portion of the instructions for the flash memory.

Abstract: A processor of a data processing apparatus performs: acquiring target image data that is generated by optically reading an original document; acquiring, by using the target image data, character region data and other-type region data, the character region data being indicative of a character region representing characters, the other-type region data being indicative of an other-type region different from the character region; generating first compressed data by performing a first compression process on the character region data; acquiring first character-recognized data including first character information that is generated by performing a character recognition process on the first compressed data; generating second compressed data by performing a second compression process on the other-type region data, the second compression process being different from the first compression process; and acquiring second character-recognized data including second character information that is generated by performing the ch

Abstract: A computer including a processor and a memory and a storage device that is connected to the computer and stores data has an FPGA that acquires data and an operation command from a control unit that controls reading and writing with respect to a non-volatile semiconductor storage unit to perform a data operation. The computer generates and transmits the operation command from an access request that has been received to the storage device. The computer receives execution results for the operation command from the storage device, and when the number of execution results for the operation command reaches a prescribed value, instructs the FPGA to detect a soft error, receives all execution results with respect to the generated operation command, and if there is no soft error, transmits the execution results.

Abstract: A data management method includes steps of: receiving a read command; reading a page containing target data from a non-volatile memory when the target data corresponding to the read command is stored in the non-volatile memory; determining whether a count of reading of the page is greater than a read threshold; and if false, storing at least one record of subsequent data into a first storage space of a data buffering storage device; or if true, storing the at least one record of subsequent data into a second storage space of the data buffering storage device. Both of the target data and the at least one record of subsequent data are stored in the page, and the target data and the at least one record of subsequent data have a sequential relationship in terms of data reading. Another data management method and a corresponding data storage device are also provided.

Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, a second memory, and a controller. The processing device is configured to process first data. The first memory is configured to store at least part of the first data and has an active region supplied with power necessary for holding data. The second memory is configured to store part of the first data. The controller is configured to change number of active regions such that processing information is not more than a threshold. The processing information indicates an amount of processing for moving at least part of second data stored in the first memory to the second memory and for moving at least part of third data stored in the second memory to the first memory, in a certain period for processing the first data having a size larger than active regions.

Abstract: A system for data conversion comprises an interface and a processor. The interface is to receive a data conversion definition. The processor is to store an indication of data requiring data conversion; launch a data traverser and an on-the-fly converter; and in the event that data requested to be accessed requires data conversion: convert, using the on-the-fly converter, data to a converted data using the data conversion definition and provide the converted data.

Abstract: A memory device having an improved program speed may include a memory cell array including a plurality of memory cells, each being programmed to one of a plurality of program states; a peripheral circuit configured to perform a program operation to one or more of the plurality of memory cells, the program operation including a program voltage applying operation and a verify operation; and a control logic configured to control the peripheral circuit to simultaneously perform the verify operation for at least two program states by applying bit line voltages having different voltage levels to bit lines coupled to the plurality of memory cells.

Abstract: A dual-screen user device and methods for launching applications from a revealed desktop onto a logically chosen screen are disclosed. Specifically, a user reveals the desktop and then launches a selected application from one of two desktops displayed on a primary and secondary screen of a device. When the application is launched, it is displayed onto a specific screen depending on the input received and the logical rules determining the display output. As the application is displayed onto the specific screen, the desktop is removed from display and the opposite screen can display other data.

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

Abstract: In one embodiment, a computer-implemented method of a dedupe storage network includes the step of providing one or more replication-site dedupe storage nodes. Another step includes providing an onsite-dedupe storage node, wherein the onsite dedupe node initiates a replication operation, wherein the replication operation comprises the onsite dedupe storage node operation pushing or fetching a dedupe-image data from the one or more replication-site dedupe storage nodes. The replication from local dedupe storage node to remote dedupe storage node pushes data not present at remote. The replication from remote dedupe storage node to local dedupe storage node fetches data not present at local.

Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.

Abstract: Systems, methods, and computer program products to manage an address translation in a virtually segmented memory system, with included processes comprising a process scoped segment table (STAB) consisting of segment table entries (STEs) that contain effective address segment number (ESID) to system wide unique virtual segment identifier (VSID) mappings, and creating a global kernel segment table (STAB) that itself is translated using a pinned page table entry (PTE). A switch to the global kernel STAB is initiated in response to a page fault interrupt on a process STAB PTE and a PTE reload handler invoked to reload that process STAB PTE. A switch to an original STAB is initiated in order to resume the address translation and resolve the page fault or the interrupt by an operating system executing on the processor.

Abstract: A method, computer system, and a computer program product for enhanced application write operations is provided. The present invention may include performing a write operation by an application node. The present invention may then include committing the write operation to a local buffer cache. The present invention may then include sending the application node an indication that the write operation was successful. The present invention may then include flushing the local buffer cache to a disk, and the present invention may lastly include sending a Remote Procedure Call (RPC) to a gateway node.

Abstract: A method for tracking and invalidating memory address synonyms in a cache memory system includes receiving a request to associate a second memory address with a first memory address in a cache memory system that supports synonyms, wherein the second memory address and the first memory address each comprise a synonym identifier. The method also includes determining a set of differing bits within the synonym identifier of the first memory address and the second memory address, and including the set of differing bits within a set of synonym generation bits for the cache memory system. A corresponding apparatus, computer program product, and system are also disclosed herein.

Abstract: Methods and devices are described for encoding and decoding control information that has been modulated based on one or more identifiers of the transmitter and/or receiver. Some embodiments describe scrambling sequence design for multi-mode block discrimination on downlink control information (DCI) blind detection. Separate scrambling masks may be applied to disparate bit fields within a coded DCI message, wherein each of the scrambling masks is derived from a unique identifier associated with either the transmitter or the intended receiver. The scrambling masks may be used by the receiver to perform early termination of the decoding process, to mitigate intercell interference, and to verify that the receiver is the intended receiver.

Abstract: Embodiments include a multi-stream storage device, a system including a multi-stream storage device, and a method, comprising: receiving an access to a logical address associated with a multi-stream storage device; converting the logical address into a stream identifier; and accessing the multi-stream storage device using the logical address and the stream identifier.

Abstract: A processor modifies memory management mode for a range of memory locations of a multilevel memory hierarchy based on changes in an application phase of an application executing at a processor. The processor monitors the application phase (e.g., computation-bound phase, input/output phase, or memory access phase) of the executing application and in response to a change in phase consults a management policy to identify a memory management mode. The processor automatically reconfigures a memory controller and other modules so that a range of memory locations of the multilevel memory hierarchy are managed according to the identified memory management mode. By changing the memory management mode for the range of memory locations according to the application phase, the processor improves processing efficiency and flexibility.

Abstract: A method for encoding and decoding information data using a polar code is provided. The method for encoding includes segmenting information data into a plurality of first packets, generating a plurality of second packets corresponding to the plurality of first packets by adding a corresponding packet Cyclic Redundancy Check (CRC) code to each of the plurality of first packets, fragmenting each of the plurality of second packets into a plurality of data blocks, polar code encoding each of the plurality of data blocks included in a corresponding second packet of the plurality of second packets, and generating a plurality of third packets corresponding to the plurality of second packets by concatenating each polar code encoded data block included in the corresponding second packet. The method for decoding includes decoding the third packet to obtain the information data based on the method for encoding.

Abstract: A peripheral device may implement storage virtualization for non-volatile storage devices connected to the peripheral device. A host system connected to the peripheral device may host one or multiple virtual machines. The peripheral device may implement different virtual interfaces for the virtual machines or the host system that present a storage partition at a non-volatile storage device to the virtual machine or host system for storage. Access requests from the virtual machines or host system are directed to the respective virtual interface at the peripheral device. The peripheral device may perform data encryption or decryption, or may perform throttling of access requests. The peripheral device may generate and send physical access requests to perform the access requests received via the virtual interfaces to the non-volatile storage devices. Completion of the access requests may be indicated to the virtual machines via the virtual interfaces.

Abstract: The present disclosure includes apparatuses and methods for sequence power control. A number of embodiments include executing a number of sequences associated with a number of commands, wherein a number of logical unit (LUN) controllers execute the number of sequences by locating power consumption information and a starting address of the number of sequences stored in a data structure on the number of LUN controllers.

Abstract: Various embodiments are generally directed to techniques to remotely access object events. An apparatus may comprise a processor and a memory communicatively coupled to the processor. The memory may be operative to store a remote event bridge having a surrogate object that when executed by the processor is operative to allow an observer object for a first process to subscribe to an event of a subject object for a second process using the surrogate object. In this manner, the remote event bridge and the surrogate object operates as an interface between subject objects and observer objects without any modifications to either class of objects.

Abstract: One or more control circuits of a storage system are configured to intelligently set a task readiness indicator for tasks on a task command queue. A memory controller may divide each of the tasks into one or more chunks. The memory controller initiates processing of at least some of the chunks for at least two tasks and determines a task readiness factor each of the tasks based on how far respective chunks have progressed in the processing. The memory controller sets a ready indicator in a task status register for a selected task based on the task readiness factor of the tasks. Therefore, task latency may be reduced. In one aspect, the memory controller allocates a ring buffer to chunks of an executing task. This ring buffer may assure that there will always be memory for the chunks of the task.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device receives a store data object request and facilitates distributed storage of the data object in storage units (SUs). the computing device applies unique deterministic functions to the object name to generate deterministic values. For a deterministic value, the computing device identifies a corresponding SU based on the deterministic value and the bucket mapping scheme. The computing device transmits an update bucket request to the corresponding SU to be used by the corresponding SU to update a state value of a bucket that is locally stored by the corresponding SU to indicate an active state.

Abstract: A storage system in one embodiment comprises a plurality of storage devices and a storage controller. The storage controller is configured to receive a plurality of logical addresses. Each logical address has one of a content-based mapping type and an address-based mapping type. Responsive to a first logical address of the plurality of logical addresses having the content-based mapping type, the storage controller is configured to utilize a content-based mapping generated based on content of a data page associated with the first logical address to identify a corresponding physical address. Responsive to a second logical address of the plurality of logical addresses having the address-based mapping type, the storage controller is configured to utilize an address-based mapping generated based on the second logical address to identify a corresponding physical address.

Abstract: Executing connections from a data processing system to a storage controller using ports specified in a TPG report. The storage controller receives a RTPG SCSI request from the data processing system via a FC fabric. The storage controller determines whether NPIV is enabled on the storage controller and, if so, the storage controller modifies the TPG report to include one or more dedicated N-Ports and one or more multi-purpose N-Ports, where AAS bits of a dedicated N-Port descriptor associated with the dedicated N-Ports are set as Active/optimized. The storage controller sends the modified TPG report to the data processing system. The storage controller then processes an access request received from the data processing system where the access request is received on one of the one or more dedicated N-Ports and the one or more multi-purpose N-Ports according to the TPG report and a device type of the data processing system.

Abstract: Exemplary methods, apparatuses, and systems parse programming code to identify instructions within the programming code to allocate objects and instructions within the programming code to create, delete, and/or update references to the objects. Based upon the identified instructions, a model of memory used when the programming code is executed is generated. The model includes representations of the objects and representations of changes to the references to the objects. Based upon the representations in the model, it is determined that each of a plurality of the objects is connected to another of the plurality of objects by one of the references but unreachable by any variable at a point of execution of the programming code. In response to the determination that the plurality of objects is unreachable, a report is generated to flag the unreachable plurality of objects as a potential memory leak for correction.

Abstract: Embodiments of this disclosure are directed to an execution profiling handler configured for intercepting an invocation of memory allocation library and observing memory allocation for an executable application process. The observed memory allocation can be used to update memory allocation meta-data for tracking purposes. The execution profiling handler can also intercept indirect branch calls to prevent heap allocation from converting to execution and intercept exploitation of heap memory to block execution.

Abstract: General polar codes are disclosed that encode symbols of a q-ary alphabet, where q?2. Systems and methods are also disclosed for performing code rate matching when using general polar codes. In one embodiment, a method performed at a transmitter includes receiving a plurality of bits at a polar encoder. The plurality of bits represent a plurality of q-ary symbols, where q>2. The method further includes encoding the plurality of bits using the polar encoder to generate a codeword of q-ary symbols represented by bits. The method further includes puncturing the codeword according to a puncturing pattern to obtain a punctured codeword having a reduced bit length.

Abstract: Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical memory is organized as two or more physical memory blocks, each physical memory block having a fixed storage capacity. An indication of which of the physical memory blocks is active at any point in time is provided. A memory controller provides a non-duplicating write capability, where data to be written to the physical memory is compared to contents of all active physical memory blocks at the time of writing, to ensure that no two active memory blocks have the same data after completion of the non-duplicating write.

Abstract: A memory system is provided. The memory system includes a first memory device having a first latency corresponding to a first command and a second memory device having a second latency corresponding to a second command. The second latency differs from the first latency by a latency difference. The memory system further includes a host operably coupled to the first and second memory devices. The host is configured to send the first command to the first memory device at a first time, and to send the second command to the second memory device at a second time. The first time and the second time are separated by a delay corresponding to the latency difference.

Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. Instructions that modify the main address space are intercepted, storage delta packets are generated based on intercepted instructions, and the storage delta packets are sent to a service co-processor maintaining a service address space.

Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor updates the service address space with storage delta packets received from the main processor, and the service co-processor performs diagnostic services based on command packets received from the main processor.

Abstract: Embodiments include method, systems and computer program products for data compression in storage clients. In some embodiments, a storage client for accessing a storage service from a computer program is provided. A compression method is provided in the storage client to reduce a size of data objects. A frequency of compressing data from the computer program or modifying a compression algorithm based on assessing costs and benefits of compressing the data is varied.

Abstract: A method of operating a storage system is disclosed. The method includes determining a storage cluster among storage arrays of the storage system. Each storage array includes at least two controllers and at least one storage shelf. The at least two controllers are configured to function as both a primary controller for a first storage array and a secondary controller for a second storage array.

Abstract: A computing system for supporting a plurality of different types of memory devices includes a memory voltage regulator. The memory voltage regulator adjusts a supply voltage to a requisite voltage for a detected memory device based on serial presence detect (SPD) data. The computing system further includes a memory controller that supports a plurality of types of memory devices. The memory controller receives data regarding the type of the detected memory device, and controls input/output signals relative to the type of the detected memory device based on the SPD data and the GPIO data of the detected memory device.

Abstract: A secure parallel processing technique for converting any parallel random access machine (PRAM) into an oblivious parallel random access machine (OPRAM), whose distribution of memory accesses is statistically independent of the data (with negligible error), while only inducing a polylogarithmic slowdown to both the total and parallel complexities of the program.

Abstract: Technical solutions are described for shifting wearout of an array of storage disks in a storage system. In an aspect, a method includes staggering completion of maximum number of writes for each storage disk in the array. The method also includes copying data from a storage disk in the array to a replacement disk and redirecting a request to access the data from the storage disk to the replacement disk. The method also includes, in response to passage of a predetermined duration of time since copying the data from the storage disk to the replacement disk, copying the data from the replacement disk to the storage disk and directing the request to access the data from the storage disk back to the storage disk.

Abstract: A dynamic shared-memory data race detection tool with data-scoping capabilities to reduce runtime overheads is disclosed. The tool allows users to restrict analysis of memory locations to heap and/or stack variables that are of interest to them using explicit calls to functions provided in a library that is part of the race detection tool. The application code is instrumented to insert probes at all memory instructions and linked with the data race detection library to perform data-scoped race detection.

Abstract: In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.

Abstract: There is provided with an imaging control apparatus. A reception unit receives an imaging order. A control unit permits adding identification information if the received imaging order includes no identification information and to inhibit correction of the identification information upon determining that the identification information is included in the imaging order. An obtaining unit obtains information to be added as the identification information if the identification information is not included in the imaging order. A transmission unit transmits an image captured in accordance with the imaging order and either the obtained identification information or the identification information included in the imaging order, in association with each other, to an external image archiving apparatus.