Abstract: An apparatus for controlling operation of a cache includes a first command queue, a second command queue and an input controller configured to receive requests having a first command type and a second command type and to assign a first request having the first command type to the first command queue and a second command having the first command type to the second command queue in the event that the first command queue has not received an indication that a first dedicated buffer is available.

Abstract: A method, apparatus, and a storage system are provided for implementing enhanced indirection update for indirected storage devices. A novel remapping command generated by a host is used to store indirection data. The remapping command enables remapping of a set of Logical Block Addresses (LBAs) to a different set of LBAs. The remapping command includes a source LBA, length and a destination LBA.

Abstract: Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device.

Abstract: Techniques for providing access to data are disclosed. In an embodiment, a method for providing access to data involves storing data among a plurality of data stores where at least two of the data stores differ in at least one ability to perform a data operation. A mapping associates data containers with locations of corresponding data among the data stores. At least a portion of the data is redistributed among the data stores according to at least one policy that defines where among the data stores said at least a portion of the data should be stored. A request from a requestor to access particular data corresponding a data container is received and the particular data is located using the mapping. The particular data is provided to the requestor.

Abstract: Methods and systems are disclosed that relate to identifying an appropriate logical unit for a requested application storage allocation. An exemplary method includes receiving a request for storage allocation comprising a plurality of storage attributes including capacity and at least one performance and/or availability criterion. The method further includes identifying a logical unit having at least one designated storage characteristic that satisfies the at least one criterion and having an available storage space that satisfies the capacity and allocating at least a portion of the identified logical unit for storage associated with the request.

Abstract: Embodiments of the present invention provide a method of a first processor using a memory resource associated with a second processor. The method includes receiving a memory instruction from a first processor process, wherein the memory instruction refers to a shared memory address (SMA) that maps to a second processor memory. The method also includes mapping the SMA to the second processor memory, wherein the mapping produces a mapping result and providing the mapping result to the first processor.

Abstract: A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.

Abstract: Provided is a method, which may be performed on a computer, for prefetching data over an interface. The method may include receiving a first data prefetch request for first data of a first data size stored at a first physical address corresponding to a first virtual address. The first data prefetch request may include second data specifying the first virtual address and third data specifying the first data size. The first virtual address and the first data size may define a first virtual address range. The method may also include converting the first data prefetch request into a first data retrieval request. To convert the first data prefetch request into a first data retrieval request the first virtual address specified by the second data may be translated into the first physical address. The method may further include issuing the first data retrieval request at the interface, receiving the first data at the interface and storing at least a portion of the received first data in a cache.

Abstract: A file-mapped volume is a logical volume in which the data storage of the logical volume is the data storage of a regular file associated with the logical volume. The regular file can be a file of a first file system, and a second file system can be built upon the file-mapped volume. These two file systems can have distinct inode address spaces, yet files of the first file system are easily moved to the second file system by changing pointers to inodes of these files. The second file system can be easily copied, attached, or transported by copying, attaching, or transporting the regular file containing the second file system, yet files in the second file system can be accessed in real time via file access routines of the operating system.

Abstract: Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory section of a redundant memory array. One such memory includes a fuse block having programmable elements configured to be programmed to identify main memory sections to be mapped to redundant memory sections of the redundant memory array. The memory further includes a redundant memory logic circuit coupled to the redundant memory array and the fuse block. The redundant memory logic is configured to map the memory for a main memory section identified in the fuse block to at least one of the redundant memory sections of the redundant memory array.

Abstract: In general, a technique or mechanism is provided to efficiently transfer data of a distributed file system to a parallel database management system using an algorithm that avoids or reduces sending of blocks of files across computer nodes on which the parallel database management system is implemented.

Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.

Abstract: Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk.

Abstract: A storage device includes a host interface, a buffer memory, a storage medium, and a controller. The host interface is configured to receive storage data and an invalidation command, where the invalidation command is indicative of invalid data among the storage data received by the host interface. The buffer memory is configured to temporarily store the storage data received by the host interface. The controller is configured to execute a transcribe operation in which the storage data temporarily stored in the buffer memory is selectively stored in the storage medium. Further, the controller is responsive to receipt of the invalidation command to execute a logging process when a memory capacity of the invalid data indicated by the invalidation command is equal to or greater than a reference capacity.

Abstract: A command receiver receives, from an external access requesting entity, a command with which to access data, together with an address to be accessed and IOID to identify the access requesting entity. Based on the IOID, the access decision unit determines whether or not an access is one that is to be permitted for an access requesting entity to access a region of access destination. The access decision unit determines whether access of the access requesting entity is permitted or not, for each page that serves as the basic management unit of logical address in the processor space.

Abstract: Systems and processes may use a first memory, a second memory, and a memory controller. The second memory is at least as large as a block of the first memory. Data is received and stored in the second memory for further writing to the second memory.

Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: According to one embodiment, a memory system includes a controller for controlling a data transfer between a nonvolatile memory and a host device. The controller writes, to the nonvolatile memory, management information to be used in the data transfer, a multiplexed pointer indicating a storage position, and a log indicating whether the writing of the pointer is successful, determines whether the multiplexing the pointer by the predetermined number is maintained according to at least one of the pointer and the log, and rewrites the multiplexed pointers to the nonvolatile memory when determining that the multiplexing the pointer by the predetermined number is not maintained.

Abstract: Provided are a computer program product, system and method for managing Input/Output (I/O) requests to a storage device. In response to a write request, a determination is made as to whether preserve mode is enabled. A first entry is located in a volume control table for the logical address to write indicating a version number of the data and a first physical location in the storage device. The write data is written to a second physical location in the storage device. If the preserve mode is enabled, a second entry is added to the volume control table for the logical address, the volume control table is updated to have the first or second entry for the logical address point to the second physical location and indicate a current version, and the first or second entry not indicating the current version indicates the first physical location and a previous version.

Abstract: A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.

Abstract: Network computing systems are disclosed including a shared memory cloud coupled to one or more processor complexes. The shared memory cloud has an interconnect network coupled to disk-read-only-memories (disk-ROMs) each including a memory array that is read/write block accessible to access blocks of consecutive memory locations and random read memory accessible to access random memory locations. The processor complexes read and write blocks of data from/to the disk-ROMs to provide disk-like access to the shared memory cloud. Each processor complex maps the addresses of one or more of the disk-ROMs into processor address spaces, and reads from random memory locations of one or more of the disk-ROMs to provide main memory-like access to the shared memory cloud. The network computing systems may further include a power controller coupled to the processor complexes. The power controller can keep the disk-ROMS powered on while it powers off inactive processor complexes.

Abstract: Example embodiments described herein may relate to memory devices, and may relate more particularly to configurable address space for non-volatile memory devices.

Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.

Abstract: In an embodiment of the invention, an apparatus and method for storage space management performs the steps including: activating a logical volume group; reading pattern-based mapping information from physical volumes in the logical volume group; and using the pattern-based mapping information to determine a target physical extent in at least one of the physical volumes for a received request.

Abstract: A data writing method for writing data belonging to a logical page into a rewritable non-volatile memory module is provided. In the data writing method, a mark count value is set for each logical page. Whether the mark count value corresponding to the logical page is greater than a predetermined threshold is determined. If the mark count value corresponding to the logical page is not greater than the predetermined threshold, the mark count value corresponding to the logical page is counted, and the data and the mark count value corresponding to the logical page are written into a first storage area or a second storage area. Otherwise, the data and the mark count value corresponding to the logical page are written into the second storage area. Thereby, data stored in the rewritable non-volatile memory module can be effectively identified and data loss caused by power failure can be avoided.

Abstract: An information processing apparatus sequentially selects a function whose execution frequency is high as a selected function that is to be stored in an internal memory, in a source program having a hierarchy structure. The information processing apparatus allocates the selected function to a memory area of the internal memory, allocates a function that is not the selected function and is called from the selected function to an area close to the memory area of the internal memory, and generates an internal load module. The information processing apparatus allocates a remaining function to an external memory coupled to a processor and generates an external load module. Then, a program executed by the processor having the internal memory is generated.

Abstract: Method for accessing data in a storage system architecture, the architecture comprises at least one disk array subsystem, comprising the following steps. Provide a SAS for managing a first and a second media extent (ME) the at least one subsystem. Obtain a location index corresponding to a host LBA via a BAT. Obtain a location information of a physical section located in the first ME corresponding to the location index via a physical section to virtual section cross-referencing functionality. Update the cross-reference in the cross-referencing functionality so that the location information obtained from the cross-referencing functionality corresponding to the location index is the location information of the second physical section. A host IO request addressing the host LBA accesses data in the second physical section utilizing the location information of the second physical section.

Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.

Abstract: Systems and methods may provide for receiving a scatter/gather list that identifies a contiguous data block in a physical memory, and splitting the contiguous data block into a first data packet payload and a second data packet payload based on a target packet size. Additionally, another contiguous data block can be combined into one of the first and second data packet payloads based on the target packet size, wherein the first and second data packet payloads may be transferred in a data stream through a host interface that does not support scatter/gather lists. In one example, a software driver is used to split and combine the contiguous data blocks.

Abstract: Provided are a method, system, and program for utilizing a virtualized data structure table such as an address translation and protection table (TPT), for example, in an I/O device. The virtualized data structure table has virtually contiguous data structures but not necessarily physically contiguous data structures in system memory. The data structure table may be accessed in a virtually contiguous manner. In the illustrated embodiment, the table is subdivided at a first hierarchal level into a plurality of virtually contiguous units or segments. Each unit or segment is in turn subdivided at a second hierarchal level into a plurality of virtually contiguous subunits, subsegments, pages or blocks. Each page or block is in turn subdivided at a third hierarchal level into a plurality of physically contiguous table entries.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract: Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Abstract: A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read operations is provided including a nonvolatile memory; a volatile memory for storing file management information of the nonvolatile memory; a controller for controlling the nonvolatile memory and the volatile memory; and a power supply maintaining unit for supplying power to the nonvolatile memory, the volatile memory, or the controller upon power shutdown. The controller reads the file management information in the nonvolatile memory upon power-on and writes the same in the volatile memory, and read and write operations are performed based on the file management information in the volatile memory, and the file management information in the volatile memory is written in the nonvolatile memory upon power shutdown.

Abstract: A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A1), providing a second nonvolatile physical memory zone (A2), and, in response to a write command of an initial data, searching for a first erased location in the first memory zone, writing the initial data (DT1a) in the first location (PB1(DPP0)), and writing, in the metadata (DSC0) an information (DS(PB1)) allowing the first location to be found and an information (LPA, DS(PB1)) forming a link between the first location and the location of the data in the virtual memory.

Abstract: In a data read-and-write controlling device, without waiting for confirmation that data is written in a RAM, data is written in a WER and an ADR, and at the same time, address information of the data is written in the RAM write-information table. That is, the data read-and-write controlling device associates an address retained at a data register of a write controlling unit with the value (a write request is present=“1”) of a write request that makes a request for writing data in the RAM, the value being retained in a write request register, and then causes the result to be stored in the RAM write-information table as the address information.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output.

Abstract: Embodiments of the present technical solution relate to the technique field of storage, and disclose a server and a method for the server to access a volume. The method comprises: determining, from a first list, a block that needs to be accessed according to an access offset of a volume that needs to be accessed; determining, from a second list, a storage controller corresponding to the block that needs to be accessed according to the determined block; and sending a data reading request or a data writing request to the storage controller corresponding to the block that needs to be accessed to process. Embodiments of the present invention can reduce time delay when the data reading request or the data writing request of the server reaches the block that needs to be accessed.

Abstract: A cache controller in a computer system is configured to manage a cache. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.

Abstract: In response to detecting a PCI host bridge (PHB), a first address translation table may be allocated in a first portion of a memory. The first address translation table may be associated with the PHB. If an input/output adapter accessible to the PHB is configured as a virtualized adapter, a first table manager may be assigned to manage the first address translation table. The first address translation table may be configured for an initial number of virtual functions. If a requested number of virtual functions is greater than the initial number of virtual functions, additional virtual functions may be configured. A second address translation table may be allocated in a second portion of the memory. The second portion of the memory may be non-contiguous with reference to the first portion of the memory. Entries may be created in the second address translation table for the additional virtual functions.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.

Abstract: A controller, techniques, systems, and devices for optimizing throughput of read operations in flash memory are disclosed. Various optimizations of throughput for read operations can be performed using a controller. In some implementations, read operations for a multi-die flash memory device or system can be optimized to perform a read request with a highest priority (e.g., an earliest received read request) as soon as the read request is ready. In some implementations, the controller can enable optimized reading from multiple flash memory dies by monitoring a read/busy state for each die and switching between dies when a higher priority read operation is ready to begin.

Abstract: An apparatus and method for processing non-sequentially stored data is provided. The data processing apparatus may include an order information mapping unit to map transmission order information to data, an address list generating unit to generate an address list including addresses of the data arranged sequentially based on the transmission order information, and a data processing unit to process the data corresponding to each of the addresses based on an address order of the address list.

Abstract: A method of manipulating data includes receiving a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The method further includes mapping the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command. A system for manipulating data includes a host and a flash translation layer. The host transmits a data manipulation command for corresponding data, which corresponds to a first logical block address, to a second logical block address. The flash translation layer maps the second logical block address to a physical block address, which is mapped to the first logical block address, in response to the data manipulation command.

Abstract: An apparatus, system, and method are disclosed for caching data. A storage request module detects an input/output (“I/O”) request for a storage device cached by solid-state storage media of a cache. A direct mapping module references a single mapping structure to determine that the cache comprises data of the I/O request. The single mapping structure maps each logical block address of the storage device directly to a logical block address of the cache. The single mapping structure maintains a fully associative relationship between logical block addresses of the storage device and physical storage addresses on the solid-state storage media. A cache fulfillment module satisfies the I/O request using the cache in response to the direct mapping module determining that the cache comprises at least one data block of the I/O request.

Abstract: During runtime of a binary program file, streams of instructions are executed and memory references, generated by instrumentation applied to given ones of the instructions that refer to memory locations, are collected. A transformation is performed, based on the executed streams of instructions and the collected memory references, to obtain a table. The table lists memory events of interest for active data structures for each function in the program file. The transformation is performed to translate memory addresses for given ones of the instructions and given ones of the data structures into locations and variable names in a source file corresponding to the binary file. At least the memory events of interest are displayed, and the display is organized so as to correlate the memory events of interest with corresponding ones of the data structures.

Abstract: A method includes forming a memory device through providing an array of non-volatile memory cells including one or more non-volatile memory cell(s) and an array of volatile memory cells including one or more volatile memory cell(s) on a substrate. The method also includes appropriately programming an address translation logic associated with the memory device through a set of registers associated therewith to enable configurable mapping of an address associated with a sector of the memory device to any memory address space location in a computing system associated with the memory device. The address translation logic is configured to enable translation of an external virtual address associated with the sector of the memory device to a physical address associated therewith.

Abstract: A memory controller provided according to an aspect of the present invention includes a predictor block which predicts future read requests after converting the memory address in a prior read request received from the processor to an address space consistent with the implementation of a memory unit. According to another aspect of the present invention, the predicted requests are granted access to a memory unit only when there are no requests pending from processors and the peripherals sending access requests to the memory unit.