Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: A method of performing cascaded flashcopy (FC) including starting a flashcopy map when a target disk is already a source of an active FC map. A computer storage system includes a configuration that allows a flashcopy (FC) map to be started when a target disk is already the source of an active FC map.

Abstract: In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.

Abstract: The present invention is directed to a method and software for managing the host-to-volume mappings of a SAN storage system. The host-to-volume mappings of the SAN storage system are represented in mapping configuration components. The active mapping configuration component represents the current host-to-volume mapping for the SAN storage system. Only one mapping configuration component is active at a time. The host-to-volume mappings of a SAN storage system are changed by deactivating the active mapping configuration component and activating an inactive mapping configuration component that represents a different mapping configuration, effecting a repartition, repurpose, disaster recovery, or other business activity. This can be a scheduled task or performed in an on-demand manner. The mapping configuration components are managed and controlled through the management component of the SAN storage system.

Abstract: A baseboard management controller is disclosed. The baseboard management controller adapted to monitor a host comprises a baseboard management control module, a memory controller and a video graphic array (VGA) module. The VGA module comprises a video controller, a decoder, a select circuit and a mapping circuit. The decoder receives a transaction signal from a first local bus and decodes a first address signal contained in the transaction signal. The select circuit selectively transfers data from one of the microprocessor bus, the video controller and the memory controller back to the first local bus according to a control signal. The mapping circuit being connected with the decoder maps the first address signal and a second address signal to a third address signal, updates the first address signal and transfers an updated transaction signal.

Abstract: A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.

Abstract: A memory access technique that provides for overriding a translation lookaside buffer and page table data structure, in accordance with one embodiment of the present invention, includes selectively translating a virtual address directly to a physical address utilizing an adjustment in a context specifier, or translating the virtual address to the physical address utilizing a translation lookaside buffer or page table data structure.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. For a system configuration that includes partitions, the translation mechanism to be used for a partition or a portion thereof is selectable and may be different for different partitions or even portions within a partition.

Abstract: A method begins by a processing module determining an imbalance between inode utilization and data storage utilization. When the imbalance compares unfavorably to an imbalance threshold, the method continues with the processing module determining whether utilization of another inode memory and utilization of another corresponding data storage memory are not imbalanced. When the utilization of the other inode memory and the utilization of the other corresponding data storage memory are not imbalanced, determining whether the inode utilization is out of balance with respect to the data storage utilization. When the inode utilization is out of balance, the method continues with the processing module transferring data objects from a data storage memory to the other corresponding data storage memory and transferring mapping information of data objects from a inode memory to the other inode memory.

Abstract: Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.

Abstract: The amount of virtual disk space available for use by software executing within a virtual machine (VM) may be dynamically adjusted while the VM is running in a virtual computer system. A method for reservation of disk space from a virtual machine is provided. A request is received at a first VM relating to reserving a portion of a virtual disk used by the first VM. In response, the first VM allocates additional storage in the virtual disk to a guest file stored in the virtual disk, wherein the guest file is not used to store meaningful data and then communicates sectors of the virtual disk corresponding to the additional storage to the virtualization layer. The virtualization layer provides to a second VM access to sectors of the physical storage space that correspond to the sectors of the virtual disk that were allocated as additional storage to the guest file.

Abstract: A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

Abstract: Provided are a system, method, and computer program product for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached.

Abstract: A memory controller implements flexible memory mapping for storage of data units in a memory. The memory controller logically partitions the memory into a plurality of blocks or block segments and manages the storage of data units among the plurality of blocks/block segments. The memory controller can operate in one of three modes: a monolithic mode whereby the memory is modeled as a plurality of blocks, whereby each block is treated as a “monolithic” block; a fragmented mode whereby the memory is modeled as a plurality of blocks segments of varying sizes; and a combined mode whereby the memory is initially partitioned into a plurality of equal-sized blocks, and whereby each block can be used as a monolithic block or a fragmented block comprising a plurality of block segments of different sizes, and wherein monolithic blocks can be converted to fragmented blocks and fragmented blocks can be converted back to monolithic blocks.

Abstract: An arithmetic processing apparatus includes: a plurality of TLBs holding as entries a portion of a conversion table for conversion of virtual addresses into physical addresses that has been placed in a main memory unit; an entry registration determining unit that, while registering an entry output from the main memory unit in any one of a plurality of TLBs, determines whether an entry has already been registered in an area of a TLB as registration destination; and a relocation control unit that, when the entry registration determining unit determines that an entry has already been registered in the area of the TLB as registration destination, evicts the entry that has already been registered and registers evicted entry in other TLB.

Abstract: Provided is a method for managing cache memory to cache data units in at least one storage device. A cache controller is coupled to at least two flash bricks, each comprising a flash memory. Metadata indicates a mapping of the data units to the flash bricks caching the data units, wherein the metadata is used to determine the flash bricks on which the cache controller caches received data units. The metadata is updated to indicate the flash brick having the flash memory on which data units are cached.

Abstract: There are described tools and methodologies for building Read Only Memory (ROM) mask software images and the corresponding data/code patching software images. One method is for creating ROM mask content having patch references included therein whereby patch reference errors are detected and corrected. A software patch for a ROM mask with existing patch references may then automatically be created.

Abstract: Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.

Abstract: A method begins by a processing module determining an imbalance between inode memory utilization and data storage memory utilization. When the imbalance compares unfavorably to an imbalance threshold, the method continues with the processing module determining whether the inode memory utilization is out of balance with respect to the data storage memory utilization or whether the data storage memory utilization is out of balance with respect to the inode memory utilization. When the inode memory utilization is out of balance with respect to the data storage memory utilization, the method continues with the processing module transferring a set of data objects from a data object section to a data block section and transferring object mapping information of the set of data objects into block mapping information for the set of data objects.

Abstract: Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a particular address. One such apparatus includes memory devices configured to selectively adjust an input impedance seen by one or more of the signal lines in response to receiving a particular address.

Abstract: A storage library is described that includes a tape magazine that possesses at least one spare slot and a number of other addressable slots that each contains a tape cartridge. Each addressable slot is mapped and made known to a host when the host is linked to the storage library. One of the addressable slots contains a tape cartridge that prior to being mapped as an addressable slot was formerly a spare slot unmapped to the host and the current spare slot was formerly mapped as an addressable slot.

Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.

Abstract: Data blocks are copied from a source (e.g., a source virtual disk) to a target (e.g., a target virtual disk). The source virtual disk format is preserved on the target virtual disk. Offsets for extents stored in the target virtual disk are converted to offsets for corresponding extents in the source virtual disk. A map of the extents for the source virtual disk can therefore be used to create, for deduplication, segments of data that are aligned to boundaries of the extents in the target virtual disk.

Abstract: The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.

Abstract: Conventionally, when a switch virtualizing a storage (storage virtualization switch) is installed in a computer system including an SAN, a host computer, and a storage device, since a port ID of a virtual storage and a port ID of a storage device assigned to the virtual storage are different, the computer system has to be suspended at the time of installation of the storage virtualization switch. The storage virtualization switch installed in the computer system assigns a port ID to a port of a virtual storage generated by the storage virtualization switch so as to be equivalent to a port ID of an existing storage device and, in the case in which the port ID is designated as an access destination by an access request from one computer to the storage device, sends the access request to the virtual storage.

Abstract: A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.

Abstract: This disclosure relates to parity declustered storage device arrays having partition groups. In an exemplary embodiment, the storage system includes a storage device array, such as disk array. Each storage device is divided into partitions. Each partition includes stripe units, such as hundreds or thousands of stripe units in exemplary embodiments. The storage system also includes a physical array controller coupled to the storage device array. In an exemplary embodiment, the array controller includes a partition group lookup table and stores and retrieves data and parity in the storage devices based on the partition group lookup table. In this exemplary embodiment, the array controller also includes a stripe lookup table and/or a log. In an exemplary embodiment, the partition group lookup table and the stripe lookup table take up less memory (e.g., by an order of magnitude) than a single-level stripe map conveying the same information.

Abstract: A storage control device for controlling the storage device including a medium for storing data, logical address information, and address translation information and a memory for storing the address translation information read from the medium includes a first receiver for receiving a write request including logical address information, a first sending module for sending a read request including the logical address information of the write request to the storage device, a second receiver for receiving data and logical address information stored in the medium in accordance with the read request from the storage device, and a second sending module for sending an instruction to cause the storage device to write the address translation information stored in the medium into the memory when the logical address information received by the second receiver is different from logical address information included in the write request.

Abstract: An access request including a client address for data is received. A metadata server determines a mapping between the client address and storage unit identifiers for the data. Each of the one or more storage unit identifiers uniquely identifies content of a storage unit and the metadata server stores mappings on storage unit identifiers that are referenced by client addresses. The one or more storage unit identifiers are sent to one or more block servers. The one or more block servers service the request using the one or more storage unit identifiers where the one or more block servers store information on where a storage unit is stored on a block server for a storage unit identifier. Also, multiple client addresses associated with a storage unit with a same storage unit identifier are mapped to a single storage unit stored in a storage medium for a block server.

Abstract: A memory and a method for controlling a memory including: a set of first memory blocks of identical size, intended to contain first words, a set of second memory blocks of identical size, intended to contain second words, the number of second words being identical to the number of first words, a third memory block identical to the first blocks, a fourth memory block identical to the second blocks, each memory address comprising a first portion identifying a same line in all blocks, and each first word of the third block identifying a free word from among the second words sharing a same second address portion.

Abstract: A data storage device is disclosed comprising a non-volatile memory. A write command is received comprising a first logical block address (LBA) and first user data, and a second LBA and second user data. The first LBA is mapped to a first physical block address (PBA) for addressing a first memory segment. The second LBA is mapped to a second PBA for addressing a second memory segment. First redundancy is generated in response to the first user data, second redundancy in generated in response to the second user data, and parity data is generated in response to the first and second user data. Third redundancy is generated in response to the parity data and in response to at least one of the first LBA and the first PBA and at least one of the second LBA and the second PBA.

Abstract: A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.

Abstract: Provided are a computer program product, system, and method for converting a first address mapping function for mapping addresses to storage locations to a second address mapping function. For each of a plurality of addresses allocated in the storage using the first address mapping function, a node is generated in the second address mapping function. Each node in the second address mapping function associates a logical address with a physical location for the logical address. A determination is made of addresses having unused space and storage space is freed for the determined addresses having the unused space. Indication is made in the second address mapping function that the storage space for the determined addresses has been freed.

Abstract: A data storage device is disclosed including a non-volatile media having a first and a second plurality of physical locations, the first plurality of physical locations storing user data and the non-volatile media storing first metadata associating each of the first plurality of physical locations with a logical block address (LBA), and a mapping table including a mapping of each LBA to a current physical location. The data storage device further includes control circuitry that reads the first metadata to obtain a first plurality of LBAs, reads the mapping table to determine a current physical location for the first plurality of LBAs, and compares the current physical location of each of the first plurality of LBAs to a corresponding one of the first plurality of physical locations to identify valid user data in the first plurality of physical locations for migration into the second plurality of physical locations.

Abstract: The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command.

Abstract: According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between a bit line of the port A and the port A based on a first clock and data is exchanged between the bit line of the port A and the port B based on a second clock.

Abstract: A memory mapping apparatus for a multi-processing unit includes at least one memory matching unit configured to perform matching between a plurality of processing units and a plurality of memories, a memory controller configured to perform access control and arbitration for the respective memories, a memory mapping unit configured to include a window map for the respective processing units, make correspond the memories to the respective processing units with reference to the window map, and assign part of the entire address region of the corresponding memory, and a window map change unit configured to change a window map for a processing unit in which a request to use the memory has occurred in response to a request to use the memory from any one of the processing units.

Abstract: Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object.

Abstract: An audio decoder has an arithmetic decoder for providing decoded spectral values on the basis of an arithmetically-encoded representation and a frequency-domain-to-time-domain converter for providing a time-domain audio representation. The arithmetic decoder selects a mapping rule describing a mapping of a code value onto a symbol code in dependence on a numeric current context value describing a current context state. The arithmetic decoder determines the numeric current context value in dependence on a plurality of previously decoded spectral values. The arithmetic decoder evaluates at least one table using an iterative interval size reduction to determine whether the numeric current context value is identical to a table context value described by an entry of the table or lies within an interval described by entries of the table, and derives a mapping rule index value describing a selected mapping table. An audio encoder also uses an iterative interval table size reduction.

Abstract: A storage apparatus and its control method capable of implementing thin provisioning and reducing power consumption of storage devices are provided. The storage apparatus classifies a plurality of storage devices, which provide a pool with a storage resource, into a plurality of groups; performs thin provisioning operation by setting some of the plurality of groups to an active mode, in which the storage devices belonging to the groups are made to enter an activated state; sets other groups to a power-saving mode in which the storage devices are made to enter a power-saving state; and sequentially switches between the group(s) in the active mode and the group(s) in the power-saving mode among the plurality of groups.

Abstract: A method for concurrently converting a standard volume to a thin-provisioned volume includes initially establishing metadata for a thin-provisioned volume. The method then updates the metadata for the thin-provisioned volume to point to extents residing in a standard volume. The method then suspends I/O to metadata for the standard volume. Upon suspending the I/O, the method migrates control of the extents in the standard volume from a standard-volume control algorithm to a thin-provisioned-volume control algorithm. The method then resumes the I/O to the metadata for the thin-provisioned volume. Using this technique, standard volumes may be rapidly converted to thin-provisioned volumes while minimally disrupting I/O to the volumes. A corresponding apparatus and computer program product are also disclosed and claimed herein.

Abstract: A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.

Abstract: In the computer system, a storage system provides a storage level virtual volume based on thin provisioning technology, to a physical server on which a virtual machine is defined. The storage system releases the area of the logical volume corresponding to the storage level virtual volume accessed by a virtual machine which is specified to be deleted, on the basis of storage level virtual volume conversion information which is managed by the storage system.

Abstract: Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time.

Abstract: According to one embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured to receive a mount request to access at least one host data record on a virtual tape storage (VTS) system; computer readable program code configured to determine a number of host compressed data records per physical block on a magnetic tape medium; computer readable program code configured to determine a physical block ID (PBID) that corresponds to the requested at least one host data record; computer readable program code configured to access a physical block on the magnetic tape medium corresponding to the PBID; and computer readable program code configured to output the physical block without outputting an entire logical volume from the magnetic tape medium that the physical block is stored to. Other systems and computer program products are also described.

Abstract: Described embodiments provide a media controller that receives requests that include a logical address and address range. In response to the request, the media controller determines whether the received request is an invalidating request. If the received request type is an invalidating request, the media controller uses a map to determine one or more entries of the map associated with the logical address and range. Indicators in the map associated with each of the map entries are set to indicate that the map entries are to be invalidated. The media controller acknowledges to a host device that the invaliding request is complete and updates, in an idle mode of the media controller, a free space count based on the map entries that are to be invalidated. The physical addresses associated with the invalidated map entries are made available to be reused for subsequent requests from the host device.

Abstract: A data processing method for a nonvolatile memory system is described. In the method, a host CPU calls N data file segments, generates logical addresses, and then transfers the N data file segments and logical addresses to an ASIC. The ASIC then maps the logical addresses onto physical addresses of a nonvolatile memory, derives N payload data segments, and collectively generates corresponding metadata for all of the N payload data segments. Then, a single multi-segment transfer operation is performed to sequentially write the N payload data segments to a data block in the nonvolatile memory, and thereafter, write the corresponding metadata to a metadata block associated with the data block.

Abstract: An audio decoder includes an arithmetic decoder for providing a plurality of decoded spectral values on the basis of an arithmetically encoded representation of the spectral values, and a frequency-domain-to-time-domain converter for providing a time-domain audio representation using the decoded spectral values. The arithmetic decoder selects a mapping rule describing a mapping of a code value onto a symbol code in dependence on a context state described by a numeric current context value. The arithmetic decoder determines the numeric current context value in dependence on a plurality of previously decoded spectral values. The arithmetic decoder evaluates a hash table, entries of which define both significant state values and boundaries of intervals of numeric context values, in order to select the mapping rule. A mapping rule index value is individually associated to a numeric context value being a significant state value.

Abstract: A system and method is illustrated wherein a protocol agent module receives a memory request encoded with a protocol, the memory request identifying an address location in a memory module managed by a buffer. Additionally, the system and method includes a memory controller to process the memory request to identify the buffer that manages the address location in the memory module. Further, the system and method includes an address mapping module to process the memory request to identify at least one super page associated with the memory module, the at least one super page associated with the address location.

Abstract: Embodiments of the invention include systems and methods for auto-tiering multiple file systems across a common resource pool. Storage resources are allocated as a sub-LUN auto-tiering (SLAT) sub-pool. The sub-pool is managed as a single virtual address space (VAS) with a virtual block address (VBA) for each logical block address of each data block in the sub-pool, and a portion of those VBAs can be allocated to each of a number of file systems. Mappings are maintained between each logical block address in which file system data is physically stored and a VBA in the file system's portion of the virtual address space. As data moves (e.g., is added, auto-tiered, etc.), the mappings can be updated. In this way, multiple SLAT file systems can exploit the full resources of the common SLAT sub-pool and maximize the resource options available to auto-tiering functions.