Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
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Patent number: 8832391Abstract: In one embodiment, the semiconductor device includes a data control unit configured to selectively process data for writing to a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group of processing functions including at least three processing functions. The enabled processing function may be performed based on a signal received over a single pin associated with the group of processing functions. In another embodiment, the semiconductor device includes a data control unit configured to process data read from a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a read operation. Here, the group of processing functions including at least two processing functions.Type: GrantFiled: November 15, 2010Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jung-Hwan Choi
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Patent number: 8825947Abstract: The present invention is directed to systems and methods for improving access to non-volatile solid-state storage systems. Embodiments described herein provide a physical chunk number (PCN), or a physical page number (PPN), by which a controller can access the next available chunks (or pages) in a programming sequence optimized by concurrency. By incrementing the PCN, the controller can program consecutive chunks in the optimized programming sequence. In one embodiment, the programming sequence is determined at the time of initial configuration and the sequence seeks to synchronize data programming and data sending operations in subcomponents of the storage system to minimize contention and wait time. In one embodiment, the PCN includes an index portion to a superblock table with entries that reference specific blocks within the subcomponents in a sequence that mirrors the optimized programming sequence, and a local address portion that references a particular chunk to be programmed or read.Type: GrantFiled: April 16, 2013Date of Patent: September 2, 2014Assignee: Western Digital Technologies, Inc.Inventor: Mei-Man L. Syu
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Patent number: 8826023Abstract: Various methods and systems for securing access to hash-based storage systems are disclosed. One method involves receiving information to be stored in a storage system from a storage system client and then generating a key. The key identifies the information to be stored. The value of the key is dependent upon a secret value, which is associated with the storage system. The key is generated, at least in part, by applying a hash algorithm to the information to be stored. The key can then be returned the key to the storage system client. The storage system client can then use the key to retrieve the stored information.Type: GrantFiled: June 30, 2006Date of Patent: September 2, 2014Assignee: Symantec Operating CorporationInventor: Craig K. Harmer
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Publication number: 20140244964Abstract: The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted.Type: ApplicationFiled: February 28, 2013Publication date: August 28, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Patrick R. Khayat, Sivagnanam Parthasarathy, Mustafa N. Kaynak
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Patent number: 8819392Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.Type: GrantFiled: July 17, 2012Date of Patent: August 26, 2014Assignee: Intel CorporationInventors: David Champagne, Abhishek Tiwari, Wei Wu, Christopher J. Hughes, Sanjeev Kumar, Shih-Lien Lu
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Patent number: 8819359Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.Type: GrantFiled: June 29, 2009Date of Patent: August 26, 2014Assignee: Oracle America, Inc.Inventors: Sanjiv Kapil, Blake Alan Jones
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Patent number: 8819388Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.Type: GrantFiled: July 17, 2012Date of Patent: August 26, 2014Assignee: Intel CorporationInventors: Zhen Fang, Mahesh Wagh, Jasmin Ajanovic, Michael E. Espig, Ravishankar Iyer
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Patent number: 8819389Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.Type: GrantFiled: April 25, 2013Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Charles J. Archer, Gary R. Ricard
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Patent number: 8819365Abstract: Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used to determine the available locations and amount of available space in the storage devices. The data storage schemes for one or more of the stored data files are changed to a basic storage mode when the size of a new data file configured in accordance with an assigned data storage scheme exceeds the amount of available space. The configured new data file is stored in accordance with the assigned data storage scheme in one or more of the available locations and the locations of the new data file are recorded.Type: GrantFiled: June 6, 2011Date of Patent: August 26, 2014Inventor: Gary Stephen Shuster
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Patent number: 8819088Abstract: Techniques are provided for accessing sector data. An embedded storage function is received. One or more data management functions are generated in response to receiving the embedded storage function. The one or more data management functions are invoked to retrieve the sector data from a sector table.Type: GrantFiled: July 14, 2005Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Balakrishna Raghavendra Iyer, Lin S. Qiao, Aamer Sachedina
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Patent number: 8819384Abstract: Aspects of the disclosure provide a virtual memory management method that can reduce memory requirement and improve system performance. The method can include detecting a scenario, matching the detected scenario with a predefined scenario that includes a pre-set mapping relationship of a first module to a dynamic memory address within a first portion of a dynamic memory, and writing the first module from a static memory to the first portion of the dynamic memory at the dynamic memory address. Further, the method can include executing the first module from the dynamic memory. In addition, the method can include storing a second module at a second portion of the dynamic memory independent of the detected scenario.Type: GrantFiled: May 15, 2008Date of Patent: August 26, 2014Assignee: Marvell International Ltd.Inventor: Deepak Kumar Gauba
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Patent number: 8819383Abstract: One or more techniques and/or systems are provided for non-disruptively addressing misalignment between a virtual data format and an underlying data format. Virtual data, such as a guest operating system of a virtual machine, may be stored within a virtual structure, such as a virtual machine disk, according to a virtual data format. The virtual structure may be stored within a storage device according to a storage data format. If misalignment is detected, then a new data container may be created within the storage device. A shim, sized according to a misalignment offset, may be inserted into the new data container in order to align the new data container with the storage device. Virtual data may be migrated from the virtual structure to the new data container to achieve alignment. During the migration, the virtual data may remain available from the virtual structure (e.g., a virtual machine may still execute).Type: GrantFiled: February 17, 2012Date of Patent: August 26, 2014Assignee: NetApp, Inc.Inventors: Varun Jobanputra, Andrew Tucker, Eric Paul Forgette, Subramaniam V. Periyagaram, Mohit Gupta, Jose Mathew, Vishwajith Shivappa, Sisir Shekhar
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Patent number: 8819386Abstract: When a dynamic data structure is used for managing sparsely accessed data stored in memory of a digital computer, pages of the memory are dynamically allocated and de-allocated to respective portions of the dynamic data structure so that the pages become distributed over the portions of the dynamic data structure and the de-allocated pages include free pages that are mapped in the dynamic data structure and free pages that are not mapped in the dynamic data structure. To reduce memory fragmentation and recover memory, upon de-allocating a page of memory from a portion of the data structure, a determination is made whether or not to un-map the de-allocated page from the portion of the dynamic data structure so that un-mapping of the de-allocated page has a probability that is the inverse of a superlinear function of the number of allocated pages in the portion of the dynamic data structure.Type: GrantFiled: January 25, 2011Date of Patent: August 26, 2014Assignee: EMC CorporationInventor: Clifford Mather
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Patent number: 8819346Abstract: A computer implemented method analyzes shared memory accesses during execution of an application program. The method includes instrumenting events of shared memory accesses in the application program, where the application program is to be executed on a target configuration having p nodes; executing the application program using p1 processing nodes, where p1 is less than p and satisfies a constraint. For accesses made by the executing application program, the method determines a target thread and maps determined target threads to either a remote node or a local node corresponding to a remote memory access and to a local memory access, respectively. Also disclosed is a computer-readable storage medium that stores a program of executable instructions that implements the method, and a data processing system. The invention can be implemented using a language such as Unified Parallel C (UPC) directed to a partitioned global address space (PGAS) paradigm.Type: GrantFiled: March 9, 2012Date of Patent: August 26, 2014Assignee: International Business Machines CorporationInventors: Guojing Cong, Ettore Tiotto, Hui-Fang Wen
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Patent number: 8819385Abstract: A method for accessing a flash memory, the method includes: receiving a read request that is associated with a logical address that is mapped to a physical address of a set of flash memory cells; accessing multiple mapping data structures of different granularity to obtain the physical address of the set of flash memory cells; wherein during at least one point in time at least one mapping data structure is stored in an erase block and wherein the erase block comprises multiple physical pages that are written in a sequential manner and are associated with logical page addresses that are assigned in a random manner; and reading a content of the set of flash memory cells.Type: GrantFiled: July 27, 2009Date of Patent: August 26, 2014Assignee: Densbits Technologies Ltd.Inventors: Boris Barsky, Avigdor Segal, Igal Maly
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Patent number: 8819387Abstract: A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.Type: GrantFiled: September 8, 2011Date of Patent: August 26, 2014Assignee: Phison Electronics Corp.Inventor: Wei-Chen Teo
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Patent number: 8819378Abstract: A data processing apparatus has processing circuitry for executing a memory access instruction in order to generate a memory transaction comprising at least one address transfer specifying a memory address, and at least one associated data transfer specifying data to be accessed at the specified memory address. The apparatus is arranged to route each address transfer and associated data transfer via a first interface when the specified memory address is within a first memory address range, or to route each address transfer and associated data transfer via a second interface when the specified memory address is within a second memory address range and is further configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing.Type: GrantFiled: November 14, 2011Date of Patent: August 26, 2014Assignee: ARM LimitedInventor: Simon John Craske
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Publication number: 20140237211Abstract: The present invention provides a system and method for virtual block numbers (VBNs) to disk block number (DBN) mapping that may be utilized for both single and/or multiple parity based redundancy systems. Following parity redistribution, new VBNs are assigned to disk blocks in the newly added disk and disk blocks previously occupied by parity may be moved to the new disk.Type: ApplicationFiled: April 29, 2014Publication date: August 21, 2014Applicant: NetApp, Inc.Inventor: Atul Goel
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Patent number: 8812817Abstract: A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.Type: GrantFiled: June 28, 2013Date of Patent: August 19, 2014Assignee: Microsoft CorporationInventors: Jeffrey C. Fuller, Thomas J. Ootjers, Bruce L. Worthington
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Patent number: 8812818Abstract: A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.Type: GrantFiled: February 14, 2012Date of Patent: August 19, 2014Assignee: International Business Machines CorporationInventors: Eric Lawrence Barsness, David L. Darrington, Patrick Joseph McCarthy, Amanda Peters, John Matthew Santosuosso
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Patent number: 8812816Abstract: Systems and methods are provided for handling uncorrectable errors that may occur during garbage collection of an index page or block in non-volatile memory.Type: GrantFiled: March 23, 2010Date of Patent: August 19, 2014Assignee: Apple Inc.Inventors: Daniel J. Post, Vadim Khmelnitsky
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Patent number: 8804752Abstract: A method for temporary storage of data units including receiving a first data unit to store in a hardware linked list queue on a communications adapter, reading a first index value from the first data unit, determining that the first index value does match an existing index value of a first linked list, and storing the first data unit in the hardware linked list queue as a member of the first linked list. The method further includes receiving a second data unit, reading a second index value from the second data unit, determining that the second index value does not match any existing index value, allocating space in the hardware linked list queue for a second linked list, and storing the second data unit in the second linked list.Type: GrantFiled: May 31, 2011Date of Patent: August 12, 2014Assignee: Oracle International CorporationInventors: Brian Edward Manula, Magne Vigulf Sandven, Haakon Ording Bugge
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Patent number: 8806171Abstract: Systems and methods for dynamically remapping elements of a set to another set based on random keys. Application of said systems and methods to dynamically mapping regions of memory space of non-volatile memory, e.g., phase-change memory, can provide a wear-leveling technique. The wear leveling technique can be effective under normal execution of typical applications, and in worst-case scenarios including the presence of malicious exploits and/or compromised operating systems, wherein constantly migrating the physical location of data inside the PCM avoids information leakage and increases security; wherein random relocation of data results in the distribution of memory requests across the physical memory space increases durability; and wherein such wear leveling schemes can be implemented to provide fine-grained wear leveling without overly-burdensome hardware overhead e.g., a look-up table.Type: GrantFiled: May 24, 2012Date of Patent: August 12, 2014Assignee: Georgia Tech Research CorporationInventors: Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S Lee
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Patent number: 8806116Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.Type: GrantFiled: February 11, 2009Date of Patent: August 12, 2014Assignee: Virident Systems, Inc.Inventors: Vijay Karamcheti, Kumar Ganapathy
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Patent number: 8806104Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2012Date of Patent: August 12, 2014Assignee: Intel CorporationInventors: Vedvyas Shanbhogue, Stephan J. Robinson
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Patent number: 8799620Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.Type: GrantFiled: June 1, 2007Date of Patent: August 5, 2014Assignee: Intel CorporationInventors: Ohad Falik, Ben-Zion Friedman, Jack Doweck, Eliezer Weissmann, James B. Crossland
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Patent number: 8799618Abstract: Examples are disclosed for allocating a block of persistent storage or accessing a block of persistent storage based on a storage service string that includes a universally unique identifier and associated metadata.Type: GrantFiled: April 12, 2011Date of Patent: August 5, 2014Assignee: Empire Technology Development LLCInventor: Rudi Cilibrasi
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Patent number: 8799553Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.Type: GrantFiled: September 30, 2010Date of Patent: August 5, 2014Assignee: Apple Inc.Inventors: Ian Hendry, Rajabali Koduri, Jeffry Gonion
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Patent number: 8799559Abstract: Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data.Type: GrantFiled: December 20, 2011Date of Patent: August 5, 2014Assignee: Sandisk Technologies Inc.Inventors: Eran Sharon, Idan Alrod
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Patent number: 8798085Abstract: Techniques are described herein that can be used to process inbound network protocol units. In some implementations, the techniques may process inbound DDP segments. In some implementations, a steering tag of an inbound network protocol unit may be used to access a context accessible to a network component. In some implementations, the context may include an array useful to determine whether all segments in a group have been received by the network component. In some implementations, the segments may be stored in a first buffer and transferred to a second buffer after all segments in a group have been received.Type: GrantFiled: June 20, 2006Date of Patent: August 5, 2014Assignee: Intel CorporationInventor: Mark W. Wunderlich
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Patent number: 8793468Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.Type: GrantFiled: April 11, 2013Date of Patent: July 29, 2014Assignee: International Business Machines CorporationInventors: Vincent Tkac, Keith Shafer, Michael R. Ingardia
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Patent number: 8793429Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.Type: GrantFiled: June 3, 2011Date of Patent: July 29, 2014Assignee: Western Digital Technologies, Inc.Inventors: Matthew Call, Lyndon S. Chiu, Robert L. Horn, Lan D. Phan
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Patent number: 8788787Abstract: Systems and methods allow access between a software application residing within a processor module and an accelerator module having an accelerator address space distinct from the processor address space. Access to the accelerator is provided by mapping the accelerator address space to an associated portion of the processor address space. The association may be made based upon a description of the accelerator address space provided in a pre-determined format. The formatted description is processed to create a software indicator module that is provided to the user application to thereby indicate the associated portion of the processor address space. Access to the associated portion of the processor address space by the software program is redirected to the accelerator address space to thereby allow the application to access the accelerator. A functional interface that allows the software application to issue commands and perform other administrative functions on the accelerator module may also be provided.Type: GrantFiled: March 2, 2005Date of Patent: July 22, 2014Assignee: The Boeing CompanyInventors: Michael R. Mott, Evans C. Harrigan, Heidi E. Ziegler, Jamie Douglass
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Patent number: 8788749Abstract: A method and a storage system are provided for implementing deterministic memory allocation for indirection tables for persistent media or disk drives, such as, shingled perpendicular magnetic recording (SMR) indirection tables. A plurality of fixed-size memory pools are used to store indirection data. The distribution of pool allocate sizes is fixed. A pool allocate size is selected based upon an indirection system request size.Type: GrantFiled: August 11, 2011Date of Patent: July 22, 2014Assignee: HGST Netherlands B.V.Inventor: David Robison Hall
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Patent number: 8787101Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.Type: GrantFiled: August 5, 2013Date of Patent: July 22, 2014Assignee: Micron Technology, Inc.Inventors: Brent Keeth, Chris G. Martin, Troy A. Manning, Joe M. Jeddeloh, Timothy B. Cowles, Jim Rehmeyer, Paul A. LaBerge
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Patent number: 8782325Abstract: The present disclosure includes systems and techniques relating to data type based alignment of data written to non-volatile memory. In some implementations, an apparatus includes an input, an output, and control logic coupled with the input and the output, where the control logic is configured to modify placement of data written to a non-volatile memory based on a first data type of the data. The first data type is distinct from a second data type also written to the non-volatile memory, and the placement of the data of the first data type is modified in relation to placement of data of the second data type in the non-volatile memory.Type: GrantFiled: February 4, 2010Date of Patent: July 15, 2014Assignee: Marvell International Ltd.Inventor: Xueshi Yang
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Patent number: 8782344Abstract: A cache layer leverages a logical address space and storage metadata of a storage layer (e.g., storage layer) to cache data of a backing store. The cache layer maintains access metadata to track data characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not in the cache. The access metadata may be separate and distinct from the storage metadata maintained by the storage layer. The cache layer determines whether to admit data into the cache using the access metadata. Data may be admitted into the cache when the data satisfies cache admission criteria, which may include an access threshold and/or a sequentiality metric. Time-ordered history of the access metadata is used to identify important/useful blocks in the logical address space of the backing store that would be beneficial to cache.Type: GrantFiled: January 12, 2012Date of Patent: July 15, 2014Assignee: Fusion-io, Inc.Inventors: Nisha Talagala, Swaminathan Sundararaman, Amar Mudrankit
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Patent number: 8782360Abstract: A method, system and computer-program product for re-initializing a storage volume with an previously created volume map being preserved to allow access to previously stored data sets. The invention includes creating a new volume map in an unused volume area where the new volume map has pointers to new data sets. One of the new data sets contains the previously created volume map that points to previously created data sets. Each volume map is referenced by a volume label and includes a VTOC and an optional VTOC index. The pointers in the VTOC are data set control block (DSCB) records.Type: GrantFiled: May 13, 2010Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: James B. Cammarata, Gavin Stuart Johnson, Michael John Koester
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Publication number: 20140195724Abstract: An apparatus and method of converting an address and data of a memory in a terminal. The apparatus includes a random key generator configured to generate a new random key, each time the terminal is powered on, an address mapper configured to convert an address of a memory area for data writing or reading using the random key and transmit the converted address to a data converter, and the data converter configured to convert data to be written to the memory using the converted address and convert data to read from the memory using the converted address to original data.Type: ApplicationFiled: January 7, 2014Publication date: July 10, 2014Applicant: Samsung Electronics Co., LtdInventor: Hee-Sub Shin
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Patent number: 8775776Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).Type: GrantFiled: January 18, 2012Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Bulent Abali, John J. Reilly
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Patent number: 8775772Abstract: Methods and apparatus for enhanced READ and WRITE operations in a FLASH-based solid state storage system that includes a logical to physical translation table where the logical to physical translation table can include entries associating a logical block address with one or more data identifiers, where each data identifier is associated with a data string.Type: GrantFiled: December 21, 2009Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: James A. Fuxa, Lance W. Shelton, Justin C. Haggard
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Publication number: 20140189283Abstract: Provided is a semiconductor memory device that may efficiently map an internal address used inside the semiconductor memory device in response to an external address that is applied from the outside of the semiconductor memory device. The semiconductor memory device may include a memory cell array configured to include a first main cell array, a first spare cell array, a second main cell array, and a second spare cell array each of which has internal cells that are selected in response to an internal address, and an address mapping unit configured to map external address as the internal address when the external address designates the first main and spare cell arrays, and to operate calculation with a given value and the external address and to map the calculation result value as the internal address when the external address designates the second main and spare cell arrays.Type: ApplicationFiled: March 14, 2013Publication date: July 3, 2014Applicant: SK HYNIX INC.Inventor: Sang-Oh LIM
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Patent number: 8769241Abstract: Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the disk drive are virtualized as a single logical drive having a logical address space, where the logical drive maps logical block addresses to the SSD and to the disk drive. The technique includes determining, based on a file to be written to the logical drive, a target logical address that corresponds to one of the SSD and the disk drive, and writing the file to the logical drive at the target logical address to effect storage on one of the SSD and the disk drive.Type: GrantFiled: November 19, 2010Date of Patent: July 1, 2014Assignee: Marvell World Trade Ltd.Inventors: Hsing-Yi Chiang, Xinhai Kang, Qun Zhao
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Patent number: 8769242Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.Type: GrantFiled: February 14, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Vincent Tkac, Keith Shafer, Michael R. Ingardia
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Patent number: 8769239Abstract: Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first identifier with a modified identifier in the memory request, and transmitting the memory request to the memory through a processor complex. The method further includes receiving a response from the memory, determining that the response corresponds to the memory request, replacing the modified identifier with the first identifier in the response, and transmitting the response to the hardware subsystem. In some embodiments, a system may be implemented as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.Type: GrantFiled: December 17, 2010Date of Patent: July 1, 2014Assignee: Apple Inc.Inventors: Deniz Balkan, Gurjeet S. Saund
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Patent number: 8769240Abstract: An integrated circuit includes a random address generation unit configured to generate a first random address for a data randomizing operation, an address conversion unit configured to convert the first random address and generate a second random address, and a synchronization output unit configured to sequentially output the first and second random addresses in synchronization with a clock signal.Type: GrantFiled: December 21, 2011Date of Patent: July 1, 2014Assignee: Hynix Semiconductor Inc.Inventor: Dae-Il Choi
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Publication number: 20140181456Abstract: A memory controller may include a reception unit configured to receive count information on the number of failed addresses in a memory, an address generation unit configured to generate an address having a value between a minimum address value and a maximum address value, wherein the maximum address value is adjusted based on an original maximum value and the count information, and a transmission unit configured to transmit the generated address to the memory.Type: ApplicationFiled: March 15, 2013Publication date: June 26, 2014Applicant: SK HYNIX INC.Inventor: Ki-Chang KWEAN
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Patent number: 8762683Abstract: An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.Type: GrantFiled: October 15, 2008Date of Patent: June 24, 2014Assignee: MStar Semiconductor, Inc.Inventors: Chih-Min Wang, Chao-Ping Su, Yi-Lung Tsai, Ming-Hong Huang
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Patent number: 8762682Abstract: A data storage apparatus includes a command processor that receives write commands and data blocks from a host, the write commands comprising block ID's (BID) corresponding to data blocks; storage resources including semiconductor memory and mass storage; a data manager that selects storage resources and allocates selected resources to block ID's; a translation table to map a storage resource to the allocated block ID, and storage resources that are selected after receipt of the write command. A method is further provided for increasing performance in a storage device comprising a plurality of storage resources, transferring data to a storage resource that is available to transfer the data.Type: GrantFiled: July 2, 2010Date of Patent: June 24, 2014Assignee: Western Digital Technologies, Inc.Inventor: Curtis E. Stevens
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Patent number: RE45097Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.Type: GrantFiled: February 2, 2012Date of Patent: August 26, 2014Assignee: Cisco Technology, Inc.Inventors: Sundar Iyer, Nick McKeown