Abstract: Method and apparatus for mutably associating logical block addresses to physical blocks. A physical storage space is apportioned into one or more bands. A logical block address (LBA) from a logical space is assigned to one of the bands, and the LBA is mutably associated with a particular physical block (sector) at an associated physical block address (PBA) within the assigned band. Such mutable association preferably includes the writing of user data associated with the LBA to the associated physical sector. During a subsequent operation, user data associated with the LBA can be stored in a second physical sector in the assigned band. The physical storage space preferably comprises a magnetic recording medium, and some or all of the bands preferably utilize overlapping tracks. The logical space is preferably divided into sets of sequential LBAs, with non-adjacent sets assigned to the same band. Map data are used to track sector allocation status in each band.

Abstract: Systems, methods, and other embodiments associated with managing memory are described. According to one embodiment, an apparatus includes a converter that dynamically converts a structure of a data representation stored in a memory, where the structure is selectively converted between a sparse format and a non-sparse format.

Abstract: Methods and apparatuses for optimizing the performance of a storage system comprise a FLASH storage system, a hard drive storage system, and a storage controller. The storage controller is adapted to receive READ and WRITE requests from an external host, and is coupled to the FLASH storage system and the hard drive storage system. The storage controller receives a WRITE request from an external host containing data and an address, forwards the received WRITE request to the FLASH storage system and associates the address provided in the WRITE request with a selected alternative address, and provides an alternative WRITE request, including the selected alternative address and the data received in the WRITE request, to the hard drive storage system, wherein the alternative address is selected to promote sequential WRITE operations within the hard drive storage system.

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract: Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

Abstract: Apparatuses, systems, and methods are disclosed for caching data. A method includes directly mapping a logical address of a backing store to a logical address of a non-volatile cache. A method includes mapping, in a logical-to-physical mapping structure, the logical address of the non-volatile cache to a physical location in the non-volatile cache. The physical location may store data associated with the logical address of the backing store. A method includes removing the mapping from the logical-to-physical mapping structure in response to evicting the data from the non-volatile cache so that membership in the logical-to-physical mapping structure denotes storage in the non-volatile cache.

Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of a partition control area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.

Abstract: Systems and methods for providing additional instructions for supporting efficient memory corruption detection in a processor. A physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Version numbers associated with data structures allocated in the memory may be generated so that version numbers of adjacent data structures are different. A processor determines that a fetched instruction is a memory access instruction corresponding to a first data structure within the memory. For instructions that are not a version update instruction, the processor compares the first version number and second version number stored in a location in the memory indicated by the generated address and flags an error if there is a mismatch. For version update instructions, the processor performs a memory access operation on the second version number with no comparison check.

Abstract: A semiconductor recording apparatus includes a logical-to-physical conversion table 115 showing correspondence between a physical address of said semiconductor memory and a logical address and writes the table to a flash memory 120. On receiving a write command issued from a host device 200, a block management section 114 selects a physical block with reference to said logical-to-physical conversion table, and updates said logical-to-physical conversion table. A logical-to-physical conversion table initializing section 117 updates a physical address corresponding to each logical address of the logical-to-physical conversion table into an invalid address. Accordingly the apparatus can render the number of rewrites of physical blocks uniform irrespective of writing conditions.

Abstract: Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.

Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Abstract: A storage device includes a memory and a processor. The processor is configured to store data items for a host in respective logical addresses, to identify a first subset of the logical addresses as frequently-accessed logical addresses and a second subset of the logical addresses as rarely-accessed logical addresses, to manage the frequently-accessed logical addresses separately from the rarely-accessed logical addresses, to receive from the host an indication of one or more logical addresses, which are used for storing data that is identified by the host as having been deleted by a user, and to add the logical addresses indicated by the host to the rarely-accessed logical addresses.

Abstract: A method comprising: obtaining a value of source data; encoding the value of source data using an encoding process, to thereby obtain an encoded value; calculating a difference value based on the value of source data and the encoded value; mapping the difference value to a multi-digit binary value associated with a voltage level based on a mapping scheme; causing a cell of a multi-level cell memory to store the mapped multi-digit binary value; and causing the encoded value of source data to be stored in the multi-level cell memory.

Abstract: A detection module selects logically adjacent first and second control areas of a cluster. The detection module further determines that the first and second control areas satisfy a migration test wherein the first control area has free space exceeding a free threshold, the free space is at least equal to a space requirement for each second control area control interval, and the second control area has fewer control intervals than a control interval threshold. In addition, a copy module copies each second control area control interval to the first control area in response to determining that the first and second control areas satisfy the migration test.

Abstract: A method and system is provided for initializing files such as, for example and without limitation, pre-allocated files or raw device mapping (RDM) files, by delaying initializing file blocks. In accordance with one or more embodiments of the present invention, file blocks are associated with corresponding indicators to track un-initialized blocks.

Abstract: In accordance with the present disclosure, a system and method for controller independent faulty memory replacement is described. The system includes a system memory component with a system memory component architecture. The system also includes a memory buffer coupled to the system memory component. The memory buffer may include at least one spare memory location corresponding to a faulty memory location of the system memory component. Additionally, the system memory component architecture may receive a read command directed to an address of the system memory component containing the faulty memory location and output, in response to the read command, data corresponding to the address from both the system memory component and the at least one spare memory component.

Abstract: A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

Abstract: A method for improving replication persistence in a caching appliance structure can begin when a primary catalog service receives a command to instantiate a data partition. The primary catalog service can manage a collective of caching appliances in a networked computing environment. The data partition can include a primary shard and at least one replica shard. The primary shard of the data partition can be stored within a memory space of a first caching appliance. The at least one replica shard of the data partition can be stored within a non-volatile storage space of a second caching appliance. The first and the second caching appliances can be separate physical devices. The memory space of the second caching appliance that could have been used to store the at least one replica shard can be available for storing primary shards for other data partitions, increasing the capacity of the collective.

Abstract: The present disclosure describes various techniques resolving block boundary issues and reconstructing logical blocks in a block access storage device when there are resulting mismatches between logical and physical block sizes or alignments, such that logical blocks span multiple physical block boundaries in irregular ways. In one example, a method comprises the following features: receiving logical block addresses that are associated with a sequence of logical blocks; and locating a first portion of a logical block within a first physical block that is stored in a block access storage device based upon a logical block address of the logical block, wherein the logical block is part of the sequence of logical blocks, and wherein at least two logical blocks within the sequence of logical blocks have different sizes.

Abstract: A method for improving replication persistence in a caching appliance structure can begin when a primary catalog service receives a command to instantiate a data partition. The primary catalog service can manage a collective of caching appliances in a networked computing environment. The data partition can include a primary shard and at least one replica shard. The primary shard of the data partition can be stored within a memory space of a first caching appliance. The at least one replica shard of the data partition can be stored within a non-volatile storage space of a second caching appliance. The first and the second caching appliances can be separate physical devices. The memory space of the second caching appliance that could have been used to store the at least one replica shard can be available for storing primary shards for other data partitions, increasing the capacity of the collective.

Abstract: An apparatus for processing data 2 includes a memory 4 having a plurality of memory regions 28 to 38. A mapping controller 56 applies a variable mapping to map memory addresses of access requests to different regions within the memory 4. The mapping controller varies the mapping applied in dependence upon both one or more memory behavioral parameters indicative of behavioral characteristics of the different regions and one or more access behavioral parameters indicative of behavioral characteristics of an access request to be mapped. The memory behavioral parameters may include the temperature of the regions and/or the refresh period of the regions. The access behavior able parameters may include the quality of service level, the access frequency, the access volume and/or the identity of the source of the access request.

Abstract: A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.

Abstract: Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk.

Abstract: Machines, systems and methods for deploying one or more virtual machines on a host computing system, the method comprising: receiving mapping information from a data storage system, wherein the mapping information associates a first data chunk stored in the data storage system with a unique identifier; utilizing the mapping information to determine whether any copies of the first data chunk have already been loaded into a memory of the host computing system in association with deployment of a first virtual machine or a second virtual machine on the host computing system; and in response to determining that no copies of the first data chunk have already been loaded into the memory: retrieving the first data chunk from the data storage system; loading the first data chunk into the memory; and utilizing the first data chunk to deploy the first virtual machine on the host computing system.

Abstract: The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands.

Abstract: A method is described for preserving the flexibility associated with relative memory addressing in programs designed to be stored in read-only memory.

Abstract: A solution is provided to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices, while satisfying the capacity requirements for the flash memory devices in a system design, wherein a decoding unit is used for determining which flash memory devices will be accessed and re-mapping incoming serial addressing bits, for accessing one flash memory device, into an outgoing serial addressing bits for accessing another flash memory device.

Abstract: Methods and apparatus are disclosed for managing access to data in a data storage system. For example, an apparatus comprises at least one processing platform associated with a distributed virtual infrastructure. The processing platform comprises at least one processing device having a processor coupled to a memory. The processing platform is operative to instantiate a meta data management process that is configured to provide at least one client process with information to allow the client process to perform one or more operations in accordance with one or more data storage devices through a storage area network. The information provided to the client process may comprise one or more data block descriptors. Each of the one or more data block descriptors may comprise path information for at least one of the data storage devices and an offset address in the at least one data storage device.

Abstract: A system including a write module, a read module, and a signal processing module. The write module is configured to write pilot data, having a first predetermined pattern, in a page of memory cells. The pilot data are interspersed with user data stored in the page. The read module is configured to read the pilot data and to generate pilot signals based on reading the pilot data. The signal processing module is configured to compare the pilot signals and the pilot data, and to estimate, based on a comparison of the pilot signals and the pilot data, a disturbance to the user data.

Abstract: A sticky drive includes a flash storage device and a mounting structure having a stickable surface. The mounting structure is coupled to the flash storage device to enable a user to attach the flash storage device to a user-selected object.

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract: A method begins by a processing module receiving redundant array of independent disks (RAID) data and determining whether to store the RAID data in at least one of a RAID format and in a dispersed storage network (DSN) format. The method continues with the processing module converting at least a portion of the RAID data into at least one set of encoded data slices when the at least a portion of the RAID data is to be stored in the DSN format. The method continues with the processing module outputting the at least one set of encoded data slices to a DSN memory.

Abstract: In computing environments that use virtual addresses (or other indirectly usable addresses) to access memory, the virtual addresses are translated to absolute addresses (or other directly usable addresses) prior to accessing memory. To facilitate memory access, however, address translation is omitted in certain circumstances, including when the data to be accessed is within the same unit of memory as the instruction accessing the data. In this case, the absolute address of the data is derived from the absolute address of the instruction, thus avoiding address translation for the data. Further, in some circumstances, access checking for the data is also omitted.

Abstract: A method and apparatus for storing data packets in two different logical erase blocks pursuant to an atomic storage request is disclosed. Each data packet stored in response to the atomic storage request comprises persistent metadata indicating that the data packet pertains to an atomic storage request. In addition, a method and apparatus for restart recovery is disclosed. A data packet preceding an append point is identified as satisfying a failed atomic write criteria, indicating that the data packet pertains to a failed atomic storage request. One or more data packets associated with the failed atomic storage request are identified and excluded from an index of a non-volatile storage media.

Abstract: A command analyzer 160 determines whether or not a first write command after power-on is issued. A new block reserve determinator 170 determines that a new physical block is reserved, in a case where the command analyzer 160 determines that first writing command after power-on is issued and the physical block corresponding to a logical address at which a host device requests transmit is in a written state. At this time, the semiconductor memory device writes data to the new physical block. Thereby, data written before power disconnection does not been destroyed.

Abstract: According to one embodiment, a method for a compiler to produce an executable module to be executed by a computer system including a main processor and active memory devices includes dividing source code into code sections, identifying a first code section to be executed by the active memory devices, wherein the first code section is one of the code sections and identifying data structures that are used by the first code section. The method also includes classifying the data structures based on pre-defined attributes, formulating, by the compiler, a storage mapping plan for the data structures based on the classifying and generating, by the compiler, mapping code that implements the storage mapping plan, wherein the mapping code is part of the executable module and wherein the mapping code maps storing of the data structures to storage locations in the active memory devices.

Abstract: Apparatus, systems, and methods may operate to provide, to a memory device, an obfuscated clear-page address derived from a clear-page address that is not the same as a key-page address and/or providing, to the memory device, an obfuscated key-page address derived from the key-page address when the obfuscated clear-page address is the same as the key-page address. Additional apparatus, systems, and methods are disclosed.

Abstract: A storage device made up of multiple storage media is configured such that a flash memory serves as a cache for data stored on a backend storage device having one or more magnetic storage media. The storage device includes a controller configured to maintain a direct mapping from respective backend block addresses of the backend storage device to respective physical addresses of the flash memory. Such mapping is used to translate a backend block address of the backend storage device at which a first block is stored into a physical address of the flash memory at which the first block is cached.

Abstract: A method and a storage system are provided for implementing indirection tables for persistent media or disk drives with enhanced emergency power outage (EPO) protection for the indirection data, such as shingled perpendicular magnetic recording (SMR) indirection tables. Chaining of indirection data is provided with one block pointing to another block of the indirection data stored to disk or flash memory. An EPO-safe buffer is used to store a metadata entry responsive to completing each host write command. Each metadata entry is added to a metadata block, a pointer is stored in the EPO-safe buffer to a current metadata block and a previous metadata block. For a next EPO-safe buffer update entries are removed for the previous metadata block, keeping the last two metadata pointers and last metadata block.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.

Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit (196) is used to detect memory accesses; to check page protection information relevant to the detected access by examining the contents of a page descriptor store; and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.

Abstract: A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a “miss” in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained.

Abstract: A system, method, and computer-readable storage medium for mapping block numbers within a region to physical locations within a storage system. Block numbers are mapped within a region according to a fractal-based space-filling curve. If the region is not a 2k by 2k square, then the region is broken up into one or more 2k by 2k squares. Any remaining sub-region is centered within a 2k by 2k square, the 2k by 2k square is numbered using a fractal-based space-filling curve, and then the sub-region is renumbered by assigning numbers based on the order of the original block numbers of the sub-region.

Abstract: A method includes receiving an address at a tag state array of a cache. The cache is configurable to have a first size or a second size that is larger than the first size. The method includes identifying a first portion of the address as a set index and using the set index to locate at least one tag field of the tag state array. The method also includes identifying a second portion of the address to compare to a value stored at the at least one tag field and locating at least one state field of the tag state array associated with a particular tag field that matches the second portion. The method further includes identifying a cache line based on a comparison of a third portion of the address to at least two status bits of the at least one state field and retrieving the cache line.

Abstract: Memory address translations are disclosed. An example memory controller includes an address translator to translate an intermediate memory address into a hardware memory address based on a function, the address translator to select the function based on at least a portion of the intermediate memory address, the intermediate memory address being identified by a processor. The example memory controller includes a cache to store the function in association with an address range of the intermediate memory sector, the intermediate memory address being within the intermediate memory sector. Further, the example memory controller includes a memory accesser to access a memory module at the hardware memory address.

Abstract: A method is provided in one example embodiment and includes communicating location and access network information for an end user to a policy and charging rules function (PCRF) element that is coupled to a network element. The network element receives packets for a communications flow from the end user if the flow is initiated through a wireless network and through a wireline network. In more specific embodiments, the location and access network information is used to initiate one or more applications for the end user. The method could also include communicating to an application function that the end user has attached to one of the networks, has been assigned an Internet Protocol (IP) address, and the location and access network information for the end user.

Abstract: Techniques are described for efficient reordering of data and performing data exchanges within a register file or memory, or in general, any device storing data that is accessible through a set of addressable locations. An address translator is placed in the path of all or a selected set of address busses to a storage device to provide a programmable and selectable means of translating the storage device addresses. An effect of this translation is that the data stored in one pattern may be accessed and stored in another pattern or accessed, processed and stored in another pattern. The address translation operation may be carried out in a single cycle, does not involve the physical movement of data in swap operations, allows data to effectively be ordered more efficiently for algorithmic processing and therefore saves power.

Abstract: A method and system for interfacing a system operating through a logical address space with a direct file storage (DFS) medium is disclosed. The method includes receiving data associated with addresses in a logical block address (LBA) format from a host system and generating file objects manageable by the DFS medium based on a determination of the correlation of the LBA data to host file data. The memory system includes non-volatile memory using the DFS format, an interface for receiving LBA format data, and a controller configured to communicate with the host via an LBA interface and generate file objects from the LBA format data correlated to the host application files usable by the memory system.

Abstract: A method of storing data in a storage medium of a data storage device comprises storing input data in the storage medium, and reading the input data from the storage medium and compressing the read data during a background operation of the data storage device.

Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.