Abstract: A method, apparatus, and system of presentation of a read-only clone Logical Unit Number (LUN) to a host device as a snapshot of a parent LUN are disclosed. In one embodiment, a method includes generating a read-write clone LUN of a parent LUN and coalescing an identical data instance of the read-write clone LUN and the parent LUN in a data block of a volume of a storage system. A block transfer protocol layer is modified to refer the read-write clone LUN as a read-only clone LUN, according to the embodiment. Furthermore, according to the embodiment, the read-only clone LUN is presented to a host device as a snapshot of the parent LUN.

Abstract: A backup apparatus has an address conversion table for storing, in correspondence with each other, a logical address and a physical address. The backup apparatus has a sequential data count setting unit, a sequential data information acquisition unit, and a reading unit. The sequential data count setting unit sets sequential data count information indicating the number of data blocks in a sequence in the physical address in the address conversion table. The sequential data information acquisition unit, upon receiving a read request, reads the data block in the address conversion table corresponding to the leading logical address among the logical addresses requested to be read and acquires the sequential data count information set in the address conversion table. The reading unit reads a physical volume corresponding to physical addresses in a sequence in accordance with the sequential data count information acquired by the sequential data information acquisition unit.

Abstract: Systems and methods are provided for dynamically allocating a number of bits per cell to memory locations of a non-volatile memory (“NVM”) device. In some embodiments, a host may determine whether to store data in the NVM device using SLC programming or MLC programming operations. The host may allocate an erased block as an SLC block or MLC block based on this determination regardless of whether the erased block was previously used as an SLC block, MLC block, or both. In some embodiments, to dynamically allocate a memory location as SLC or MLC, the host may provide an address vector to the NVM package, where the address vector may specify the memory location and the number of bits per cell to use for that memory location.

Abstract: A network element that includes multiple memory types and memory sizes translates a logical memory address into a physical memory address. A memory access request is received for a data structure with a logical memory address that includes a region identifier that identifies a region that is mapped to one or more memories and is associated with a set of one or more region attributes whose values are based on processing requirements provided by a software programmer and the available memories of the network element. The network element accesses the region mapping table entry corresponding to the region identifier and, using the region attributes that are associated with the region, determines an access target for the request, determines a physical memory address offset within the access target, and generates a physical memory address. The access target includes a target class of memory, an instance within the class of memory, and a particular physical address space of the instance within the class of memory.

Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Abstract: Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object.

Abstract: Exemplary embodiments of the invention provide a solution to deploy a virtual hard disk (VHD) to virtual device with maximizing capacity efficiency and data access performance by making the allocation unit size of virtual device the same as that of the VHD. In one embodiment, a method of deploying a VHD file to a storage apparatus comprises checking a block size of the VHD file received by the storage apparatus based on a header of the VHD file; creating a virtual volume to provide a page size which is same size as the block size of the VHD file; and performing one of (A) copying contents of the VHD file to the created virtual volume by allocating one page of the created virtual volume for each block of the VHD file; or (B) formatting the created virtual volume with a virtual volume file system, and copying the VHD file to the formatted virtual volume.

Abstract: In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used.

Abstract: User data transferred from a host apparatus and a first information table 35 indicating correspondence between a logical address and a physical address are recorded in a first region of a flash memory 20. A second information table 38 composed of the physical block address storing the first information table 35 and the number of times of update of the physical block for recording the first information table from the time of manufacturing is recorded in a second region of the flash memory 20. The physical blocks of the first and the second regions are recorded independently from each other in a rotational manner. According to the recording of the second information table, the total number of times of rewriting of the first region is converted. This can suppress the number of times of rewriting of the second region and improve reliability of the number of times of update of the first information table from the time of manufacturing, the number being recorded in the second region.

Abstract: A device may receive a request to read data from or write data to a memory that includes a number of memory banks. The request may include an address. The device may perform a mapping operation on the address to map the address from a first address space to a second address space, identify one of the memory banks based on the address in the second address space, and send the request to the identified memory bank.

Abstract: A method includes selectively routing a physical address to an originating device instead of to a shared memory at controller that manages conversion of device virtual addresses to physical addresses. The physical address corresponds to a data access from a virtual device. The method may provide local coherency at a computing system that implements virtualized input/output.

Abstract: Disclosed are a semiconductor memory system and a method for controlling same. The semiconductor memory system according to one embodiment of the present invention includes: a first memory for storing normal data and master metadata, the master metadata representing a relationship between a local address and a physical address for accessing the normal data; and a control logic generating compression metadata compressed in accordance with update metadata and storing the generated metadata in the first memory in response to a first control signal.

Abstract: The present invention provides a method apparatus for recognizing a process in a guest operation system by a virtual machine monitor, and the method comprises: step 101 of recording by the virtual machine monitor the page table information of a process to be executed upon process switching of the guest operating system; step 102 of acquiring by the virtual machine monitor the identification information of the currently-executed process; step 103 of storing by the virtual machine monitor the correspondence between the previously recorded page table information of the process to be executed and the identification information of the currently-executed process.

Abstract: In one embodiment, a data storage device comprises a buffer, a buffer manager, and a buffer client. The buffer client is configured to receive data to be stored in the buffer, to compute a difference between a bank boundary address of the buffer and a starting buffer address for the data, to generate a first data burst having a length equal to the computed difference and including a first portion of the data, and to send the first data burst to the buffer manager, wherein the buffer manager is configured to write the first data burst to the buffer.

Abstract: A network device that includes a first memory to store packets in segments; a second memory to store pointers associated with the first memory; a third memory to store summary bits and allocation bits, where the allocation bits correspond to the segments. The network device also includes a processor to receive a request for memory resources; determine whether a pointer is stored in the second memory, where the pointer corresponds to a segment that is available to store a packet; and send the pointer when the pointer is stored in the second memory. The processor is further to perform a search to identify other pointers when the pointer is not stored in the second memory, where performing the search includes identifying a set of allocation bits, based on an unallocated summary bit, that corresponds to the other pointers; identify another pointer, of the other pointers, based on an unallocated allocation bit of the set of allocation bits; and send the other pointer in response to the request.

Abstract: A solid state storage system includes a flash memory area and a memory controller. The flash memory area includes memory blocks and replacement blocks configured to replace bad blocks occurring within the memory blocks. The memory controller is configured to perform a logical-to-physical address mapping on logical blocks including the replacement blocks, and select the replacement blocks using logical addresses of the logical blocks corresponding to the bad blocks.

Abstract: The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. Logical storage volumes are created from a logical storage container having an address space that maps to storage locations of the physical data storage units. Each of the logical storage volumes so created has an address space that maps to the address space of the logical storage container. A logical storage container may span more than one storage system and logical storage volumes of different customers can be provisioned from the same logical storage container with appropriate security settings.

Abstract: A semiconductor storage device having an improved write performance is disclosed. The semiconductor storage device includes a plurality of memory devices, with each memory device associated with a logical address space comprising contiguous logical addresses. A controller of the semiconductor storage device is configured to allocate a plurality of meta data groups for each memory device, with each meta data group assigned a set of logical addresses of the logical address space. The controller may also configured to assign a first logical address of a logical address space to a first meta data group and a second logical address of the logical address space, contiguous to the first logical address, to a second meta data group, where the second meta data group is different than the first meta data group.

Abstract: In one embodiment, a memory control system is provided with a memory controller having 1) a first interface to receive memory read/write requests; 2) a second interface to read/write data from a number of memory modules; 3) a memory cache containing spare memory locations; and 4) logic to, upon receipt of a memory read/write request, i) direct the read/write request to the memory cache when an address associated with the read/write request resides in the memory cache, and ii) direct the read/write request to the second interface when the address associated with the read/write request does not reside in the memory cache.

Abstract: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic.

Abstract: An electronic apparatus and a booting method of the same are provided. The booting method of the electronic apparatus, including a non-volatile first storage unit storing a device initialization file and a device execution file, and a volatile second storage unit, includes: loading the device execution file from the first storage unit into the second storage unit at an initial booting; generating reference information about the loaded device execution file; maintaining power supplied to the second storage unit when the electronic apparatus is turned off; loading and executing the device initialization file from the first storage unit into the second storage unit at a rebooting; and executing the device execution file stored in the second storage unit with reference to the reference information.

Abstract: A recording and/or reproducing method, a recording and/or reproducing apparatus, and an information storage medium are provided. The method of recording data to an information storage medium includes: according to a change in a method of using the information storage medium, rearranging the order of a first information structure with a variable size and a second information structure with a fixed size, both of which are included in management information of the information storage medium, so that the first information structure with the variable size can be positioned following the second information structure with the fixed size; and recording the rearranged management information on the information storage medium. According to the method and apparatus, recording management information can be found in a fixed location of a finalized information storage medium, thereby allowing the recording management information to be found easily and quickly.

Abstract: A method for migrating data to a mass storage system, including receiving an incoming data partition for storage in the mass storage system and allocating logical storage for the incoming data partition in the mass storage system. The method further includes making a determination that the incoming data partition includes only zero data, and, in response to the determination, inhibiting physical storage of the incoming data partition in the mass storage system while maintaining the allocated logical storage for the incoming data partition.

Abstract: A tile-map caching technique in which it is determined whether a tile object is stored in a first cache that is configured to store a plurality of tile objects associated with a map. It is also determined whether a resource locator associated with the tile object is stored in a second cache, if the tile object is not in the first cache. The tile object is retrieved based on the resource locator if the resource locator is stored in the second cache.

Abstract: One embodiment of the present invention sets forth an interface circuit configured to combine time staggered data bursts returned by multiple memory devices into a larger contiguous data burst. As a result, an accurate timing reference for data transmission that retains the use of data (DQ) and data strobe (DQS) signals in an infrastructure-compatible system while eliminating the cost of the idle cycles required for data bus turnarounds to switch from reading from one memory device to reading from another memory device, or from writing to one memory device to writing to another memory device may be obtained, thereby increasing memory system bandwidth relative to the prior art approaches.

Abstract: Various embodiments of a system and method for updating backup configuration information used by backup software to perform backup operations for a storage cluster are described. Backup configuration information specifying a configuration of the storage cluster may be stored. Subsequently, a particular change to the configuration of the storage cluster may be automatically detected. In response to detecting the particular change, the backup configuration information may be automatically updated to reflect the particular change to the configuration of the storage cluster. Subsequent backup operations may then be performed using the updated backup configuration information.

Abstract: Method and system for uniquely identifying a replicated copy of a storage volume is provided. A unique identifier is created by a storage system managing the replicated copy. The unique identifier includes a time stamp of when the identifier is being created, a system clock of the storage system and a unique address for an adapter that is used by the storage system.

Abstract: A system, method and program product for tracking an I/O mapping-path among a plurality of nodes in a storage configuration. A system is disclosed that includes: a path tracking manager implemented at a host system that enables I/O mapping-path tracking for an I/O request being serviced within the storage configuration; and a path tagging system implemented at each of a plurality of virtual storage nodes within the storage configuration, wherein each path tagging system appends mapping-path information to the I/O request in response to receiving and processing the I/O request.

Abstract: Provided is a data storage device including two or more data storage areas including may have two or more (heterogeneous) types of nonvolatile memory cells. At least one of the data storage areas includes a plurality of memory blocks that are sequentially selected, and metadata are stored in the currently selected memory block. The memory blocks can be sequentially used and metadata can be stored in a uniformly-distributed manner throughout the data storage device. Therefore, separate merging and wear-leveling operations are unnecessary. Thus, it is possible to improve the lifetime and writing performance of a data storage device having two or more heterogeneous nonvolatile memories.

Abstract: The invention provides a method for data recovery. In one embodiment, a memory comprises a plurality of pages for data storage. First, first data is obtained from a host. A first page for storing the first data is then selected from the pages of the memory. A start page link indicating the first page is then stored in the memory. The first data, a first page link indicating a next page, and first FTL fragment data corresponding to the first page are then written into the first page. Next data is then obtained from the host. The next data, a next page link indicating a subsequent page, and FTL fragment data corresponding to the next page are written into the next page.

Abstract: A system and method provides for enabling a storage virtualization system to dynamically discover shares on a network attached storage file system is disclosed. Certain network attached storage systems represent user shares using abbreviated symbolic path names rather than full absolute path names. These network attached storage systems can correctly map the abbreviated path address to the actual file location; however, when a storage virtualization system is implemented to manage shares or files in these shares, it cannot access these files because it does not have the absolute path address. An embodiment of the present invention provides software instructions to augment the capabilities of the storage virtualization system, enabling it to map files with abbreviated share names, and therefore provide it with the ability to access these types of network attached storage systems.

Abstract: A device, method and system is directed to fast data storage on a block storage device. New data is written to an empty write block. A location of the new data is tracked. Meta data associated with the new data is written. A lookup table may be updated based in part on the meta data. The new data may be read based the lookup table configured to map a logical address to a physical address.

Abstract: A packet inspection device and method for use with a packet-retrievable network apparatus are provided. The packet inspection method includes: converting header information of a packet received into a hashing function value in presence of handshaking underway at the Transmission Control Protocol (TCP) layer and comparing the hashing function value by a hashing function unit of the pending processing module, storing the hashing function value in a memory unit, and performing packet state comparison and packet screening and then creating by the session processing module a transmission connection according to the packet screened and selected by the pending processing module upon determination that data stored in the memory unit match the hashing function value resulting from conversion by the hashing function unit, thereby expediting packet inspection, reducing occupied memory space, and cutting costs.

Abstract: A data object is stored in a hosted storage system and includes an access control list specifying access permissions for data object stored in the hosted storage system. The hosted storage system provides hosted storage to a plurality of clients that are coupled to the hosted storage system. A request to store a second data object is received. The request includes an indicator that the first data object stored in the hosted storage system should be used as an access control list for the second data object. The second data object is stored in the hosted storage system. The first data object is assigned as an access control list for the second data object stored in the hosted storage system.

Abstract: A memory system in which a first management unit includes an update information managing unit that manages update information indicating an updated section in status information stored in a volatile first storing unit, and an update information notifying unit that notifies a second management unit of the update information managed by the update information managing unit, and the second management unit includes a commit executing unit that collects, based on the update information, difference information of the status information from the status area when the update information is notified from the update information notifying unit, and causes a second storing unit to accumulate the difference information in a backup area.

Abstract: Disclosed is a method for accessing a non-volatile memory device using a flash translation layer. The method includes receiving a write request for data from a file system and recording the data in the non-volatile memory device in response to the write request. The flash translation layer is informed whether a confirm mark for the data is recorded or not from the file system.

Abstract: The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.

Abstract: A method for memory space management is disclosed. It uses a resident program loaded into an operation system or the controller of a storage device to monitor the storage space and the resource allocation of the file system of the storage device. The status of the logical address with an erased and invalid data mapped with a physical block is checked via a L2P mapping table. By using a data erase instruction, the controller modifies the L2P mapping table to cancel the link relation between the physical block and the logical address and erase the physical block to release the memory space. Finally, the check location is stored for a next check. The method for memory space management improves the access speed and the usage life of the storage device.

Abstract: A semiconductor storage system includes a memory controller that classifies a memory block of a memory area into a data block and a buffer block. The buffer block corresponds to the data block. The memory controller compares the number of free pages of both the data block and the buffer block with the number of valid pages of the data block and the buffer block during mergence in order to select the merged target block. Depending on the result of the comparison, either the data block or the buffer block is selected as the merged target block.

Abstract: instructions to: (1) process first data by encrypting based on a first key and re-arranging based on a first mapping to obtain second data, where a first element included in the first data is associated with a first index corresponding to a location in a first memory; (2) request to store the second data in a second memory at locations determined based on the first mapping; (3) in response to determining that the first element is not stored in the first memory, request a second element from the second memory; and (4) in response to determining that the first element is stored in the first memory: (a) retrieve the first element from the first memory; and (b) request a third element from the second memory that has not been previously requested, without requesting the second element from the second memory.

Abstract: Memory systems and mapping methods thereof are provided. In one embodiment of a memory system, an interface device is coupled between a flash memory and a host and stores a flash translation layer. The flash translation layer utilizes a data block mapping table and a page mapping table to manage data blocks and log blocks of the flash memory by a page mapping scheme and utilizes a random write page mapping table independent from the block mapping table and the page mapping table to manage the random write blocks by a random write mapping scheme. When a first predetermined condition is satisfied, the flash translation layer converts one of the data blocks (and one of the log block corresponding to the converted data block if any) into random write block(s) and utilizes the random write mapping schemes to manage the random write block(s).

Abstract: Provided are a flash memory device and a reading method of the flash memory device. A multi-level cell flash memory device includes: a memory cell array comprising main memory cells storing main data, and indicator cells storing indicate data indicating one of a first mode and a second mode in which the main data of the main memory cell, to which the indicate cells correspond, is written; and an output unit outputting in response to a control signal corresponding to the indicate data, one of main data read from the memory cell array and forced data forcing some bit values of the main data to bit values of mode specific data, as reading data.

Abstract: An apparatus includes a first Universal Serial Bus (USB) connector and a card holder associated with the first USB connector. A controller including a USB host interface is coupled to the first USB connector. A housing enclosing the controller and at least partially enclosing the card holder has an opening that is dimensioned to enable insertion of a memory card into the card holder. The first USB connector is configured to connect to a second USB connector of the memory card when the memory card is inserted into the card holder.

Abstract: A coprocessor performs operations on behalf of processes executing in processors coupled thereto, and accesses data operands in memory using real addresses. A process executing in a processor generates an effective address for a coprocessor request, invokes the processor's address translation mechanisms to generate a corresponding real address, and passes this real address is the coprocessor. Preferably, the real address references a block of additional real addresses, each for a respective data operand. The coprocessor uses the real address to access the data operands to perform the operation. An address context detection mechanism detects the occurrence of certain events which could alter the context of real addresses used by the coprocessor or the real addresses themselves.

Abstract: A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to the data memory. A connection identifier (ID), received in association with the access request; may include a buffer ID designating a buffer in the data memory in which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into the real address of the data memory, and accessing the data memory at a location corresponding to the real address. Different types of buffers, such as point-to-point, scatter, and gather buffers may be used, and different patterns, such as first-in-first out (FIFO), nested loop, matrix transforms may be used.

Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes selectively overriding attributes contained in a translation lookaside buffer or page table data structure with attributes contained in a context specifier.

Abstract: Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method includes managing commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and mapping portions of a second memory having the attribute enhanced set through a second interface controller. Additional apparatuses and methods are described.

Abstract: A method for data transmission in a system is disclosed. The system includes a computer (1) and a peripheral device (9), which are connected to each other via a network (8). The computer has hardware resources (2), including a network interface (2.3) and a controller (4), which is designed to provide a virtual machine system in that it maps the hardware resources (2), including the network interface (2.3) onto logical interfaces (5, 5.3) in virtual machines (4). A peripheral device adapter (10) provided in the computer (1) is mapped by the controller (3) onto a logical peripheral device interface (11) in one of the virtual machines (4) and data is exchanged between the peripheral device (9) and the virtual machine (4) via the network (8), the peripheral device adapter (10), and the logical peripheral device interface (11) while bypassing the logical interfaces (5.3) mapping the network interface (2.3) into the virtual machines (4).

Abstract: Adaptive write leveling in limited lifetime memory devices including performing a method for monitoring a write data stream that includes write line addresses. A property of the write data stream is detected and a write leveling process is adapted in response to the detected property. The write leveling process is applied to the write data stream to generate physical addresses from the write line addresses.

Abstract: A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.