Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
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Patent number: 9374292Abstract: Embodiments of a system and method for providing frequency assignment with managed transceiver resources. A frequency assignment protocol manages transceiver resources in making channel assignment decisions based on a number of links and state of transceivers. Long-term traffic patterns are captured and transceiver resource decisions are made based on an analysis of the captured long-term traffic patterns to increase a selected metric, such as connectivity, capacity or any other measurable quantity.Type: GrantFiled: March 14, 2013Date of Patent: June 21, 2016Assignee: Raytheon BBN Technologies Corp.Inventors: William Nii Tetteh, Christophe Jean-Claude Merlin
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Patent number: 9361474Abstract: Resource acquisition requests for a filesystem are executed under user configurable metering. Initially, a system administrator sets a ratio of N:M for executing N read requests for M write requests. As resource acquisition requests are received by a filesystem server, the resource acquisition requests are sorted into queues, e.g., where read and write requests have at least one queue for each type, plus a separate queue for metadata requests as they are executed ahead of any waiting read or write request. The filesystem server controls execution of the filesystem resource acquisition requests to maintain the ratio set by the system administrator.Type: GrantFiled: December 26, 2013Date of Patent: June 7, 2016Assignee: SILICON GRAPHICS INTERNATIONAL CORP.Inventors: David Chinner, Michael Anthony Gigante
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Patent number: 9354900Abstract: A device (110) and method (700) for providing windows in a multi-environment operating system is provided. A first operating system environment (first OSE) (222) is executed in a native mode on a mobile device (110). The mobile device comprises a first graphical user interface (GUI) 112. The first OSE generates graphical data for a first OSE window (118). The first OSE window can be used on the first GUI for interfacing with the first OSE. A second operating system environment (second OSE) (224) is executed in a native mode on the mobile device, wherein the second OSE generates a GUI desktop (318) that is displayed on a second GUI (312). A second window (320) is rendered on the GUI desktop that comprises the first OSE window. The second OSE communicates relevant events to the first OSE, which are used by the first OSE to update the information used to render the first OSE window within the second OSE window.Type: GrantFiled: April 28, 2011Date of Patent: May 31, 2016Assignee: Google Technology Holdings LLCInventors: Binu Abraham, Joshua D. Galicia, Tae Jin Kim, Andrew N. Tzakis
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Patent number: 9348531Abstract: A method may comprise caching a portion of a pool of unique data blocks in a memory, the pool of unique data blocks comprising a plurality of unique blocks, at least some of the plurality of blocks in the pool of unique data blocks being referred to in at least one reference file. A list of blocks may be updated with any block in the cached portion of the pool of unique data blocks that is not referred to by at least one reference in the reference file(s). Different portions of the pool of unique data blocks may then continue to be cached and the list of blocks not referred to by at least one reference may be updated until the remaining portions of the pool of unique data blocks are cached. The blocks in the list of blocks may then be deleted from the pool of unique data blocks.Type: GrantFiled: October 14, 2013Date of Patent: May 24, 2016Assignee: Western Digital Technologies, Inc.Inventor: Tamir Ram
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Patent number: 9342444Abstract: Disclosed are systems, computer-readable mediums, and methods for reading a sequence number from regions of a solid state storage device. A latest region is determined based upon the sequence numbers and a checkpoint file is read within the latest region. A request for a block of data of a first branch is received. A first block of pointers associated with the first branch from the checkpoint file is read. A first pointer from the first block of pointers and a second block of pointers pointed to by the first pointer are read. A second pointer from the second block of pointers and a third block of pointers pointed to by the second pointer are read. A third pointer from the third block of pointers and data pointed to by the third pointer are read. The block of data of the first branch is determined based upon the read data. The block of data is returned.Type: GrantFiled: April 13, 2015Date of Patent: May 17, 2016Assignee: NetApp, Inc.Inventors: William Minckler, David D. Wright
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Patent number: 9342243Abstract: A method for implementing multi-operating system, applied to an electronic apparatus in which a Solid State Disk, SSD, is provided, the SSD including a plurality of partitions each of which corresponding to a unique logical snapshot table, and a plurality of operating systems being installed in different partitions respectively, wherein the method includes: determining a logical snapshot table corresponding to an operating system to be loaded currently as a first logical snapshot table during a Power On Self Test process of a basic input/output system; and determining a position of a partition in the SSD which corresponds to a reading/writing operation based on the first logical snapshot table if the reading/writing operation is performed on the SSD in a manner of Logical Block Addressing.Type: GrantFiled: November 27, 2013Date of Patent: May 17, 2016Assignee: Lenovo (Beijing) Co., Ltd.Inventors: Weixian Guo, Qi Guo, Dakai Zhou, Hongwei Li, Hongjiang Bi, Jianwei Lu, Lijun Ma
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Patent number: 9342365Abstract: A multi-core system includes at least three cores, a load comparator and a load migrator. The comparator simultaneously compares at least three loads of the at least three cores to detect a maximum load and a minimum load. The load migrator determines a first core having the maximum load as a source core and a second core having the minimum load as a target core of the at least three cores to migrate tasks from the source core to the target core.Type: GrantFiled: December 10, 2012Date of Patent: May 17, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Jung-Hi Min
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Patent number: 9336821Abstract: Provided is a recording apparatus including a light radiating unit that radiates light to an optical recording medium, a recording unit that performs light emission control of the light radiating unit, and performs recording on the optical recording medium, and a control unit that controls the recording unit in a manner that recording of remaining data starts from a position over a defect occurrence area, according to occurrence of a defect, in a state in which a logical address space and a physical address space are defined with respect to a recording area of the optical recording medium, and controls the recording unit in a manner that, when the buffer area is consumed and data is not completely recorded, a recording area of the remaining data that is not completely recorded is replaced with the spare area and the remaining data is recorded on the spare area.Type: GrantFiled: March 21, 2013Date of Patent: May 10, 2016Assignee: SONY CORPORATIONInventors: Hideyuki Nakamuro, Takashi Nagatomo, Toshihisa Iriyama
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Patent number: 9336048Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.Type: GrantFiled: July 17, 2015Date of Patent: May 10, 2016Assignee: Renesas Electronics CorporationInventors: Goro Sakamaki, Yuri Azuma
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Patent number: 9336136Abstract: Embodiments of the present disclosure provides a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provides a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller always performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100?p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.Type: GrantFiled: October 8, 2014Date of Patent: May 10, 2016Assignee: HGST Netherlands B.V.Inventors: Kanishk Rastogi, Sanoj Kizhakkekara Unnikrishnan, Anand Mitra
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Patent number: 9330007Abstract: In various embodiments, a storage device includes a magnetic media, a cache memory, and a drive controller. In embodiments, the drive controller is configured to establish a portion of the cache memory as an archival zone having a cache policy to maximize write hits. The drive controller is further configured to pre-erase the archival zone, direct writes from a host to the archival zone, and flush writes from the archival zone to the magnetic media. In embodiments, the drive controller is configured to establish a portion of the cache memory as a retrieval zone having a cache policy to maximize read hits. The drive controller is further configured to pre-fetch data from the magnetic media to the retrieval zone, transfer data from the retrieval zone to a host upon request by the host, and transfer read ahead data to the retrieval zone to replace data transferred to the host.Type: GrantFiled: November 30, 2012Date of Patent: May 3, 2016Assignee: Dell Products, LPInventors: Munif M. Farhan, William F. Sauber, Dina A. Eldin
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Patent number: 9323654Abstract: An apparatus including a memory having an array of blocks addressable using address bits; and a permutation circuit coupled to the memory and configured to permutate the address bits such that during a memory access blocks of data are rearranged virtually.Type: GrantFiled: July 17, 2013Date of Patent: April 26, 2016Assignee: Infineon Technologies AGInventor: Ljudmil Anastasov
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Patent number: 9323661Abstract: A memory system has a storage unit having two or more parallel read/write processing elements and non-volatile data recording areas for a logical block divided into a plurality of logical pages, and a control unit that generates log information for each unit of data written into the recording areas, determines for each logical page a log information recording area from a group of recording areas of the logical page, and controls the parallel operation elements to write the log information generated for a logical page into the log information recording area of the logical page and the data of the logical page into the other recording areas of the group of recording areas of the logical page.Type: GrantFiled: February 27, 2013Date of Patent: April 26, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Akinori Harasawa, Yoko Masuo
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Patent number: 9323659Abstract: A method of caching data is performed by a respective computer having one or more processors storing one or more storage management programs for execution by the one or more processors, non-volatile secondary storage and non-volatile cache memory. The method includes receiving from the non-volatile cache memory information identifying an amount of available storage in the non-volatile cache memory, and identifying a size of the management units in the non-volatile cache memory. The method further includes identifying write requests to write data to the non-volatile cache memory, sequentially writing to the non-volatile cache memory the write data for the identified write requests, to sequentially arranged locations in an address space of the non-volatile cache memory, and storing in memory metadata that maps the addresses or storage offsets of the write data to respective locations in the address space of the non-volatile cache memory.Type: GrantFiled: August 10, 2012Date of Patent: April 26, 2016Assignee: SANDISK ENTERPRISE IP LLCInventors: Serge Shats, Steven Ted Sanford
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Patent number: 9311014Abstract: There is provided a storage system capable to maintain a snapshot family comprising a plurality of members having hierarchical relations therebetween, and a method of operating thereof.Type: GrantFiled: September 25, 2013Date of Patent: April 12, 2016Assignee: INFINIDAT LTD.Inventors: Josef Ezra, Yechiel Yochai, Ido Ben-Tsion, Efraim Zeidner
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Patent number: 9311475Abstract: A computer system mechanism is provided that restricts execution of binaries, such as applications, kernel modules, shared libraries, on the computing system to only those that have been installed by an approved mechanism. The approved mechanism acts as a single entry point on the computing for installing new binaries. Any change in file content or metadata taints an executable file and prevents execution by the kernel. Files copied over and not installed via, the approved mechanism will not be executed.Type: GrantFiled: June 5, 2014Date of Patent: April 12, 2016Assignee: VMware, Inc.Inventors: Mukund Gunti, Christoph Klee
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Patent number: 9304896Abstract: A data processing node has an inter-node messaging module including a plurality of sets of registers each defining an instance of a GET/PUT context and a plurality of data processing cores each coupled to the inter-node messaging module. Each one of the data processing cores includes a mapping function for mapping each one of a plurality of user level processes to a different one of the sets of registers and thereby to a respective GET/PUT context instance. Mapping each one of the user level processes to the different one of the sets of registers enables a particular one of the user level processes to utilize the respective GET/PUT context instance thereof for performing a GET/PUT action to a ring buffer of a different data processing node coupled to the data processing node through a fabric without involvement of an operating system of any one of the data processing cores.Type: GrantFiled: August 5, 2013Date of Patent: April 5, 2016Assignee: III Holdings 2, LLCInventors: Prashant R. Chandra, Thomas A. Volpe, Mark Bradley Davis, Niall Joseph Dalton
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Patent number: 9304707Abstract: A method includes receiving, at a logical partition, a series of messages. Each message in the series of messages includes a respective block of data. The method further includes, in response to receiving the first message of the series of messages, suspending further processing of the series of messages. The method also includes identifying, from a header of the first message, a respective buffer address for each block of data. The method still further includes resuming processing of the series of messages. The method additionally includes, for each respective block of data, storing the respective block of data at the respective buffer address, and transferring the respective block of data from the corresponding buffer address to an open storage disk.Type: GrantFiled: October 30, 2013Date of Patent: April 5, 2016Assignee: CA, Inc.Inventors: David Helsley, Lawrence Lee
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Patent number: 9305009Abstract: A technique for managing replication of VSPs (Virtualized Storage Processors) proceeds on a per-VSP basis by (i) identifying the data objects associated with a VSP, (ii) establishing a common set of replication settings across all of the data objects associated with the VSP, and (iii) replicating the VSP by replicating each of the identified data objects associated with the VSP in accordance with the common set of replication settings established across all of the data objects associated with the VSP. The technique avoids the need for administrators to separately configure and manage replication on large numbers of individual data objects and thus reduces administrative burdens.Type: GrantFiled: September 30, 2013Date of Patent: April 5, 2016Assignee: EMC CorporationInventors: Jean-Pierre Bono, Himabindu Tummala, Assaf Natanzon
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Patent number: 9298603Abstract: A solid state drive having at least one NAND flash memory component organized in blocks, pages and cells. Each cell is adapted to store at least two bits. Each block of the memory component is adapted to be dynamically configured to store at least one bit per cell using a first mode of operation and dynamically configured to store at least two bits per cell using a second mode of operation while the mass storage device is operating, wherein the first mode of operation entails programming fewer bits of a cell in fewer passes as compared to the second mode of operation.Type: GrantFiled: November 15, 2012Date of Patent: March 29, 2016Assignee: OCZ Storage Solutions Inc.Inventor: Franz Michael Schuette
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Patent number: 9298550Abstract: A maintenance free storage container includes a container housing, storage servers, and a container controller. The container controller includes a processing module that is operable to maintain virtual storage server to physical storage server mapping information and to maintain storage server failure information. The processing module is further operable to dispersed storage error encode the virtual storage server to physical storage server mapping information to produce encoded mapping slices. The processing module is further operable to send the encoded mapping slices for dispersed storage outside of the maintenance free storage container. The processing module is further operable to dispersed storage error encode the storage server failure information to produce encoded failure data slices. The processing module is further operable to send the encoded failure data slices for dispersed storage outside of the maintenance free storage container.Type: GrantFiled: March 16, 2015Date of Patent: March 29, 2016Assignee: Cleversafe, Inc.Inventors: S. Christopher Gladwin, Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 9298619Abstract: Embodiments relate to tracking cache lines. An aspect of embodiments includes performing an operation by a processor. Another aspect of embodiments includes fetching a cache line based on the operation. Yet another aspect of embodiments includes storing in an instruction address register file at least one of (i) an operation identifier identifying the operation and (ii) a memory location identifier identifying a level of memory from which the cache line is populated.Type: GrantFiled: November 19, 2013Date of Patent: March 29, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Adam B. Collura, Brian R. Prasky
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Patent number: 9299457Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.Type: GrantFiled: February 23, 2014Date of Patent: March 29, 2016Assignee: QUALCOMM INCORPORATEDInventors: Dexter T. Chun, Yanru Li, Xiangyu Dong, Jungwon Suh, Jung Pill Kim, Deepti Vijayalakshmi Sriramagiri
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Patent number: 9298607Abstract: A controller is used in a computer system to control access to an NVRAM. The computer system includes a processor coupled to a non-volatile random access memory (NVRAM). The NVRAM is byte-rewritable and byte-erasable. The NVRAM stores data to be used by a set of agents including in-band agents and an out-of-band agent. The in-band agents run on a processor having one or more cores, and the out-of-band agent that runs on a non-host processing element. When the controller receives an access request from the out-of-band agent, the controller determines, based on attributes associated with the out-of-band agent, whether a region in the NVRAM is shareable by the out-of-band agent and at least one of the in-band agents.Type: GrantFiled: November 22, 2011Date of Patent: March 29, 2016Assignee: Intel CorporationInventors: Vincent J. Zimmer, Michael A. Rothman
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Patent number: 9286108Abstract: One particular implementation may take the form of a system or method for tracking application identification and application context in a context-isolated computing environment. The method may store such application information to reduce redundant information being stored on a stack. More particularly, the embodiment may store the application information in a context-specific marker frame. The context-specific marker frame may be stored once on the stack or it may be stored separately from the stack to maintain a small stack size. In another implementation, an invocation handler method may be called to store the redundant information about the executing application. The invocation handler may store the necessary information in a well-known location for later use by the virtual machine. The invocation handler may also provide further benefits, such as synchronization to ensure thread safety on shareable objects.Type: GrantFiled: October 30, 2008Date of Patent: March 15, 2016Assignee: Oracle America, Inc.Inventors: Saqib Ahmad, Tanjore Ravishankar, Thierry Violleau
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Patent number: 9286248Abstract: A method of managing peripherals is performed in a device coupled to a processor in a computer system. For example, the method is performed in an input/output memory management unit (IOMMU) or a peripheral. The method includes recording information associated with I/O activity for one or more peripherals in a log that has a first base address. The method also includes, without pausing the I/O activity, specifying a second base address for the log and setting a head pointer and a tail pointer for the log to indicate that the log is empty. The second base address is distinct from the first base address.Type: GrantFiled: October 4, 2013Date of Patent: March 15, 2016Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Andrew Kegel
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Patent number: 9280473Abstract: A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.Type: GrantFiled: December 2, 2004Date of Patent: March 8, 2016Assignee: Intel CorporationInventors: Sanjoy K. Mondal, Rajesh B. Patel, Lawrence O. Smith
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Patent number: 9280499Abstract: Embodiments of the invention include electronic communications devices having a memory in near field communication device, a memory arbitrator and a host processor. The near field communication (NFC) devices are configured to receive data and drive power from the communication signal. The memory arbitrator is connected to the NFC device and the memory. The memory arbitrator is also configured to access the memory in response to an access request from the NFC device. Additionally, the memory is configurable to be accessed by both the host processor and the NFC device according to embodiments of the present invention.Type: GrantFiled: August 18, 2014Date of Patent: March 8, 2016Assignee: Broadcom CorporationInventor: Craig Ochikubo
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Patent number: 9280555Abstract: A technique for protecting host data using, for example, snaps, asynchronous replication, and/or synchronous replication, includes storing both block-based objects and file-based objects in a common form—as files. With both block-based objects and file-based objects represented as the same type of underlying objects, data protection of both block-based and file-based objects is accomplished using a single set of data protection technologies, which are configured to perform data protection operations on files.Type: GrantFiled: March 29, 2013Date of Patent: March 8, 2016Assignee: EMC CorporationInventors: Jean-Pierre Bono, William Davenport, Miles A. de Forest, Philippe Armangau, Walter C. Forrester, Himabindu Tummala
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Patent number: 9274985Abstract: Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.Type: GrantFiled: June 13, 2012Date of Patent: March 1, 2016Assignee: NVIDIA CorporationInventors: Shu-Yi Yu, Ram Gummadi, John H. Edmondson
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Patent number: 9268577Abstract: An information processing apparatus includes a processor that executes an instruction stored in a fixed address area in a storage part; the storage part that stores a first startup program and a second startup program, contents of the second startup program being different at least partially from those of the first startup program; and an address conversion part that, when the processor carries out a predetermined startup different from an ordinary startup that is carried out at a time of starting power supply to the information processing apparatus, converts an address included in a read instruction issued by the processor indicating a storage area that stores the first startup program into an address indicating an other storage area that stores the second startup program, and sends the converted address to the storage part.Type: GrantFiled: August 22, 2013Date of Patent: February 23, 2016Assignee: RICOH COMPANY, LTD.Inventors: Tamon Sadasue, Satoshi Mori, Naoya Ohashi, Satoshi Aoki, Naoya Morita
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Patent number: 9268709Abstract: According to various embodiments, a storage controller configured to control storage of data in a pre-determined area of a storage medium may be provided. The storage controller may include a memory configured to store a write pointer, a reclaim pointer, and a wrapped around pointer. The write pointer may indicate a location of the storage medium to write incoming data. The reclaim pointer may indicate a location of the storage medium to perform a space reclamation. The wrapped around pointer may indicate a location of the storage medium where writing is to continue if writing of data reaches an end of the pre-determined area.Type: GrantFiled: October 17, 2013Date of Patent: February 23, 2016Assignee: Marvell International LTD.Inventors: Weiya Xi, Sufui Sophia Tan, Khai Leong Yong, Chun Teck Lim, Chao Jin, Zhi Yong Ching
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Patent number: 9262039Abstract: A method is used in displaying data storage system information. A graphical user interface (GUI) is provided that includes a tree structure of GUI components. Each of the GUI components is representative of an object in a data storage system. The tree structure includes lightweight information for the GUI components. At least one of the GUI components is updated by exercising a model view controller architecture. The GUI component is derived from a model chain that includes at least two models.Type: GrantFiled: June 30, 2008Date of Patent: February 16, 2016Assignee: EMC CorporationInventors: Scott E. Joyce, Anirudh Takkallapally, Vidhi Bhardwaj, Sreenath Rajagopal
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Patent number: 9256497Abstract: A checkpoint technique associated with an out of order based architecture of a processing device is described. An instruction may be received by its retirement unit and an identification as to whether the instruction is associated with a speculative error is performed. If the instruction is associated with the speculative error, then a first operation may be performed to replace state values of a first checkpoint of the processing device with state values of a second checkpoint. If the instruction is not associated with the speculative error, then the second checkpoint state may be updated based on the instruction.Type: GrantFiled: March 25, 2014Date of Patent: February 9, 2016Assignee: Intel CorporationInventors: Denis M. Khartikov, John H. Kelm, Naveen Neelakantam
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Patent number: 9235581Abstract: A cluster system includes a plurality of computing nodes connected to a network. Each node is configured to access its own storage device, and to send and receive input/output (I/O) operations associated with its own storage device. Further, each node of the plurality of nodes may be configured to have a function of acting as a first node, which sends a first message to other nodes of the plurality of nodes. The first message may include configuration information indicative of a data placement of data on the plurality of nodes in the cluster system according to an event. Following receipt of the first message from the first node, each of the other nodes may be configured to determine, based at least in part on the configuration information, whether data stored on its own storage device is affected by the event.Type: GrantFiled: January 30, 2015Date of Patent: January 12, 2016Assignee: HITACHI DATA SYSTEMS ENGINEERING UK LIMITEDInventors: Oleg Kiselev, Gaurab Paul, Christopher Youngworth
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Patent number: 9229760Abstract: Reducing virtual memory power consumption during idle states in virtual memory systems comprising tracking the topology of the system memory by the system hypervisor and operating system running on any selected virtual machine hosted by the system hypervisor. The idle states in the system memory are dynamically monitored and then the power consumption states in the system memory are dynamically reduced through the interaction of the hypervisor and the operation system running on the selected virtual machine.Type: GrantFiled: November 12, 2012Date of Patent: January 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ankita Garg, Dipankar Sarrna, Vaidyanathan Srinivasan
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Patent number: 9229840Abstract: Provided are a computer program product, system, and method for managing traces to capture data for memory regions in a memory. A trace includes a monitor parameter used by a trace procedure to monitor data in a memory device. A frequency is determined at which the trace procedure monitors the memory device. The trace procedure is invoked at the determined frequency to perform trace procedure operations comprising determining a region in the memory device according to the monitor parameter and copying data in the determined region to trace data in a data space.Type: GrantFiled: October 23, 2014Date of Patent: January 5, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Neal E. Bohling, Joseph V. Malinowski, David C. Reed, Max D. Smith
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Patent number: 9223516Abstract: The present invention discloses a data accessing method and an apparatus for performing the method. Through a newly-defined host logical unit (HLUN), a unique HLUN number is given to each LUN-to-LD/Partition mapping relationship, and the HLUN is present to external hosts. Therefore, all of the hosts in the same storage system may recognize different logical units (i.e., HLUN). Hence, when processing an Input/Output (IO) request issued from any one host, a storage virtualization controller (SVC) can correctly find the corresponding LD/Partition for accessing data without identifying the identity of the host.Type: GrantFiled: March 5, 2010Date of Patent: December 29, 2015Assignee: INFORTREND TECHNOLOGY, INC.Inventors: Michael Gordon Schnapp, Ching-Hao Chou
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Patent number: 9213641Abstract: Embodiments relate to tracking cache lines. An aspect of embodiments includes performing an operation by a processor. Another aspect of embodiments includes fetching a cache line based on the operation. Yet another aspect of embodiments includes storing in an instruction address register file at least one of (i) an operation identifier identifying the operation and (ii) a memory location identifier identifying a level of memory from which the cache line is populated.Type: GrantFiled: June 14, 2012Date of Patent: December 15, 2015Assignee: International Business Machines CorporationInventors: Adam B. Collura, Brian R. Prasky
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Patent number: 9208009Abstract: A method begins by a dispersed storage (DS) processing module generating a data object identifier for data to be stored in a dispersed storage network (DSN) and partitioning the data into a plurality of data partitions based on a set of retrieval preferences and data boundary information. For a data partition, the method continues with the DS processing module dispersed storage error encoding the data partition to produce a plurality of sets of encoded data slices and generating a plurality of sets of DSN addresses for the plurality of sets of encoded data slices, wherein a DSN address of the plurality of sets of DSN addresses includes a representation of the data object identifier, a representation of one or more retrieval preferences of the set of retrieval preferences, a representation of a corresponding portion of the data boundary information, and dispersed storage addressing information.Type: GrantFiled: December 9, 2013Date of Patent: December 8, 2015Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Wesley Leggette
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Patent number: 9201603Abstract: Dynamic logical mapping (“DLM”) provides a virtual layer interposed between a host and a data storage library. Residing on the library, DLM creates a data storage map that records and manages the relationship between a storage cartridge's physical address and that cartridge's mapping to a logical address. During runtime of the data storage library, DLM manages the physical to logical address mapping of each storage cartridge so as to optimize efficiency and speed of the data storage library.Type: GrantFiled: June 1, 2007Date of Patent: December 1, 2015Assignee: Oracle America, Inc.Inventors: Stephen G. Hamada, Brian L. Plomondon, Douglas A. Smith, Christopher J. West, Michael Silcott
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Patent number: 9189420Abstract: Embodiments of the present invention provide a wear-leveling method, a storage device, and an information system, where a storage region is divided into a plurality of storage sub-regions of the same size. The method includes: recording the accumulated number of write operations of each storage sub-region; and when the accumulated number of write operations of any one storage sub-region of the plurality of storage sub-regions reaches a predetermined remapping rate, mapping a logical address of the storage sub-region to a remapping physical address. With the wear-leveling method, the storage device, and the information system in the embodiments of the present invention, a logical address of a local data block on which too many write operations are performed may be evenly mapped to an overall physical storage region, thereby avoiding that local data is too hot and prolonging a service life of a storage medium.Type: GrantFiled: May 28, 2013Date of Patent: November 17, 2015Assignees: Huawei Technologies Co., Ltd., Tsinghua UniversityInventors: Hongliang Yu, Yuyang Du, Hao Gong
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Patent number: 9189165Abstract: A method for memory management, include allocating an empty page of a physical memory for reference data according to execution of an application program, and mapping the empty page to a virtual memory; checking a physical address of the physical memory to which the reference data has been loaded; mapping the checked physical address to the virtual memory to which the empty page has been mapped, and mapping the reference data; and releasing allocation of the allocated physical memory when the reference data is mapped to the virtual memory.Type: GrantFiled: July 15, 2013Date of Patent: November 17, 2015Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Kwang-Won Koh, Kang Ho Kim, Seung Hyub Jeon, Seungjo Bae
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Patent number: 9183036Abstract: Migration of a virtual machine to a new host is coordinated while data that is mapped into virtual (swap) memory of a source instance of the virtual machine (or guest) is properly handled. Sharing rights for one or more swap devices can be modified to facilitate the use of the swap devices by a new host and a corresponding (target) instance of virtual machine running on the new host.Type: GrantFiled: December 10, 2013Date of Patent: November 10, 2015Assignee: International Business Machines CorporationInventors: Utz Bacher, Reinhard Buendgen, Angel Nunez Mencias
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Patent number: 9177276Abstract: A computer-readable recording medium stores a program causing a computer to execute an association process that includes identifying a second storage location associated with a first storage location by referring to a memory unit configured to store storage location association information indicating relevance between the first storage location and the second storage location where data prepared at a second operation stage associated with a first operation stage is stored. The second storage location is identified when new data is stored to the first storage location where data prepared at the first operation stage among multiple stages for manufacture of a product is stored. The association process further includes creating and recording in the memory unit, data association information indicating the relevance between the new data stored in the first storage location and the latest data among the data that is stored in the second storage location.Type: GrantFiled: October 25, 2012Date of Patent: November 3, 2015Assignees: FUJITSU LIMITED, HONDA MOTOR CO., LTD.Inventors: Takashi Chiba, Shota Yamada, Yasuo Kurosaki
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Patent number: 9176866Abstract: A solid state drive and a method for providing active recycling for the solid state drive are disclosed. The solid state drive includes a plurality of blocks and each of the plurality of blocks includes a plurality of pages. The method steps include receiving a read request from a data requester; identifying at least one page containing data requested by the read request; determining whether the at least one page belongs to a block identified for active recycling; writing the at least one page to a different block when the at least one page belongs to the block identified for active recycling; and sending the at least one page to the data requester in response to the read request.Type: GrantFiled: November 15, 2013Date of Patent: November 3, 2015Assignee: Seagate Technology LLCInventors: Peng Xu, Lizhao Ma
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Patent number: 9176857Abstract: A method for managing an image memory in an embedded device is provided. A node is obtained from a linked list of the image memory. It is judged whether valid data is present in a memory block corresponding to the node. When no valid data is present, it is judged whether valid data is present in a memory block corresponding to a previous node of the node. When valid data is present in the previous node, it is further judged whether the valid data is movable. When the valid data is movable, memory block information described in the two nodes is exchanged, and the valid data previously stored in the memory block corresponding to the previous node is moved to the memory block corresponding to the node.Type: GrantFiled: August 14, 2012Date of Patent: November 3, 2015Assignee: MStar Semiconductor, Inc.Inventor: Hu He
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Patent number: 9172380Abstract: A method and an apparatus for supporting a self-destruction function in a baseband modem are provided. Aspects of the present disclosure are to address at least the above-mentioned problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an aspect of the present disclosure is to provide a self-destruction method and apparatus in which a self-impossible state is autonomously entered if the baseband modem of a receiving terminal which supports mobile communication is necessary. Another aspect of the present disclosure is to provide a method and apparatus for deleting information stored in memory when a command is received over a mobile communication network in which a baseband modem has been constructed and then entering a self-impossible state so that the terminal is not recovered although it is booted up again.Type: GrantFiled: July 2, 2014Date of Patent: October 27, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yun Ju Kwon, In Yup Kang
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Patent number: 9164880Abstract: Exemplary embodiments provide a technique to offload storage workload. In one aspect, a computer comprises: a memory; and a controller operable to manage a relationship among port information of an initiator port, information of a logical volume storing data from the initiator port, and port information of a target port to be used for storing data from the initiator port to the logical volume, and to cause another computer to process a storage function of a storage system including the logical volume and the target port by creating a virtual machine for executing the storage function and by configuring the relationship on said another computer, said another computer sending the data to the logical volume of the storage system after executing the storage function. In specific embodiments, by executing the storage function on said another computer, the workload of executing the storage function on the storage system is eliminated.Type: GrantFiled: October 23, 2012Date of Patent: October 20, 2015Assignee: HITACHI, LTD.Inventors: Masayuki Sakata, Akio Nakajima, Akira Deguchi
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Patent number: 9164920Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.Type: GrantFiled: December 12, 2014Date of Patent: October 20, 2015Assignee: Intel CorporationInventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard UhligQ, Lawrence Smith, III, Scott D. Rodgers