Abstract: Memory performance in a computer system that implements large page mappings is improved by dynamically tuning the page scan rate at which a memory sharing module (e.g., in a hypervisor) performs small page scanning operations that identify and exploit potential small page sharing opportunities within large pages. In operation, when free memory is relatively low, the hypervisor adjusts the page scan rate based on a statistical estimate of the percentage of virtual small pages that are mapped to physical large pages that are shareable. In this fashion the hypervisor dynamically tunes the sharing rate to reflect memory usage of applications. Further, unlike conventional approach to page sharing, the hypervisor proactively breaks large pages before resorting to more expensive memory reclamation techniques, such as ballooning and host swapping.

Abstract: A method and information processing system provide trace compression for trace messages. In response to a branch of a conditional branch instruction having not been taken or having been taken, a flag of a history buffer is set or cleared. A trace address message is generated in response to a conditional indirect branch instruction being taken, wherein the trace address message includes address information indicating the destination address of the taken branch, and an index value indicating a corresponding flag of the history buffer. In response to a return from interrupt or return from exception instruction, a predicted return address is compared to an actual return address. A trace address message is generated in response to the predicted and actual return addresses not matching. A trace address message is not generated in response to the predicted and actual return addresses matching.

Abstract: An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

Abstract: Methods and systems for a storage server are provided. One method includes storing data at a first storage tier by a processor executable storage operating system; tracking the data stored at the first storage tier for moving the data to a second storage tier; transferring the data from the first storage tier to the second storage tier; and updating a data structure that tracks a transfer block number of a block that stores the data, where the transfer block number is based on a virtual identifier, a generation count and an offset value of a storage chunk that is a portion of a physical volume block number address space.

Abstract: Migration of computer information. In one example embodiment, a method for migration of computer data includes modifying a volume boot record of a destination volume to a first state in which at least a portion of the destination volume becomes inaccessible to a standard file system, writing one or more snapshots of a source volume to the inaccessible portion of the destination volume while the volume boot record is in the first state, and restoring the volume boot record to a second state in which the inaccessible portion of the destination volume becomes accessible to the standard file system.

Abstract: An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.

Abstract: A handheld gaming device having a non-removable hard disk drive memory is used to perform gaming and non-gaming functions. The hard disk drive memory provides internal mass storage that is utilizable for storing various types of game-related information and non-game-related information. In one embodiment, the hard disk drive is configured to store selected portions of data in assigned regions of memory. The internal mass storage can be used to store saved game data, game specific data, and can be used as a buffer while streaming content from a remote server or drive. The internal mass storage also can be used to store other types of information, such as calendar information, personal appointments, maps, photographs, and other third party game related information.

Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.

Abstract: Disclosed is an address mapping method for a data storage device using a hybrid mapping scheme. The address mapping method determines whether write data includes a defined super sequential block (SSB), and selects an address mapping mode for the write data in accordance with whether or not a SSB is present.

Abstract: A device is described for operating a multi-partition networking system, the device comprising hardware resources for the operation of a primary partition for performing tasks, a primary buffer for holding packets for processing within a partition of the multi-partition system and a reserve buffer. The device is arranged to allocate the primary buffer for use by the primary partition and allocate the reserve buffer for use by the primary partition when at least a suspicious condition is detected in the primary partition. A method of operating a multi-partition networking system is also described.

Abstract: A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

Abstract: A hardware prefetch tablewalk system for a microprocessor including a tablewalk engine that is configured to perform hardware prefetch tablewalk operations without blocking software-based tablewalk operations. Tablewalk requests include a priority value, in which the tablewalk engine is configured to compare priorities of requests in which a higher priority request may terminate a current tablewalk operation. Hardware prefetch tablewalk requests having the lowest possible priority so that they do not bump higher priority tablewalk operations and are bumped by higher priority tablewalk requests. The priority values may be in the form of age values indicative of relative ages of operations being performed. The microprocessor may include a hardware prefetch engine that performs boundless hardware prefetch pattern detection that is not limited by page boundaries to provide the hardware prefetch tablewalk requests.

Abstract: A transactional memory receives a command, where the command includes an address and a novel DAT (Do Address Translation) bit. If the DAT bit is set and if the transactional memory is enabled to do address translations and if the command is for an access (read or write) of a memory of the transactional memory, then the transactional memory performs an address translation operation on the address of the command. Parameters of the address translation are programmable and are set up before the command is received. In one configuration, certain bits of the incoming address are deleted, and other bits are shifted in bit position, and a base address is ORed in, and a padding bit is added, thereby generating the translated address. The resulting translated address is then used to access the memory of the transactional memory to carry out the command.

Abstract: A method, system, apparatus, and computer program product are provided for facilitating autonomous device interaction. A method is provided that includes receiving response configuration information, receiving at least one indication of at least one occurrence of at least one triggering event, and receiving information regarding at least one peripheral device. The method further includes determining, based at least in part on the information regarding the at least one peripheral device and the response configuration information, at least one configured responsive action and performing at least one authorization procedure. The method even further includes determining, based at least in part on the at least one authorization procedure, whether the at least one configured responsive action is authorized, and, in an instance in which the at least one configured responsive action is authorized, causing the at least one configured responsive action to be automatically performed.

Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.

Abstract: A memory management unit (MMU) is disclosed for storing mappings between virtual addresses and physical addresses. The MMU includes a translation look-aside buffer (TLB) and a memory management unit controller. The TLB stores mappings between a virtual address and a physical address. The MMU controller receives a request to insert an entry into the TLB and performs a set of operations based on the received request. The MMU controller determines whether an entry stored in the TLB is associated with the virtual address of the request, removes the entry stored in the TLB that is associated with the virtual address and inserts the requested entry into the TLB.

Abstract: A method and apparatus for performing a read/write process on a recording medium having a defect, the method including determining an area of a recording medium, in which a defect, greater than a first set threshold, occurring in units of tracks, to be a massive defective area; adjusting a first parameter representing a logical track length, based on a size of a defect occurring in each track included in the massive defective area; and performing the read/write process on the recording medium by using the adjusted first parameter.

Abstract: A method for generating and recovering a memory snapshot of a virtual machine is provided. The method includes: obtaining a current Sth memory page of the virtual machine; identifying a page type of the current Sth memory page, where the page type includes an invalid data page and a valid data page; and recording the page type of the current Sth memory page in a memory snapshot file when the page is an invalid data page; and recording the page type and page data of the current Sth memory page in the memory snapshot file when the page is a valid data page, so that only valid data is stored according to the embodiments of the present invention, thereby reducing backup of invalid data, greatly shortening the generation time of the memory snapshot, reducing the size of the memory snapshot file, and saving storage resources.

Abstract: A user equipment (UE) receives downlink data using resource blocks in a wireless mobile communication system. The UE includes data processing circuitry coupled to a receiver that receives downlink control information including resource allocation information for the downlink data from a base station and to receive the downlink data mapped to physical resource blocks (PRBs) based on the downlink control information. The resource allocation information indicates virtual resource block (VRB) allocations for the user equipment. Each resource block corresponds to one time slot. A resource block pair includes a first resource block associated with a first time slot and a second resource block associated with a second time slot adjacent to the first time slot. The first and second resource blocks are allocated to the same frequency indices.

Abstract: A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone.

Abstract: A storage device is provided which includes a nonvolatile memory device configured to store a plurality of reference data, a memory configured to store a hash manage table used to manage a plurality of reference hash keys of each of the plurality of reference data, a hash key generator configured to generate a plurality of hash keys based on write requested data, and a memory controller configured to compare the plurality of hash keys and reference hash keys of each reference data to determine whether to store the write requested data in the nonvolatile memory device. The memory controller selects one of the plurality of reference data according to a similarity between the plurality of hash keys and the plurality of reference hash keys of each reference data and stores the write requested data and the selected reference data in the nonvolatile memory device to refer to each other.

Abstract: An aspect includes run-time instrumentation reporting. An instruction stream is executed by a processor. Run-time instrumentation information of the executing instruction stream is captured by the processor. Run-time instrumentation records are created based on the captured run-time instrumentation information. A run-time instrumentation sample point of the executing instruction stream on the processor is detected. A reporting group is stored in a run-time instrumentation program buffer. The storing is based on the detecting and the storing includes: determining a current address of the run-time instrumentation program buffer, the determining based on instruction accessible run-time instrumentation controls; and storing the reporting group into the run-time instrumentation program buffer based on an origin address and the current address of the run-time instrumentation program buffer, the reporting group including the created run-time instrumentation records.

Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.

Abstract: A computing apparatus computes a performance value of a program which includes a specific code which is executed multiple times by the processor and an access instruction for instructing the processor to access a memory area. The computing apparatus includes: a determining unit that determines, whether or not a cache memory is available for use at a time of execution of the access instruction in a simulation of an operation in which the processor executes the program; a generating unit that generates, in a case where the first determining unit has determined that the cache memory is not available, a computational code for computing the performance value of the specific code for a case where the processor executes the specific code, based on performance values of individual instructions within the specific code for a case where the cache memory is not used, without depending on an attribute of the memory area.

Abstract: A controller controlling a non-volatile memory includes a first memory area suitable for storing a first address table, a second memory area suitable for storing a second address table, an address conversion block suitable for converting a sector address received from a host into a physical address corresponding to the non-volatile memory with reference to the first and second address tables, and one or more function blocks suitable for sharing the second memory area with the address conversion block. The address conversion block exclusively uses the first memory area.

Abstract: A storage controller is provided that contains multiple processors. In some embodiments, the storage controller is coupled to a flash memory module having multiple flash memory groups, each flash memory group corresponding to a distinct flash port in the storage controller, each flash port comprising an associated processor. Each processor handles a portion of one or more host commands, including reads and writes, allowing multiple parallel pipelines to handle one or more host commands simultaneously.

Abstract: Provided is a method for accessing an application server. The method includes: obtaining an IP address or server domain name for accessing an application server from an access point list; initiating an access to the application server using the IP address or server domain name; and after the access to the application server succeeds, updating the access point list by storing an IP address delivered by the application server according to a load balancing policy to a blank entry of the access point list. By performing load balancing at an application server side according to the characteristics of an application program, the method improves the success rate of access by a user.

Abstract: A computing device includes technologies for securing indirect addresses (e.g., pointers) that are used by a processor to perform memory access (e.g., read/write/execute) operations. The computing device encodes the indirect address using metadata and a cryptographic algorithm. The metadata may be stored in an unused portion of the indirect address.

Abstract: Banks within a dynamic random access memory (DRAM) are managed with virtual bank managers. A DRAM controller receives a new memory access request to DRAM including a plurality of banks. If the request accesses a location in DRAM where no virtual bank manager includes parameters for the corresponding DRAM page, then a virtual bank manager is allocated to the physical bank associated with the DRAM page. The bank manager is initialized to include parameters needed by the DRAM controller to access the DRAM page. The memory access request is then processed using the parameters associated with the virtual bank manager. One advantage of the disclosed technique is that the banks of a DRAM module are controlled with fewer bank managers than in previous DRAM controller designs. As a result, less surface area on the DRAM controller circuit is dedicated to bank managers.

Abstract: A recording medium includes an encryption/decryption control unit, an authentication control unit, a non-volatile memory, and a volatile memory. The volatile memory stores recorded-position information of data recorded in a data recording area of the non-volatile memory under an unauthenticated condition that an authentication procedure by the authentication control unit has not been performed. The recorded-position information stored in the volatile memory is erased by stopping power supply by detaching the recording medium from the apparatus body, and becomes unavailable in the recording medium even if the power is supplied again to the recording medium so that the data recorded in the data recording area under the unauthenticated condition is not read out.

Abstract: Techniques are disclosed herein for paging I/O translation table entries. A host bridge of system hardware receives a request to fetch a first segment of an I/O translation table associated with one of a plurality of logical partitions executing in a computing system. The host bridge identifies a control register associated with the first segment. The control register includes a time base and an indication of whether the first segment is paged out to a storage volume. Upon determining that the first segment is paged out to the storage volume, a second segment is paged out from a location in memory to the storage volume. The first segment is paged in to the location.

Abstract: A network node comprising a processor configured to maintain a plurality of mapping entries for one or more virtual network instances, receive a data packet within a first virtual network instance, wherein the data packet comprises an inner destination address, match the inner destination address with one of the mapping entries, obtain an outer destination address that corresponds to the matched mapping entry, encapsulate the data packet with the outer destination address, and forward the encapsulated data packet based on the outer destination address, wherein the mapping entries maps out all of the addresses for a plurality of end nodes that participate in the first virtual network instance.

Abstract: Embodiments of the present invention provide a method and a system for supporting resource isolation in a multi-core architecture. In the method and system for supporting resource isolation in a multi-core architecture provided by the embodiments of the present invention, manners of inter-core operating system isolation, memory segment isolation, and I/O resource isolation are adopted, so that operating systems that run on different processing cores of the multi-core processor can run independently without affecting each other. Therefore, the present invention fully uses the advantages high integration level and low comprehensive costs of the multi-core processor, it is achieved that a failure domain of the multi-core processor remains in a single hard disk, and the multi-core processor has high reliability.

Abstract: One embodiment is a remote system management controller that virtualizes a video controller for a server that is managed by a remote computer.

Abstract: A method of managing an adapter includes identifying a firmware image configured to enable configuration firmware of a logical partition, where the firmware image is associated an expansion read-only memory (ROM). Access to the firmware image may be enabled by the logical partition, and the firmware image may be used to control of an operation of the adapter.

Abstract: An apparatus having a memory and a controller is disclosed. The memory is configured to (i) program a protected lower unit in a lower page of a location, (ii) generate a corrected lower unit by correcting the protected lower unit using a first error correction code and (iii) program a protected upper unit in an upper page of the location based on the corrected lower unit. The controller is configured to generate the protected upper unit by encoding an upper write data item using a second error correction code. The controller is on a separate die as the memory.

Abstract: A system for managing data includes providing at least one logical device having a table of information that maps sections of the logical device to sections of at least two storage areas. Characteristics of data associated with a one section of the logical device may be evaluated. The section of the data may moved between the at least two storage areas according to a policy and based on the characteristics of the data. The table of information is updated according to the movement of data between the at least two storage areas. Each of the at least two storage areas may correspond to a different storage tier, and each of the storage tiers may have different characteristic, such as speed of pools of storage devices within the tiers. A write target policy may be applied to store initial writes in a preferred location of the at least two storage areas.

Abstract: System TLBs are integrated within an interconnect, use a and share a transport network to connect to a shared walker port. Transactions are able to pass STLB allocation information through a second initiator side interconnect, in a way that interconnects can be cascaded, so as to allow initiators to control a shared STLB within the first interconnect. Within the first interconnect, multiple STLBs share an intermediate-level translation cache that improves performance when there is locality between requests to the two STLBs.

Abstract: A control apparatus capable of updating a user program while processing is being performed in a multitasking manner is provided. A processor includes a memory that stores a user program containing a program organization unit as well as a central processing unit executing a task containing the user program and also updating the program organization unit stored in the memory. The central processing unit is configured to execute a plurality of tasks concurrently and to execute each task with a period corresponding to the task. Moreover, the central processing unit is configured to update the program organization unit stored in the memory during the period of time from when a plurality of tasks to be executed have been finished until when the plurality of tasks are executed again.

Abstract: Embodiments of a system and method for providing frequency assignment with managed transceiver resources. A frequency assignment protocol manages transceiver resources in making channel assignment decisions based on a number of links and state of transceivers. Long-term traffic patterns are captured and transceiver resource decisions are made based on an analysis of the captured long-term traffic patterns to increase a selected metric, such as connectivity, capacity or any other measurable quantity.

Abstract: Disclosed are systems, computer-readable mediums, and methods for reading a sequence number from regions of a solid state storage device. A latest region is determined based upon the sequence numbers and a checkpoint file is read within the latest region. A request for a block of data of a first branch is received. A first block of pointers associated with the first branch from the checkpoint file is read. A first pointer from the first block of pointers and a second block of pointers pointed to by the first pointer are read. A second pointer from the second block of pointers and a third block of pointers pointed to by the second pointer are read. A third pointer from the third block of pointers and data pointed to by the third pointer are read. The block of data of the first branch is determined based upon the read data. The block of data is returned.

Abstract: Resource acquisition requests for a filesystem are executed under user configurable metering. Initially, a system administrator sets a ratio of N:M for executing N read requests for M write requests. As resource acquisition requests are received by a filesystem server, the resource acquisition requests are sorted into queues, e.g., where read and write requests have at least one queue for each type, plus a separate queue for metadata requests as they are executed ahead of any waiting read or write request. The filesystem server controls execution of the filesystem resource acquisition requests to maintain the ratio set by the system administrator.

Abstract: A device (110) and method (700) for providing windows in a multi-environment operating system is provided. A first operating system environment (first OSE) (222) is executed in a native mode on a mobile device (110). The mobile device comprises a first graphical user interface (GUI) 112. The first OSE generates graphical data for a first OSE window (118). The first OSE window can be used on the first GUI for interfacing with the first OSE. A second operating system environment (second OSE) (224) is executed in a native mode on the mobile device, wherein the second OSE generates a GUI desktop (318) that is displayed on a second GUI (312). A second window (320) is rendered on the GUI desktop that comprises the first OSE window. The second OSE communicates relevant events to the first OSE, which are used by the first OSE to update the information used to render the first OSE window within the second OSE window.

Abstract: A method may comprise caching a portion of a pool of unique data blocks in a memory, the pool of unique data blocks comprising a plurality of unique blocks, at least some of the plurality of blocks in the pool of unique data blocks being referred to in at least one reference file. A list of blocks may be updated with any block in the cached portion of the pool of unique data blocks that is not referred to by at least one reference in the reference file(s). Different portions of the pool of unique data blocks may then continue to be cached and the list of blocks not referred to by at least one reference may be updated until the remaining portions of the pool of unique data blocks are cached. The blocks in the list of blocks may then be deleted from the pool of unique data blocks.

Abstract: A method for implementing multi-operating system, applied to an electronic apparatus in which a Solid State Disk, SSD, is provided, the SSD including a plurality of partitions each of which corresponding to a unique logical snapshot table, and a plurality of operating systems being installed in different partitions respectively, wherein the method includes: determining a logical snapshot table corresponding to an operating system to be loaded currently as a first logical snapshot table during a Power On Self Test process of a basic input/output system; and determining a position of a partition in the SSD which corresponds to a reading/writing operation based on the first logical snapshot table if the reading/writing operation is performed on the SSD in a manner of Logical Block Addressing.

Abstract: A multi-core system includes at least three cores, a load comparator and a load migrator. The comparator simultaneously compares at least three loads of the at least three cores to detect a maximum load and a minimum load. The load migrator determines a first core having the maximum load as a source core and a second core having the minimum load as a target core of the at least three cores to migrate tasks from the source core to the target core.

Abstract: Disclosed are systems, computer-readable mediums, and methods for reading a sequence number from regions of a solid state storage device. A latest region is determined based upon the sequence numbers and a checkpoint file is read within the latest region. A request for a block of data of a first branch is received. A first block of pointers associated with the first branch from the checkpoint file is read. A first pointer from the first block of pointers and a second block of pointers pointed to by the first pointer are read. A second pointer from the second block of pointers and a third block of pointers pointed to by the second pointer are read. A third pointer from the third block of pointers and data pointed to by the third pointer are read. The block of data of the first branch is determined based upon the read data. The block of data is returned.

Abstract: Embodiments of the present disclosure provides a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provides a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller always performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100?p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.

Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register.

Abstract: Provided is a recording apparatus including a light radiating unit that radiates light to an optical recording medium, a recording unit that performs light emission control of the light radiating unit, and performs recording on the optical recording medium, and a control unit that controls the recording unit in a manner that recording of remaining data starts from a position over a defect occurrence area, according to occurrence of a defect, in a state in which a logical address space and a physical address space are defined with respect to a recording area of the optical recording medium, and controls the recording unit in a manner that, when the buffer area is consumed and data is not completely recorded, a recording area of the remaining data that is not completely recorded is replaced with the spare area and the remaining data is recorded on the spare area.