Address Mapping (e.g., Conversion, Translation) Patents (Class 711/202)
  • Patent number: 8976647
    Abstract: A network component comprising a hash generator configured to generate a first hash value using a first hash function and a packet, and generate a second hash value using a second hash function and the packet, a memory comprising a first hash table related to the first hash function and a second hash table related to the second hash function, the first and second hash tables comprising one or more entries, the one or more entries comprising a signature, a timestamp, and a path identification, a comparator configured to compare the first hash value and the second hash value with the one or more entries, and a forwarding decision module configured to forward the packet on a selected path.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: March 10, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventor: Haoyu Song
  • Patent number: 8972651
    Abstract: A storage system comprises a storage comprising a nonvolatile storage medium, and a storage control apparatus for inputting/outputting data to/from the storage. The storage control apparatus comprises a memory for storing management information, which is information used in inputting/outputting data to/from the storage, and a control part for controlling access to the storage. The control part stores the management information, which is stored in the memory, in the storage as a base image, and when the management information is updated subsequent to the base image being stored in the storage, creates a journal comprising information related to this update, and stores the journal in the storage as a journal group which is configured from multiple journals.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: March 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Kawamura, Junji Ogawa
  • Patent number: 8972659
    Abstract: There is provided a memory control device including a device driver that executes writing or reading of data to/from a main storage unit and temporary writing or reading of data to/from a cache unit including a plurality of cache blocks, and a control unit that issues an instruction for writing or reading of data of a file system to/from the main storage unit or the cache unit to the device driver. The control unit may notify priority information about a priority for data storage into a logical block to which the cache block is associated to the device driver.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: March 3, 2015
    Assignee: Sony Corporation
    Inventors: Hiroaki Ishizawa, Nobuhiro Kaneko, Shusuke Saeki, Takashi Kida, Tomohiro Katori
  • Patent number: 8972647
    Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 8966124
    Abstract: Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: February 24, 2015
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventor: Ronald Norman Prusia
  • Patent number: 8966209
    Abstract: Systems and methods are disclosed for efficient allocation policies for a system having non-volatile memory. A file system allocator of the system can be configured to allocate memory regions that are aligned with one or more logical blocks of a logical space (e.g., one or more super block-aligned regions). In some embodiments, the file system allocator can monitor the number of free sectors corresponding to each logical block. In other embodiments, the file system allocator can monitor a ratio of free space to total space corresponding to each logical block. The file system allocator can select a logical block based at least in part on the number of free sectors of the logical block. In some cases, the file system allocator can allocate the free sectors of the logical block in a sequential order.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: February 24, 2015
    Assignee: Apple Inc.
    Inventors: Daniel J. Post, Brian Sutton
  • Patent number: 8964528
    Abstract: For a network that includes several managed edge switching elements and several managed non-edge switching elements that are for implementing a logical switching element, some embodiments provide a method of distributing packet processing across the several managed non-edge switching elements. The method receives a packet for processing through the logical switching element. Based on a determination that the packet needs to be processed by a managed non-edge switching element, the method determines a particular managed non-edge switching element of the several managed non-edge switching elements to forward the packet. The method forwards the packet to the particular managed non-edge switching element for the particular managed non-edge switching element to process the packet.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: February 24, 2015
    Assignee: Nicira, Inc.
    Inventors: Martin Casado, Teemu Koponen, Pankaj Thakkar, W. Andrew Lambeth, Alexander Yip, Keith E. Amidon, Paul S. Ingram
  • Patent number: 8965995
    Abstract: A wireless storage management system adapted for being used in an electronic product for wirelessly communicating with a plurality of wireless storage devices includes an identity module assigning master and slave roles to the wireless storage devices, a hard disk manage module controlling the master device to obtain disk information about the wireless storage devices and further set an archive order for the slave devices, and a file manage module managing file access according to the archive order. The electronic product is only directly connected with the master device to make the hard disk manage module and the file manage module manage the slave devices via the master device. So the electronic product can conveniently view the disk information of all of the wireless storage devices and further realize the file access to all of the devices only by being directly connected with the master device.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: February 24, 2015
    Assignee: Cheng Uei Precision Industry Co., Ltd.
    Inventor: Chih-Jen Kuo
  • Patent number: 8966207
    Abstract: Virtual defragmentation of a storage. In one example embodiment, a method for virtual defragmentation of a storage includes various steps. For example, the method includes intercepting a move command directed to a storage during a defragmentation of the storage. The move command specifies an actual location of a block and a defrag location for the block in the storage. The method also includes updating a virtual defragmentation map to record the actual location of the block and the defrag location for the block. The method further includes preventing the block from being moved to the defrag location. The method also includes allowing file system metadata of the storage to be updated to falsely reflect that the block has been moved to the defrag location.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 24, 2015
    Assignee: Storagecraft Technology Corporation
    Inventor: Nathan S. Bushman
  • Patent number: 8966156
    Abstract: Disclosed is a memory device which comprises a data storing part having plural physical storage spaces; and a control part for storing data in the data storing part, wherein each of the physical storage spaces comprises a main area for storing user data at a write operation and a spare area for storing additional data other than the user data, the additional data including a logical address corresponding to a physical storage space and a link value indicating a physical storage space to be accessed next.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Wonmoon Cheon
  • Patent number: 8959302
    Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 17, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Kondoh, Isao Ohara
  • Patent number: 8954656
    Abstract: A method and system are disclosed for handling logical-to-physical mapping and reducing mapping table size. The method includes the storage device storing in fast access memory, such as DRAM, only the physical location of a primary cluster in each cluster group, and then writing location information for remaining clusters in a cluster group into the header of the data for the primary cluster of the cluster group in non-volatile memory. The system includes a storage device having volatile memory, non-volatile memory and a controller in communication with the volatile and non-volatile memory that is configured to carry out the method noted above.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 10, 2015
    Assignee: SanDisk Technologies Inc.
    Inventor: Nicholas James Thomas
  • Patent number: 8954657
    Abstract: A method of writing to one or more solid state disks (SSDs) employed by a storage processor includes receiving a command, creating sub-commands from the command based on a granularity, and assigning the sub-commands to the SSDs independently of the command thereby causing stripping across the SSDs.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie
  • Patent number: 8954708
    Abstract: A method of controlling a non-volatile memory device having multiple planes including receiving write requests from a host, the write requests each including a logical address, a write command, and a data set; storing the data sets at an address of a buffer; storing the buffer address in a mapping table that maps addresses of the buffer to the multiple planes; sequentially transmitting the data sets stored at respective buffer addresses to page buffers, respectively, of the planes corresponding to the buffer addresses according to the mapping table; and programming in parallel at least two data sets stored in respective page buffers to memory cells of the non-volatile memory device.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Yeong Kim, Du-Won Hong
  • Patent number: 8954959
    Abstract: A method and system for managing direct memory access (DMA) in a computer system without a host input/output memory management unit (IOMMU). The computer system hosts virtual machines and allows memory overcommit. The computer receives, from a guest operating system that runs on a virtual machine, a request for mapping a guest address to a bus address. The computer translates the guest address to a host address and pins a memory page containing the host address to keep the memory page in host memory. The host address is then returned to the guest operating system to allow a device to use the host address as the bus address for direct memory access (DMA) to a buffer managed by the guest operating system.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: February 10, 2015
    Assignee: Red Hat Israel, Ltd.
    Inventors: Michael Tsirkin, Christopher M. Wright
  • Patent number: 8954691
    Abstract: A network device that includes a first memory to store packets in segments; a second memory to store pointers associated with the first memory; a third memory to store summary bits and allocation bits, where the allocation bits correspond to the segments. The network device also includes a processor to receive a request for memory resources; determine whether a pointer is stored in the second memory, where the pointer corresponds to a segment that is available to store a packet; and send the pointer when the pointer is stored in the second memory. The processor is further to perform a search to identify other pointers when the pointer is not stored in the second memory, where performing the search includes identifying a set of allocation bits, based on an unallocated summary bit, that corresponds to the other pointers; identify another pointer, of the other pointers, based on an unallocated allocation bit of the set of allocation bits; and send the other pointer in response to the request.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Juniper Networks, Inc.
    Inventors: Robert Rhoades, Paul Kim, Gary Goldman
  • Patent number: 8954707
    Abstract: A mechanism is provided for automatic use of large pages. An operating system loader performs aggressive contiguous allocation followed by demand paging of small pages into a best-effort contiguous and naturally aligned physical address range sized for a large page. The operating system detects when the large page is fully populated and switches the mapping to use large pages. If the operating system runs low on memory, the operating system can free portions and degrade gracefully.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Gheith, Eric Van Hensbergen, James Xenidis
  • Patent number: 8954435
    Abstract: A method for storage reclamation in a shared storage device. The method includes executing a distributed computer system having a plurality of file systems accessing storage on a shared storage device, and initiating a reclamation operation by using a reclamation agent that accesses the shared storage device. The method further includes reading the file system data structure that represent unallocated storage blocks of one of the plurality of file systems that will undergo a reclamation operation. A plurality of I/O resources that are used to provide I/O to the unallocated storage blocks are then interrupted. Storage from the unallocated storage blocks is then reclaimed, and normal operation of the I/O resources that are used to provide I/O to the unallocated storage blocks is resumed.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: February 10, 2015
    Assignee: Symantec Corporation
    Inventors: Kedar Shrikrishna Patwardhan, Anirban Mukherjee, Kirubakaran Kaliannan
  • Patent number: 8954664
    Abstract: A disk drive comprising a rotatable disk, a head actuated over the disk, and a controller is disclosed. The controller is configured to write data on the disk using the head, to store logical-to-physical mapping information for data already written on the disk in a circular buffer as the data is written on the disk, and to write a plurality of metadata files on the disk using the head, wherein the plurality of metadata files are interspersed with the data on the disk and each of the metadata files includes contents of the circular buffer at a time the metadata file is written on the disk.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: February 10, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: David C. Pruett, Marcus A. Carlson
  • Patent number: 8954658
    Abstract: A method of managing logical unit numbers (LUNs) in a storage system includes identifying one or more LUN logical block address (LBA)-groups being affected. The one or more LUN LBA-groups defining a LUN. The method further determining the existence of an association of each of the affected LUN LBA-groups to a portion of a storage pool and maintaining a mapping table to track the association of the LUN LBA-groups to the storage pool.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: February 10, 2015
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Ruchirkumar D. Shah
  • Patent number: 8954685
    Abstract: A method, computer program product and computer system for virtualizing an SAS storage adapter, so as to allow logical partitions of a computer system to share a storage device. The method, computer program product and computer system includes assigning a logical storage adapter to an operating system of each of the logical partitions; creating a mapping from each of the logical partitions to a set of logical blocks in the storage device; and configuring the logical storage adapter using a hypervisor, so that a select partition can access a select set of logical blocks that the select partition is allowed to access.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Brian E Bakke, Ellen M Bauman, Timothy J Schimke, Lee A Sendelbach
  • Publication number: 20150039848
    Abstract: In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: QUAL COMM Incorporated
    Inventors: Dexter T. Chun, Jungwon Suh, Stephen A. Molloy, Jung Pill Kim
  • Patent number: 8948029
    Abstract: A method and system for network interface naming is described.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: February 3, 2015
    Assignee: Red Hat, Inc.
    Inventors: Andy Gospodarek, Neil Horman
  • Patent number: 8947445
    Abstract: A display controller includes a graphic memory, a graphic memory control unit and a scan control unit. The graphic memory has a storage capacity defined by a first directional size multiplied by a second directional size. The graphic memory control unit converts two-dimensional (2-D) addresses to one-dimensional (1-D) addresses based on an input clock signal and first directional total pixel number of a display panel for displaying input data, converts the 1-D addresses to physical 2-D addresses based on the first directional size and controls the graphic memory to store the input data. The display panel has a resolution corresponding to the first directional total pixel number multiplied by a second directional total pixel number of the display panel. The scan control unit increases scan addresses one line by one line to display data stored in the graphic memory according to a display resolution.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jun-Seok Han
  • Patent number: 8949550
    Abstract: The present invention relates to a coarse-grained reconfigurable array, comprising: at least one processor; a processing element array including a plurality of processing elements, and a configuration cache where commands being executed by the processing elements are saved; and a plurality of memory units forming a one-to-one mapping with the processor and the processing element array. The coarse-grained reconfigurable array further comprises a central memory performing data communications between the processor and the processing element array by switching the one-to-one mapping such that when the processor transfers data from/to a main memory to/from a frame buffer, a significant bottleneck phenomenon that may occur due to the limited bandwidth and latency of a system bus can be improved.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: February 3, 2015
    Assignee: SNU R&DB Foundation
    Inventors: Ki Young Choi, Kyung Wook Chang, Jong Kyung Paek
  • Patent number: 8943292
    Abstract: A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: January 27, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ravindraraj Ramaraju, David R. Bearden, Prashant U. Kenkare
  • Patent number: 8943293
    Abstract: A method includes receiving an address at a tag state array of a cache, wherein the cache is configurable to have a first size and a second size that is smaller than the first size. The method further includes identifying a first portion of the address as a set index, wherein the first portion has a same number of bits when the cache has the first size as when the cache has the second size. The method further includes using the set index to locate at least one tag field of the tag state array, identifying a second portion of the address to compare to a value stored at the at least one tag field, locating at least one state field of the tag state array that is associated with a particular tag field that matches the second portion, identifying a cache line based on a comparison of a third portion of the address to at least one status bit of the at least one state field when the cache has the second size, and retrieving the cache line.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: January 27, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Ajay Anant Ingle, Lucian Codrescu, Jian Shen
  • Patent number: 8938602
    Abstract: A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: January 20, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Colin Christopher Sharp, Thomas Andrew Sartorius
  • Patent number: 8935506
    Abstract: MemX provides a distributed system that virtualizes cluster-wide memory to support data-intensive and large memory workloads in virtual machines (VMs), and provides benefits in virtualized settings: (1) VM workloads that access large datasets can perform low-latency I/O over virtualized cluster-wide memory; (2) VMs can transparently execute very large memory applications that require more memory than physical DRAM present in the host machine; (3) reduces the effective memory usage of the cluster by de-duplicating pages that have identical content; (4) existing applications do not require any modifications to benefit from MemX such as the use of special APIs, libraries, recompilation, or relinking; and (5) supports live migration of large-footprint VMs by eliminating the need to migrate part of their memory footprint resident on other nodes.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: January 13, 2015
    Assignee: The Research Foundation for The State University of New York
    Inventor: Kartik Gopalan
  • Patent number: 8930659
    Abstract: A computer system, having a non-volatile storage unit (152), a main storage unit (151), and a data processor (102) including a memory management unit (102A) for managing a program stored in the non-volatile storage unit and the main storage unit to transfer a program stored in the non-volatile storage unit to the main storage unit, wherein the memory management unit (102A) includes a program storage control function of storing a program subjected to predetermined data conversion and a program yet to be subjected to predetermined data conversion in the non-volatile storage unit, and a function of combining programs subjected to predetermined data conversion so as not to bridge over a boundary between blocks at the execution of the program storage control function, as well as, at a first access to a certain block, expanding all the data included in the block to a corresponding block of the main storage unit.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventor: Masahiko Takahashi
  • Patent number: 8930622
    Abstract: The disclosed embodiments are directed to methods and apparatuses for providing efficient and enhanced protection of data stored in a FLASH memory system. The methods and apparatuses involve a system controller for a plurality of FLASH memory devices in the FLASH memory system that is capable of protecting data using two layers of data protection, including inter-card card stripes and intra-card page stripes.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Holloway H. Frost, Charles J. Camp, Ken Scianna, Lance W. Shelton
  • Patent number: 8929829
    Abstract: A data movement controller (20) for controlling the movement between a shared data store (18) and a local data store (16) such that the data can be used by a plurality of parallel data processing elements is described. The data movement controller (20) comprises a set of data registers (56, 58, 60) which, in use, are loaded with different data parameters (57, 61, 62) to define a plurality of different ways in which data is transferred between the shared data store (18) and a set of processing elements (12). The data parameters (57, 61, 62) define a set of time delays for transferring portions of the data to predefined ones of the plurality of processing elements (12) and the type of overall data transfer that is to be carried out.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: January 6, 2015
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventor: Martin Whitaker
  • Patent number: 8924952
    Abstract: A computing device includes a data store having two or more partitions. A first partition can be used to store information, to host a first operating system, and to perform computing tasks requested by a user. The computing tasks can be performed by the first operating system and can use/manipulate the stored information. The computing device can communicate over a network with a software server to determine whether a software update for the computing device is available for download. The software update can be downloaded into the second partition autonomously from the computing tasks being performed by the first operating system in the first partition. The downloaded software update can also be installed into the second partition autonomously from the computing tasks being performed. When the device is rebooted, either the first operating system or the second operating system (if the installation was successful) can be booted.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Xuefeng Hou
  • Patent number: 8924832
    Abstract: A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can be increased and improved performance can be attained.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: December 30, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Johnny A. Lam
  • Patent number: 8918620
    Abstract: A storage control apparatus includes a controller configured to control to convert an access to logical volume into an access to associated RAID group in response to an access to the corresponding virtual volume on the basis of access conversion information, monitor frequency of access to each of logical volumes, select a logical volume on the basis of the monitored frequency of access, move data stored in a RAID group corresponding to the selected logical volume to a different RAID group corresponding to a logical volume to be a data shift destination, and update the access conversion information to convert access to the RAID group corresponding to the selected logical volume into access to the different RAID group.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Tadashi Matsumura, Masahiro Yoshida, Kenji Uchiyama
  • Patent number: 8918578
    Abstract: Described herein are embodiments of methods and systems of using a timer based memory buffer for metrology. One embodiment of the method comprises receiving metrology data from one or more metrology sensors; writing at least part of the metrology data to a volatile memory; incrementing a write pointer to indicate the metrology data contained within the volatile memory; and repeating the above until a timer expires, then reading at least a portion of the metrology data from the volatile memory.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: December 23, 2014
    Assignee: General Electric Company
    Inventors: Bradley Richard Ree, Mark Victor Penna, George William Alexander
  • Patent number: 8918619
    Abstract: There are provided a storage system and a method of operating thereof. The method comprises: a) representing to a plurality of hosts an available logical address space divided into one or more logical groups (e.g. logical volumes, virtual partitions, snapshots, combinations of a given logical volume and its respective snapshot(s), etc.), and b) mapping between one or more contiguous ranges of addresses related to the logical address space and one or more contiguous ranges of addresses related to the physical address space, wherein said mapping is provided with the help of one or more mapping trees, each tree assigned to a separate logical group in the logical address space.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: December 23, 2014
    Assignee: Infinidat Ltd.
    Inventors: Yechiel Yochai, Haim Kopylovitz, Leo Corry
  • Publication number: 20140372713
    Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.
    Type: Application
    Filed: June 17, 2013
    Publication date: December 18, 2014
    Inventors: Hernan A. Castro, Kerry Dean Tedrow, Jack Chinho Wu
  • Publication number: 20140372695
    Abstract: A new data block to be stored in the dispersed storage system is received. When it is determined that a previous data segment contains sufficient space for the new data block, the previous data segment is retrieved from a plurality of dispersed storage units. A revised data segment is generated by aggregating the new data block with at least one existing data block of the previous data segment. A plurality of slices are generated for the revised data segment. The plurality of slices are stored in the plurality of dispersed storage units.
    Type: Application
    Filed: March 30, 2010
    Publication date: December 18, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Zachary J. Mark, S. Christopher Gladwin
  • Patent number: 8914570
    Abstract: In a method for storing data in a flash memory array, the flash memory array includes a plurality of physical pages. The method includes receiving a request to perform a data access operation through a communication bus. The request includes data and a logical page address. The method further includes allocating one or more physical pages of the flash memory array to perform the data access operation. The method further includes, based on a historical usage data of the flash memory array, selectively encoding the data contained in the logical page into the one or more physical pages.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ganesh Balakrishnan, Anil Krishna
  • Patent number: 8914381
    Abstract: In one embodiment, the correlation filter can use one of several data structure to track each migration unit and reject successive accesses within a period of time to each migration unit. In one embodiment, the correlation filter uses a space efficient data structure, such as a hash indexed correlation array to store the address of referenced migration units, and to filter accesses to a single migration unit that are correlated accesses resulting from multiple accesses to the same migration unit during a sequential I/O stream. In one embodiment, the correlation array contains a global timeout, which resets each element to a default value, clearing all store migration unit address values from the correlation array. In one embodiment, each element of the migration array can time-out separately.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventors: David A. Majnemer, Wenguang Wang
  • Patent number: 8914579
    Abstract: Provided is a method that, in the case of managing areas of a non-volatile memory of an information recording module by a file system, increases the speed of processing for writing file data and file system management information, and furthermore prevents a decrease in the rewriting lifetime of the non-volatile memory. The information recording module (2) is provided with a page cache control unit (217) that stores page cache information (224) in the non-volatile memory (22) of the information recording module (2) and performs control such that a specific physical block is used as a cache when writing small-sized data. Also, an access module (1) is provided with a page cache information setting unit (104) that sets information necessary for page cache control in the information recording module (2).
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: December 16, 2014
    Assignee: Panasonic Corporation
    Inventors: Takuji Maeda, Shigekazu Kogita, Shinji Inoue, Hiroki Etoh, Makoto Ochi, Masahiro Nakamura
  • Patent number: 8914608
    Abstract: A data storage device includes a storage medium configured to store data; and a controller configured to control the storage medium, the controller including address mapping information. The controller is configured to divide the address mapping information into at least a first address mapping table and a second address mapping table based on information regarding temporary data received at the controller. The first address mapping table is configured to map one or more addresses of valid data and to be backed up to the storage medium. The second mapping address table being configured to map one or more addresses of the temporary data and to not be backed up to the storage medium.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jin Oh, Jeonguk Kang
  • Patent number: 8914602
    Abstract: A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: December 16, 2014
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wen-Jui Lin, Hsien-Chun Chang, Yi-Shu Chang, Wen-Che Wu
  • Patent number: 8914609
    Abstract: A computing device includes an interface, memory, and a processing module. The memory stores a directory and inode tables. The directory stores a file identifier and a corresponding inumber for each file that is stored in storage units. An inode table stores an inumber, metadata, and a DSN address for each file stored in a corresponding storage unit. The processing module is operable to monitor, for each of the inode tables, utilization of the memory. The processing module is further operable to monitor, for each of the storage units, utilization of memory of the storage units. The processing module is further operable to process, for the inode table and/or the corresponding storage unit, per inode table memory utilization data and per storage unit memory utilization data to adjust memory utilization of the inode table and/or memory utilization of the corresponding storage unit.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: December 16, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Gary W. Grube, S. Christopher Gladwin
  • Patent number: 8913483
    Abstract: In a hierarchical switching architecture that includes at least one lower level managed switching element that connects to several higher level managed switching elements, some embodiments provide a method of identifying a higher level managed switching element to which the lower level managed switching element forwards a packet for further processing. The method computes a value based on a set of attributes of the packet. The method identifies a record from a hierarchy traversal table based on the computed value. The record specifies (1) a first higher level managed switching element as a primary higher level managed switching element and (2) a second higher level managed switching element as a secondary higher level managed switching element. The primary and secondary higher level managed switching elements are for forwarding the packet for further processing. The method forwards the packet to one of the higher level managed switching elements.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: December 16, 2014
    Assignee: Nicira, Inc.
    Inventors: Benjamin L. Pfaff, Ethan J. Jackson, Teemu Koponen, Pankaj Thakkar
  • Publication number: 20140365746
    Abstract: A map of storage locations that indicates storage locations associated whose associated I/O transactions are to be processed by firmware running on a storage controller is maintained. The map is communicated to a storage controller driver. The storage controller driver receives a first I/O transaction request. Based on the map, and the storage location to be accessed by the first I/O transaction request, the first I/O transaction request is sent to a storage device without further processing by the firmware running on the storage controller. The storage controller driver receives a second I/O transaction request. Based on the map and the location to be accessed by the second I/O transaction request, the second I/O transaction request is sent for further processing by the firmware running on the storage controller.
    Type: Application
    Filed: June 26, 2013
    Publication date: December 11, 2014
    Inventor: Gerald E. Smith
  • Patent number: 8909894
    Abstract: Automatically aligning virtual blocks of partitions to blocks of underlying physical storage is disclosed. In some embodiments, a starting offset of a first partition included in a logical container is detected. In some embodiments, a misalignment correction amount for a first partition included in a logical container is detected. In some embodiments, a misalignment associated with a first partition included in a logical container is corrected.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: December 9, 2014
    Assignee: Tintri Inc.
    Inventors: Pratap V. Singh, Vyacheslav V. Malyugin, Mark G. Gritter, Edward K. Lee
  • Patent number: 8909891
    Abstract: Method embodiments for facilitating overflow storage of special data sets that reside on a single logical volume are provided. A virtual logical volume is created from unallocated memory units across a plurality of logical volumes in a volume group. The virtual logical volume appears the same as any one of the logical volumes in the volume group to an external client. Upon receipt of a special data set that must reside in a single logical volume, an attempt is first made to allocate the special data set to one of the logical volumes in the volume group. If that allocation attempt fails, the special data set is allocated to the virtual logical volume. The virtual logical volume may be created only upon the failure to allocate the special data set to one of the logical volumes, and may be destroyed if sufficient space in one of the logical volumes is freed up to transfer the special data set.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: David Charles Reed, Max Douglas Smith, Kyle Barret Dudgeon, Esteban Rios
  • Patent number: 8909898
    Abstract: Embodiments of copy equivalent protection using secure page flipping for software components within an execution environment are generally described herein. An embodiment includes the ability for a Virtual Machine Monitor (VMM), Operating System Monitor, or other underlying platform capability to restrict memory regions for access only by specifically authenticated, authorized and verified software components, even when part of an otherwise compromised operating system environment. In an embodiment, an embedded VM is allowed to directly manipulate page table mappings so that, even without running the VMM or obtaining VMXRoot privilege, the embedded VM can directly flip pages of memory into its direct/exclusive control and back. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: David Durham, Prashant Dewan