Abstract: A method, apparatus, and system of presentation of a read-only clone Logical Unit Number (LUN) to a host device as a snapshot of a parent LUN are disclosed. In one embodiment, a method includes generating a read-write clone LUN of a parent LUN and coalescing an identical data instance of the read-write clone LUN and the parent LUN in a data block of a volume of a storage system. A block transfer protocol layer is modified to refer the read-write clone LUN as a read-only clone LUN, according to the embodiment. Furthermore, according to the embodiment, the read-only clone LUN is presented to a host device as a snapshot of the parent LUN.

Abstract: A cache is provided, including a data array having a plurality of entries configured to store a plurality of different types of data, and a tag array having a plurality of entries and configured to store a tag of the data stored at a corresponding entry in the data array and further configured to store an identification of the type of data stored in the corresponding entry in the data array.

Abstract: Disclosed is a method and apparatus for a storage system comprising at least one mobile random access storage device capable of storing first or second data. At least one docking station is associated with an address wherein the address is identifiable by at least one host computer. A first and second sub-address is associated with the at least one docking station wherein the first and second sub-addresses are identifiable by the at least one host computer. The first sub-address corresponds to a first virtual device adapted for storing the first data on a first virtual media. The second sub-address corresponds to a second virtual device adapted for storing the second data on a second virtual media wherein the second virtual media is a different media type from the first virtual media.

Abstract: A system, method, and computer program product are provided for receiving an incoming data stream. The system comprises a multi-core processor with a memory unit that is configured to include a circular queue that receives a data stream. The circular queue is divided into a plurality of sub-queues determined as a multiple of the number of processing cores, and each sub-queue is assigned to one processing core such that as data is received into a region covered by a particular sub-queue, the processing core assigned to the particular sub-queue processes the data. The system is also configured to update a head pointer and a tail pointer of the circular queue. The head pointer is updated as data is received into the circular queue and the tail pointer is updated by a particular processing core as it processes data in its assigned sub-queue.

Abstract: A method, an article of manufacture, and system for heapifying an object. The method includes: storing, in a working set, a first address of a certain object in a stack frame, copying the certain object into the heap area and holding a second address of the certain object in the heap area, following each stack frame to find a pointer pointing to the first address stored in the working set, converting the address that the pointer points to into the second address, proceeding to a next stack frame, where the address conversion includes storing an address of another object in the working set if the converted address is stored as a value of a field of the other object in the stack frame, and terminating the process in response to a lack of pointers found in the stack frame to point to the addresses stored in the working set.

Abstract: To make it possible to perform efficient program development, a development system includes a label managing unit configured to update, when an execution program D2 is regenerated, a label information table D3, which corresponds to the execution program D2, for generating execution screen data D5 and executes or does not execute, according to update content of the label information table D3, update of ID information associated with the label information table D3 and the regenerated execution program D2 and a drawing apparatus configured to associate, when execution screen data D5 is generated based on the label information table D3, ID information of a value same as the ID information, which is associated with the label information table D3 at a point when the execution screen data D5 is generated, with the generated execution screen data D5.

Abstract: A method, device, and computer readable medium for striping rows of data across logical units of storage with an affinity for columns is provided. Alternately, a method, device, and computer readable medium for striping columns of data across logical units of storage with an affinity for rows is provided. When data of a logical slice is requested, a mapping may provide information for determining which logical unit is likely to store the logical slice. In one embodiment, data is retrieved from logical units that are predicted to store the logical slice. In another embodiment, data is retrieved from several logical units, and the data not mapped to the logical unit is removed from the retrieved data.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: An apparatus and a method for processing data in a terminal are provided. The method includes when a specific program including a specific extension is stored, identifying addresses representing a position of specific data having the specific extension in an entire storage space, initializing the specific program based on the identified addresses, and generating an address table based on the identified addresses, and storing the generated address table.

Abstract: A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

Abstract: A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry.

Abstract: In one embodiment, the semiconductor device includes a data control unit configured to selectively process data for writing to a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a write operation, the group of processing functions including at least three processing functions. The enabled processing function may be performed based on a signal received over a single pin associated with the group of processing functions. In another embodiment, the semiconductor device includes a data control unit configured to process data read from a memory. The data control unit is configured to enable a processing function from a group of processing functions based on a mode register command during a read operation. Here, the group of processing functions including at least two processing functions.

Abstract: Various methods and systems for securing access to hash-based storage systems are disclosed. One method involves receiving information to be stored in a storage system from a storage system client and then generating a key. The key identifies the information to be stored. The value of the key is dependent upon a secret value, which is associated with the storage system. The key is generated, at least in part, by applying a hash algorithm to the information to be stored. The key can then be returned the key to the storage system client. The storage system client can then use the key to retrieve the stored information.

Abstract: The present invention is directed to systems and methods for improving access to non-volatile solid-state storage systems. Embodiments described herein provide a physical chunk number (PCN), or a physical page number (PPN), by which a controller can access the next available chunks (or pages) in a programming sequence optimized by concurrency. By incrementing the PCN, the controller can program consecutive chunks in the optimized programming sequence. In one embodiment, the programming sequence is determined at the time of initial configuration and the sequence seeks to synchronize data programming and data sending operations in subcomponents of the storage system to minimize contention and wait time. In one embodiment, the PCN includes an index portion to a superblock table with entries that reference specific blocks within the subcomponents in a sequence that mirrors the optimized programming sequence, and a local address portion that references a particular chunk to be programmed or read.

Abstract: The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a controller configured to control a dual mapping method comprising: performing a base conversion on a received data pattern and mapping a resulting base converted data pattern to one of a first number of program state combinations corresponding to a first group of memory cells; and determining a number of error data units corresponding to the base converted data pattern and mapping the number of error data units to one of a number of second program state combinations corresponding to a second group of memory cells. The number of error data units are mapped to the one of the second number of program state combinations corresponding to the second group of memory cells without being base converted.

Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.

Abstract: A memory storage device, a memory controller, and a method for identifying a valid data are provided. A rewritable non-volatile memory chip of the memory storage device includes physical blocks. Each of the physical blocks has physical pages. In the present method, logical blocks are configured and mapped to a portion of the physical blocks, wherein each of the logical blocks has logical pages. When a data to be written by a host system into a specific logical page is received, a substitute physical block is selected, the data is written into a specific physical page in the substitute physical block, and the address of a physical page in which a previous data corresponding to the specific logic page is written is recorded into the specific physical page. Thereby, a physical page containing the latest valid data can be identified among several physical pages corresponding to a same logical page.

Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.

Abstract: Aspects of the disclosure provide a virtual memory management method that can reduce memory requirement and improve system performance. The method can include detecting a scenario, matching the detected scenario with a predefined scenario that includes a pre-set mapping relationship of a first module to a dynamic memory address within a first portion of a dynamic memory, and writing the first module from a static memory to the first portion of the dynamic memory at the dynamic memory address. Further, the method can include executing the first module from the dynamic memory. In addition, the method can include storing a second module at a second portion of the dynamic memory independent of the detected scenario.

Abstract: A data processing apparatus has processing circuitry for executing a memory access instruction in order to generate a memory transaction comprising at least one address transfer specifying a memory address, and at least one associated data transfer specifying data to be accessed at the specified memory address. The apparatus is arranged to route each address transfer and associated data transfer via a first interface when the specified memory address is within a first memory address range, or to route each address transfer and associated data transfer via a second interface when the specified memory address is within a second memory address range and is further configured, when using the first interface, to execute the memory access instruction so as to cause each address transfer and associated data transfer to be presented at the first interface with a first relative timing.

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

Abstract: Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used to determine the available locations and amount of available space in the storage devices. The data storage schemes for one or more of the stored data files are changed to a basic storage mode when the size of a new data file configured in accordance with an assigned data storage scheme exceeds the amount of available space. The configured new data file is stored in accordance with the assigned data storage scheme in one or more of the available locations and the locations of the new data file are recorded.

Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.

Abstract: A computer implemented method analyzes shared memory accesses during execution of an application program. The method includes instrumenting events of shared memory accesses in the application program, where the application program is to be executed on a target configuration having p nodes; executing the application program using p1 processing nodes, where p1 is less than p and satisfies a constraint. For accesses made by the executing application program, the method determines a target thread and maps determined target threads to either a remote node or a local node corresponding to a remote memory access and to a local memory access, respectively. Also disclosed is a computer-readable storage medium that stores a program of executable instructions that implements the method, and a data processing system. The invention can be implemented using a language such as Unified Parallel C (UPC) directed to a partitioned global address space (PGAS) paradigm.

Abstract: When a dynamic data structure is used for managing sparsely accessed data stored in memory of a digital computer, pages of the memory are dynamically allocated and de-allocated to respective portions of the dynamic data structure so that the pages become distributed over the portions of the dynamic data structure and the de-allocated pages include free pages that are mapped in the dynamic data structure and free pages that are not mapped in the dynamic data structure. To reduce memory fragmentation and recover memory, upon de-allocating a page of memory from a portion of the data structure, a determination is made whether or not to un-map the de-allocated page from the portion of the dynamic data structure so that un-mapping of the de-allocated page has a probability that is the inverse of a superlinear function of the number of allocated pages in the portion of the dynamic data structure.

Abstract: One or more techniques and/or systems are provided for non-disruptively addressing misalignment between a virtual data format and an underlying data format. Virtual data, such as a guest operating system of a virtual machine, may be stored within a virtual structure, such as a virtual machine disk, according to a virtual data format. The virtual structure may be stored within a storage device according to a storage data format. If misalignment is detected, then a new data container may be created within the storage device. A shim, sized according to a misalignment offset, may be inserted into the new data container in order to align the new data container with the storage device. Virtual data may be migrated from the virtual structure to the new data container to achieve alignment. During the migration, the virtual data may remain available from the virtual structure (e.g., a virtual machine may still execute).

Abstract: A method for accessing a flash memory, the method includes: receiving a read request that is associated with a logical address that is mapped to a physical address of a set of flash memory cells; accessing multiple mapping data structures of different granularity to obtain the physical address of the set of flash memory cells; wherein during at least one point in time at least one mapping data structure is stored in an erase block and wherein the erase block comprises multiple physical pages that are written in a sequential manner and are associated with logical page addresses that are assigned in a random manner; and reading a content of the set of flash memory cells.

Abstract: Techniques are provided for accessing sector data. An embedded storage function is received. One or more data management functions are generated in response to receiving the embedded storage function. The one or more data management functions are invoked to retrieve the sector data from a sector table.

Abstract: The present invention provides a system and method for virtual block numbers (VBNs) to disk block number (DBN) mapping that may be utilized for both single and/or multiple parity based redundancy systems. Following parity redistribution, new VBNs are assigned to disk blocks in the newly added disk and disk blocks previously occupied by parity may be moved to the new disk.

Abstract: A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.

Abstract: Systems and methods are provided for handling uncorrectable errors that may occur during garbage collection of an index page or block in non-volatile memory.

Abstract: A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.

Abstract: A method for temporary storage of data units including receiving a first data unit to store in a hardware linked list queue on a communications adapter, reading a first index value from the first data unit, determining that the first index value does match an existing index value of a first linked list, and storing the first data unit in the hardware linked list queue as a member of the first linked list. The method further includes receiving a second data unit, reading a second index value from the second data unit, determining that the second index value does not match any existing index value, allocating space in the hardware linked list queue for a second linked list, and storing the second data unit in the second linked list.

Abstract: Systems and methods for dynamically remapping elements of a set to another set based on random keys. Application of said systems and methods to dynamically mapping regions of memory space of non-volatile memory, e.g., phase-change memory, can provide a wear-leveling technique. The wear leveling technique can be effective under normal execution of typical applications, and in worst-case scenarios including the presence of malicious exploits and/or compromised operating systems, wherein constantly migrating the physical location of data inside the PCM avoids information leakage and increases security; wherein random relocation of data results in the distribution of memory requests across the physical memory space increases durability; and wherein such wear leveling schemes can be implemented to provide fine-grained wear leveling without overly-burdensome hardware overhead e.g., a look-up table.

Abstract: In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

Abstract: In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if so, to re-map the access request to a virtual device page in a system memory associated with the VM, based at least in part on information stored in a control register of the processor. Other embodiments are described and claimed.

Abstract: Methods described in the present disclosure may be based on a direct transformation of original data to “shaped” data. In a particular example, a method comprises generating a first portion of output data by applying a mapping of input bit sequences to output bit sequences to a first portion of input data, updating the mapping of the input bit sequences to the output bit sequences based on the first portion of the input data to generate an updated mapping, reading a second portion of the input data, and generating a second portion of the output data by applying the updated mapping of the input bit sequences to the output bit sequences to the second portion of the input data.

Abstract: Examples are disclosed for allocating a block of persistent storage or accessing a block of persistent storage based on a storage service string that includes a universally unique identifier and associated metadata.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Techniques are described herein that can be used to process inbound network protocol units. In some implementations, the techniques may process inbound DDP segments. In some implementations, a steering tag of an inbound network protocol unit may be used to access a context accessible to a network component. In some implementations, the context may include an array useful to determine whether all segments in a group have been received by the network component. In some implementations, the segments may be stored in a first buffer and transferred to a second buffer after all segments in a group have been received.

Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

Abstract: A non-volatile storage system is provided with reduced delays associated with loading and updating a logical-to-physical mapping table from non-volatile memory. The mapping table is stored in a plurality of segments, so that each segment can be loaded individually. The segmented mapping table allows memory access to logical addresses associated with the loaded segment when the segment is loaded, rather than delaying accesses until the entire mapping table is loaded. When loading mapping segments, segments can be loaded according to whether there is a pending command or by an order according to various algorithms.

Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.

Abstract: Systems and methods allow access between a software application residing within a processor module and an accelerator module having an accelerator address space distinct from the processor address space. Access to the accelerator is provided by mapping the accelerator address space to an associated portion of the processor address space. The association may be made based upon a description of the accelerator address space provided in a pre-determined format. The formatted description is processed to create a software indicator module that is provided to the user application to thereby indicate the associated portion of the processor address space. Access to the associated portion of the processor address space by the software program is redirected to the accelerator address space to thereby allow the application to access the accelerator. A functional interface that allows the software application to issue commands and perform other administrative functions on the accelerator module may also be provided.

Abstract: A method and a storage system are provided for implementing deterministic memory allocation for indirection tables for persistent media or disk drives, such as, shingled perpendicular magnetic recording (SMR) indirection tables. A plurality of fixed-size memory pools are used to store indirection data. The distribution of pool allocate sizes is fixed. A pool allocate size is selected based upon an indirection system request size.

Abstract: Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described.

Abstract: A cache layer leverages a logical address space and storage metadata of a storage layer (e.g., storage layer) to cache data of a backing store. The cache layer maintains access metadata to track data characteristics of logical identifiers in the logical address space, including accesses pertaining to data that is not in the cache. The access metadata may be separate and distinct from the storage metadata maintained by the storage layer. The cache layer determines whether to admit data into the cache using the access metadata. Data may be admitted into the cache when the data satisfies cache admission criteria, which may include an access threshold and/or a sequentiality metric. Time-ordered history of the access metadata is used to identify important/useful blocks in the logical address space of the backing store that would be beneficial to cache.

Abstract: A method, system and computer-program product for re-initializing a storage volume with an previously created volume map being preserved to allow access to previously stored data sets. The invention includes creating a new volume map in an unused volume area where the new volume map has pointers to new data sets. One of the new data sets contains the previously created volume map that points to previously created data sets. Each volume map is referenced by a volume label and includes a VTOC and an optional VTOC index. The pointers in the VTOC are data set control block (DSCB) records.

Abstract: The present disclosure includes systems and techniques relating to data type based alignment of data written to non-volatile memory. In some implementations, an apparatus includes an input, an output, and control logic coupled with the input and the output, where the control logic is configured to modify placement of data written to a non-volatile memory based on a first data type of the data. The first data type is distinct from a second data type also written to the non-volatile memory, and the placement of the data of the first data type is modified in relation to placement of data of the second data type in the non-volatile memory.

Abstract: An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components.