Abstract: A method of operation of a storage control system including: providing a memory controller; accessing a volatile memory table by the memory controller; writing a non-volatile semiconductor memory for persisting changes in the volatile memory table; and restoring a logical-to-physical table in the volatile memory table, after a power cycle, by restoring a random access memory with a logical-to-physical partition from a most recently used list.

Abstract: System embodiments for facilitating overflow storage of special data sets that reside on a single logical volume are provided. A virtual logical volume is created from unallocated memory units across a plurality of logical volumes in a volume group. The virtual logical volume appears the same as any one of the logical volumes in the volume group to an external client. Upon receipt of a special data set that must reside in a single logical volume, an attempt is first made to allocate the special data set to one of the logical volumes in the volume group. If that allocation attempt fails, the special data set is allocated to the virtual logical volume. The virtual logical volume may be created only upon the failure to allocate the special data set to one of the logical volumes, and may be destroyed if sufficient space in one of the logical volumes is freed up to transfer the special data set.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

Abstract: A method for controlling data for a storage system comprises: receiving a write input/output (I/O) command of a data from a host computer, the write I/O command including an application ID identifying an application operating on the host computer which sends the write I/O request; maintaining a record of a relation between the application ID in the write I/O command and a storage location of the data to be written in a first volume of the storage system; determining, based on the application ID, whether a data transfer function between the first volume and a second storage volume is to be performed on the data beyond writing the data to the storage location in the first volume; and if the data transfer function is to be performed on the data, then performing the data transfer function on the data to the second volume.

Abstract: A storage system includes a Central Processing Unit (CPU) that has a physically-addressed solid state disk (SSD), addressable using physical addresses associated with user data and provided by a host. The user data is to be stored in or retrieved from the physically-addressed SSD in blocks. Further, a non-volatile memory module is coupled to the CPU and includes flash tables used to manage blocks in the physically addressed SSD. The flash tables have tables that are used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. The flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.

Abstract: Improvements for the efficiency of data transfer within interconnected components of a virtual network, and in particular components of a single physical computing device are provided. The components exchange data as if they were communicating over an actual communications network using networking protocols. Data packets to be sent from one component to another are buffered by final destination address to improve efficiency of packet delivery.

Abstract: Systems and methods for performing RAID I/O operations in PCIe-based storage resources are disclosed. In accordance with embodiments of the present disclosure, a method for performing a read operation may be provided. The method may include overlaying memory address space of storage resources of a source logical unit for the read operation onto a destination address. The method may also include determining whether the source logical unit is a RAID0 array. The method may additionally include generating a source address in a receive buffer for each storage resource of the source logical unit if the source logical unit is a RAID0 array. The method may further include storing data received from each storage address of the logical unit at the generated source address of the receive buffer associated with such storage resource.

Abstract: The method includes creating a master copy of a header for all packets of a data transmission event, the master copy including a plurality of intact constant header information, the plurality of intact constant header information being constant for all packets of the data transmission event, storing unique header information for all packets of the data transmission event, the unique header information including information unique to at least one packet of the data transmission event, tokenizing identities of each packet of the data transmission event to create a tokenized packet ID for each packet, and indexing the stored unique header information based on the tokenizing. A computer program product for directing a computer processor to perform a method. According to the method, at packet read-time, unique header information associated with the packet is overlayed onto the master copy to create a unique packet.

Abstract: A translation table has entries that each include a share bit and a delta bit, with pointers that point to a memory block that includes reuse bits. The share bit is set to indicate a translation table entry is sharing its memory block with another translation table entry. In addition, a translation table entry may include a private delta in the form of a pointer that references a memory fragment in the memory block that is not shared with other translation table entries, wherein the private delta references previously-stored content. When a translation table has a private delta, its delta bit is set. The private delta is generated by analyzing a data buffer for content that is similar to previously-stored content.

Abstract: Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system.

Abstract: A system and an article of manufacture for de-duplicating virtual machine image accesses include identifying one or more identical blocks in two or more images in a virtual machine image repository, generating a block map for mapping different blocks with identical content into a same block, deploying a virtual machine image by reconstituting an image from the block map and fetching any unique blocks remotely on-demand, and de-duplicating virtual machine image accesses by storing the deployed virtual machine image in a local disk cache.

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract: A data storage system is disclosed that utilizes a high performance caching architecture. In one embodiment, the caching architecture utilizes a cache table, such as a lookup table, for referencing or storing host data units that are cached or are candidates for being cached in the solid-state memory. Further, the caching architecture maintains a segment control list that specifies associations between particular cache table entries and particular data segments. Such separation of activities related to the implementation of a caching policy from activities related to storing cached data and candidate data provides robustness and scalability while improving performance.

Abstract: Memory management units (MMUs) are disclosed. In one aspect, an MMU may have a first interface to a component. The first interface may receive one of a read of updated data from, and a write of updated data to, a virtual memory address. The virtual memory address may initially correspond to a first physical memory location in an only one time programmable (OTP) non-volatile memory (NVM). The MMU may have a remapping unit to remap a correspondence of the virtual memory address from the first physical memory location to a spare physical memory location. The MMU may also have a second interface to the OTP.NVM. The second interface may allow the updated data to be read from or written to the spare physical memory location of the OTP NVM. Methods performed by the MMUs, and methods and articles useful for manufacturing MMUs, are also disclosed.

Abstract: A routing device includes means for executing a function of translation between at least one address of a first network and at least one address of a second network; means for receiving an association request from a terminal of said first network; means for generating a second request by substituting a source address in the association request by an address of the routing device in the second network; means for sending the second request to an address translation server of the second network; and means for sending said terminal, in response to said association request, a response received from said address translation server in response to sending said second request.

Abstract: Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

Abstract: A method for providing redundancy in a virtualized storage system for a computer system is provided. The method includes determining a first set of first logical addresses to provide a virtual storage volume. A redundancy schema is then selected to provide redundancy data for primary data stored in the first set of first logical addresses. A second set of second logical addresses is determined to provide logical storage for the primary data and for the redundancy data. The first set of first logical addresses and the second set of second logical addresses are then mapped and a set of physical storage addresses is selected from a set of physical storage elements. Mapping between the second set of second logical addresses and the set of physical addresses is then performed to provide physical storage for the primary data and the redundancy data stored in the virtual storage volume.

Abstract: Systems, methods, and apparatus with improved techniques for copying data from a source memory location to a destination memory location are disclosed. An exemplary method includes receiving a source address that indicates the source memory location, a destination address that indicates the destination memory location, and receiving a size indicator that indicates the size of the data. When the size is less than a threshold size, a particular pointer in a jump table is accessed, based upon the size that points to particular load and store instructions. The jump table includes a plurality of pointers that point to a corresponding one of a plurality of load and store instructions. The particular load-store instructions are then executed with a processor of the computing device to copy the data from the source memory location to the destination memory location. Several other efficiency-improvement aspects are also disclosed that may be used in connection with these steps to further improve copy efficiencies.

Abstract: A LUN is provided that can store multiple datasets (e.g., data and/or applications, such as virtual machines stored as virtual hard drives). The LUN is partitioned into multiple partitions. One or more datasets may be stored in each partition. As a result, multiple datasets can be accessed through a single LUN, rather than through a number of LUNs proportional to the number of datasets. Furthermore, the datasets stored in the LUN may be pivoted. A second LUN may be generated that is dedicated to storing a dataset of the multiple datasets stored in the first LUN. The dataset is copied to the second LUN, and the second LUN is exposed to a host computer to enable the host computer to interact with the dataset. Still further, the dataset may be pivoted from the second LUN back to a partition of the first LUN.

Abstract: A serial attached small computer systems interface (SAS) module includes a first port with (i) a first physical layer device and (ii) a first port control module. The first physical layer device communicates with a plurality of initiators. The first port control module comprises a first world wide number (WWN) table. The first WWN table comprises connection rates of the plurality of initiators during communication with the first physical layer device. Each of the connection rates is a last connection rate of a respective one of the plurality of initiators.

Abstract: ICC-NCQ priority and deadline information in conjunction with an estimation of command access time that is specific to SMR drives are used improve command queue optimization. Estimated completion times are determined based on the internal subcommands that the drive has to execute to complete the host read or write command taking into account whether all or part of the data will be or already is stored in write-twice cache, E-region and/or I-region. The command processor selects the next command for execution based on calculated access times with adjusted priority based on the specified deadline for the command. As the deadline approaches, the priority of the command increases. For high priority data writes as specified by a host, an optimized storage plan is selected as appropriate using the “write-twice cache” (WTC) region, E-region or I-region.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: Various embodiments provide a method and apparatus of providing a frugal cloud file system that efficiently uses the blocks of different types of storage devices with different properties for different purposes. The efficient use of the different types of available storage devices reduces the storage and bandwidth overhead. Advantageously, the reduction in storage and bandwidth overhead achieved using the frugal cloud file system reduces the economic costs of running the file system while maintaining high performance.

Abstract: A data translation system and method. This invention provides a reverse approach to implement a M bit input to N bit output cumulative/monotonic transfer function, (where M>N) by a (2**N)×M bit memory instead of the conventional (2**M)×N bit memory. The invention offers substantial circuit size savings without compromising on transfer function resolution and is independent of transfer function mapping algorithms. The M bit memory content of the reverse LUT contains input video group information for each output level and the (2**N) addresses of the reverse LUT represent the corresponding transfer function output levels. This data to address representation of the input to output relationship is exactly opposite to the conventional address to data format. Search and compare methods are employed to locate the input video group that the incoming video belongs to and the associated address of the reverse LUT represents the output.

Abstract: A computing system includes virtualization software including a guest operating system (OS). A method maintains, by the virtualization software layer, a first shadow page table for use in a kernel mode and a second shadow page table for use in a user mode. The virtualization software switches between using the first shadow page table and the second shadow page table when the guest OS switches between operating in the kernel mode and the user mode.

Abstract: A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector.

Abstract: Aspects of the subject matter described herein relate to a storage architecture. In aspects, an address provided by a data source is translated into a logical storage address of virtual storage. This logical storage address is translated into an identifier that may be used to store data on or retrieve data from a storage system. The address space of the virtual storage is divided into chunks that may be streamed to the storage system.

Abstract: A method, apparatus, and a storage system are provided for implementing enhanced indirection update for indirected storage devices. A novel remapping command generated by a host is used to store indirection data. The remapping command enables remapping of a set of Logical Block Addresses (LBAs) to a different set of LBAs. The remapping command includes a source LBA, length and a destination LBA.

Abstract: The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address.

Abstract: The present invention is adapted to data storage technology field, and provides a reading/writing control method and system for nonvolatile memory, the method including the following steps: dividing valid blocks in the nonvolatile memory into different zones, the zones including at least one data zone having fixed number of valid blocks and one exchange zone having at least two valid blocks; creating a mapping table of logic blocks and physical blocks in each zone; establishing a mapping table of logic pages and physical pages in the blocks based on redundant area information of pages in the blocks, and storing the mapping table of the logic blocks and physical blocks in each zone and the mapping table of logic pages and physical pages in each block in a private data area; and writing data segments in an idle page of the blocks of the data zones in sequence, or reading data segments from valid pages in the data zones, thus the data reading/writing speed and efficiency is promoted.

Abstract: A nonvolatile memory manages stored data by using physical addresses. By using logical addresses associated with the physical addresses, an arithmetic processing unit outputs a process instruction to be performed on data stored in the nonvolatile memory. On the basis of the process instruction output by the arithmetic processing unit, an access control unit detects an instruction to move the data stored in the nonvolatile memory. An address conversion table control unit stores therein the association relationship between the physical addresses and the logical addresses. When the access control unit detects the instruction to move the data, the address conversion table control unit changes the association relationship such that a logical address at the move destination is associated with the physical address in which the data is stored.

Abstract: According to one embodiment, a method for accessing host data records stored on a VTS system includes receiving a mount request to access at least one host data record on a VTS system, determining a number of host compressed data records per physical block on a sequential access storage medium, determining a PBID that corresponds to the requested at least one host data record, accessing a physical block on the sequential access storage medium corresponding to the PBID, and outputting the physical block without outputting an entire logical volume that the physical block is stored to. In another embodiment, a VTS system includes random access storage, sequential access storage, support for at least one virtual volume, a storage manager having logic for determining a PBID that corresponds to a SLBID, and logic for performing the above described method. Other methods are also described.

Abstract: A method for performing meta block management is provided. The method is applied to a controller of a Flash memory having multiple channels, where the Flash memory includes a plurality of blocks respectively corresponding to the channels. The method includes: utilizing a meta block mapping table to store block grouping relationships respectively corresponding to a plurality of meta blocks, where blocks in each meta block respectively correspond to the channels; and when it is detected that a specific block corresponding to a specific channel within a meta block does not have remaining space for programming, according to the meta block mapping table, utilizing at least one blank block corresponding to the specific channel within at least one other meta block as extension of the specific block, for use of further programming. An associated memory device and a controller thereof are also provided.

Abstract: A disk drive is disclosed that utilizes an additional address mapping layer between logical addresses used by a host system and physical locations in the disk drive. Physical locations configured to store metadata information can be excluded from the additional address mapping layer. As a result, a reduced size translation table can be maintained by the disk drive. Improved performance, reduced costs, and improved security can thereby be attained.

Abstract: Systems and methods are disclosed for adaptive writing behavior for a system having non-volatile memory (“NVM”). A memory interface of a system can be configured to determine whether a write preference of the system is skip-sequential. In response to determining that the write preference is skip-sequential, the memory interface can sequentially program data to a first set of pages of a block of the NVM. In addition, the memory interface can sequentially pre-merge gaps between the first set of pages with one or more pages of a data block. Moreover, the memory interface can be configured to switch to an alternative programming state in response to determining that at least one condition has been satisfied. For example, the memory interface can stop programming data sequentially, and instead program data in the order that the data is received from a file system.

Abstract: A method begins by a processing module determining whether to convert data between a redundant array of independent disks (RAID) format and a dispersed storage network (DSN) format. The method continues with the processing module retrieving the data from a RAID memory to produce retrieved RAID data when the data is to be converted from the RAID format to the DSN format. The method continues with the processing module converting stripe-block data of the retrieved RAID data into a plurality of sets of encoded data slices and outputting the plurality of sets of encoded data slices to at least one of the RAID memory and a DSN memory for storage therein.

Abstract: A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to the memory package at a bandwidth and latency associated with the volatile memory. A directory map associates a volatile memory address with data in the high-density memory. A copy of the directory map is stored in the high-density memory. The methods allow writing to and reading from the memory package using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).

Abstract: Systems and methods that allow for dynamically deconfiguring, reconfiguring and/or otherwise configuring nodes (e.g., processors) in a symmetric multiprocessing system (e.g., a symmetric multiprocessor) in a manner that avoids, or at least limits, inefficiencies such as renumbering of node IDs, system reboots, SW configuration handle changes, and the like. In one arrangement, a number of modules, tables and/or the like that are configured to generate node IDs and/or convert node IDs from one form to another form can be intelligently implemented within an SMP to allow the various processes and/or components of an SMP to utilize the node IDs in a more efficient manner. For instance, as SDs in an SMP are often configured to work with CNIDs (e.g., for use in determining at which node a particular requested cache line resides), any node GNIDs that are sent to the SD for processing can first be converted into corresponding CNIDs.

Abstract: A cache is provided, including a data array having a plurality of entries configured to store a plurality of different types of data, and a tag array having a plurality of entries and configured to store a tag of the data stored at a corresponding entry in the data array and further configured to store an identification of the type of data stored in the corresponding entry in the data array.

Abstract: Disclosed is a method and apparatus for a storage system comprising at least one mobile random access storage device capable of storing first or second data. At least one docking station is associated with an address wherein the address is identifiable by at least one host computer. A first and second sub-address is associated with the at least one docking station wherein the first and second sub-addresses are identifiable by the at least one host computer. The first sub-address corresponds to a first virtual device adapted for storing the first data on a first virtual media. The second sub-address corresponds to a second virtual device adapted for storing the second data on a second virtual media wherein the second virtual media is a different media type from the first virtual media.

Abstract: A method, apparatus, and system of presentation of a read-only clone Logical Unit Number (LUN) to a host device as a snapshot of a parent LUN are disclosed. In one embodiment, a method includes generating a read-write clone LUN of a parent LUN and coalescing an identical data instance of the read-write clone LUN and the parent LUN in a data block of a volume of a storage system. A block transfer protocol layer is modified to refer the read-write clone LUN as a read-only clone LUN, according to the embodiment. Furthermore, according to the embodiment, the read-only clone LUN is presented to a host device as a snapshot of the parent LUN.

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract: A system, method, and computer program product are provided for receiving an incoming data stream. The system comprises a multi-core processor with a memory unit that is configured to include a circular queue that receives a data stream. The circular queue is divided into a plurality of sub-queues determined as a multiple of the number of processing cores, and each sub-queue is assigned to one processing core such that as data is received into a region covered by a particular sub-queue, the processing core assigned to the particular sub-queue processes the data. The system is also configured to update a head pointer and a tail pointer of the circular queue. The head pointer is updated as data is received into the circular queue and the tail pointer is updated by a particular processing core as it processes data in its assigned sub-queue.

Abstract: A method, an article of manufacture, and system for heapifying an object. The method includes: storing, in a working set, a first address of a certain object in a stack frame, copying the certain object into the heap area and holding a second address of the certain object in the heap area, following each stack frame to find a pointer pointing to the first address stored in the working set, converting the address that the pointer points to into the second address, proceeding to a next stack frame, where the address conversion includes storing an address of another object in the working set if the converted address is stored as a value of a field of the other object in the stack frame, and terminating the process in response to a lack of pointers found in the stack frame to point to the addresses stored in the working set.

Abstract: A method, device, and computer readable medium for striping rows of data across logical units of storage with an affinity for columns is provided. Alternately, a method, device, and computer readable medium for striping columns of data across logical units of storage with an affinity for rows is provided. When data of a logical slice is requested, a mapping may provide information for determining which logical unit is likely to store the logical slice. In one embodiment, data is retrieved from logical units that are predicted to store the logical slice. In another embodiment, data is retrieved from several logical units, and the data not mapped to the logical unit is removed from the retrieved data.

Abstract: To make it possible to perform efficient program development, a development system includes a label managing unit configured to update, when an execution program D2 is regenerated, a label information table D3, which corresponds to the execution program D2, for generating execution screen data D5 and executes or does not execute, according to update content of the label information table D3, update of ID information associated with the label information table D3 and the regenerated execution program D2 and a drawing apparatus configured to associate, when execution screen data D5 is generated based on the label information table D3, ID information of a value same as the ID information, which is associated with the label information table D3 at a point when the execution screen data D5 is generated, with the generated execution screen data D5.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: An apparatus and a method for processing data in a terminal are provided. The method includes when a specific program including a specific extension is stored, identifying addresses representing a position of specific data having the specific extension in an entire storage space, initializing the specific program based on the identified addresses, and generating an address table based on the identified addresses, and storing the generated address table.

Abstract: A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

Abstract: A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry.