Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to receive a data stream including one or more data blocks; determine a size of the one or more data blocks; determine a number of mappings needed for a physical block based on the size of a data block and a size of the physical block, the number of mappings being variable for different physical blocks depending on the size of the one or more data blocks storing in the physical block; retrieve a dynamically sized reverse map, the dynamically sized reverse map being a dynamic tree structure; determine a starting location in the dynamically sized reverse map for mappings of the one or more data blocks; and create an entry for the physical block in the dynamically sized reverse map.

Abstract: The invention provides a method and apparatus that addresses and resolves the issues currently affecting the ability to offer Enhanced TV, in particular, those issues concerning timing and synchronization, interaction with other modules in the STB, and distribution.

Abstract: Described are techniques for processing service level objectives. A first service level objective specified for a storage group of devices may include a first value denoting a first target level of performance for I/O operations. A second service level objective specified for a first portion of the storage group may include a second value denoting a second target level of performance for I/O operations directed to the first portion. The second value may denote a higher level of performance than the first value. It may be determined whether there is a violation of any of the first service level objective and the second level objective. Responsive to determining there is the violation of any of the first service level objective and the second level objective, one or more data movements in accordance with the violation may be performed.

Abstract: A data identification system and method for operating the data identification system are provided. The method comprises identifying processing elements contained within the storage environment, identifying virtual processing elements contained within the processing elements, identifying virtual storage elements contained within the virtual processing elements, identifying contents of the virtual storage elements, generating the file system view of the storage environment, wherein the file system view comprises the processing elements, the virtual processing elements, the virtual storage elements, and the contents of the virtual storage elements arranged in a hierarchical order. The file system view of the storage environment is then provided.

Abstract: In a cloud environment, each host computer can have its own security service processor with an independent network interface for communicating with a remote server over a network. The security service processor can provide remote management and security functionalities for various devices connected using different buses on a platform in each host computer. The security service processor can provide a centralized mechanism to verify and authenticate firmware updates for various devices using different buses. A hardware interface can allow the security service processor to provide remote debugging and diagnostic capabilities. The security service processor can also provide some of the typical functionalities of a baseboard management controller or can be used in addition to the baseboard management controller.

Abstract: The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.

Abstract: In one embodiment, a rack enclosure for housing rack-mounted equipment includes a deflection member adapted to a piece of the rack-mounted equipment and an actuator coupled to the deflection member to control a position of the deflection member between a fully closed position and a fully opened position. A variable amount of cooling airflow is to be provided to the equipment piece based on the deflection member position.

Abstract: A method of accessing a persistent memory over a memory interface is disclosed. In one embodiment, the method includes allocating a virtual address range comprising virtual memory pages to be associated with physical pages of a memory buffer and marking each page table entry associated with the virtual address range as not having a corresponding one of the physical pages of the memory buffer. The method further includes generating a page fault when one or more of the virtual memory pages within the virtual address range is accessed and mapping page table entries of the virtual memory pages to the physical pages of the memory buffer. The method further includes transferring data between a physical page of the persistent memory and one of the physical pages of the memory buffer mapped to a corresponding one of the virtual memory pages.

Abstract: Technologies are generally described for methods and systems effective to store data in a memory module. The memory module may include a volatile portion and a non-volatile portion. The methods may comprise receiving, by a processor, a request to store the data. The request may include an indication of a virtual address. The methods may further include determining, by the processor, a persistency of the data based on the virtual address. The methods may further include performing a first operation of identifying a particular portion of the memory module based on the virtual address. The methods may further include generating a command to store the data in the particular portion of the memory module. The methods may further include controlling the operating system to perform a second operation of updating a translation lookaside buffer to indicate the persistency of the data.

Abstract: An RDMA-capable network interface controller provides an RDMA access to a physical memory using multiple mapping tables; the physical memory includes a plurality of physical memory regions, at least some of which are associated with a virtual memory region. A mapping unit is configured to map memory region identifiers, each of which is adapted to identify a virtual memory region and an associated physical memory region, to virtual memory regions and to the associated physical memory regions based on a mapping table selected from multiple mapping tables based on a network identifier. Each of the mapping tables is indexed using a plurality of memory region identifiers, each associated with a virtual memory region and a physical memory region. A processing unit is configured to receive an access request from a client for accessing one of the physical memory regions associated with a virtual memory region.

Abstract: Accessing a hybrid memory using a translation line is disclosed. The hybrid memory comprises a first portion. The translation line maps a first physical memory address to a first line in the first portion. Said mapping provides an indication that the first line is not immediately accessible in the first portion.

Abstract: A computing method includes running, on a plurality of compute nodes, multiple workloads that access respective sets of memory pages. Respective bitmaps are calculated for at least some of the workloads, wherein (i) a bitmap of a workload is statistically indicative of a cardinality of the set of memory pages used by the workload, (ii) a union of two or more bitmaps is statistically indicative of the cardinality of a union of the sets of memory pages used by the two or more corresponding workloads, and (iii) an intersection of first and second bitmaps is statistically indicative of an overlap between respective first and second sets of memory pages used by the corresponding workloads. A decision is made to migrate a selected workload from a source compute node to a destination compute node, based on one or more of the bitmaps.

Abstract: Example devices are disclosed. For example, a device may include a processor, a plurality of translation lookaside buffers, a plurality of switches, and a memory management unit. Each of the translation lookaside buffers may be assigned to a different process of the processor, each of the plurality of switches may include a register for storing a different process identifier, and each of the plurality of switches may be associated with a different one of the translation lookaside buffer buffers. The memory management unit may be for receiving a virtual memory address and a process identifier from the processor and forwarding the process identifier to the plurality of switches. Each of the plurality of switches may be for connecting the memory management unit to a translation associated with the switch when there is a match between the process identifier and the different process identifier stored by the register of the switch.

Abstract: Technologies are generally described for a system and method effective to copy virtual machine images from a source to a destination memory. A processor may copy a first block corresponding to a first virtual machine image from an interim memory to the destination memory. The interim memory may include de-duplicated data present in the first and the second virtual machine images. The processor may identify a second block in the interim memory that corresponds to the second virtual machine image and store the second block in a buffer. The processor may identify a third block in the interim memory that corresponds to the first virtual machine image and copy the third block from the interim memory to the destination memory.

Abstract: For system management applied to a computer system, a power supply of the computer system starts to power a motherboard and a CPU thereon. A reset holding module in a system management controller holds the CPU in a Power-on Reset (PoR) state. The system management controller executes an operation requested by a user. The reset holding module releases the CPU from the PoR state in response to the system management controller completing the operation.

Abstract: A dynamic monitoring process begins with configuring a start and end method to be monitored. The dynamic monitoring process may intercept both the start and end methods as and when the loader is initiated or at runtime to dynamically attach and detach the instrumentation. A loader may then be modified to call a library method upon detection of the start method. The library method may serve as a notification to the start of the method and causes a reflector to retrieve information from the incoming request. The incoming information may include data from which a business transaction name may be determined. The business transaction name is then associated with the monitoring of the particular request. When an exit call is detected, a call may be made to the library for a method which invokes a decorator. The decorator may insert business transaction name and other data into the outgoing call.

Abstract: A method of operating a nonvolatile memory (NVM) is provided which includes calculating an assignment interval between successive assignments of erase blocks to free blocks from among a plurality of memory blocks of the NVM, and adjusting a number of erase blocks of the plurality of memory blocks according to the assignment interval. The erase blocks are memory blocks, having an erased state, from among the plurality of memory blocks, and the free blocks are memory blocks, which are selected to write data, from among the erase blocks.

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract: Transmitting or storing subsegments is disclosed. A data stream or a data block is received and broken into a plurality of segments. For at least one segment, the segment is broken into a plurality of subsegments. A previously stored or transmitted segment similar to the at least one segment is identified. A fingerprint is computed for at least one subsegment. And, using the fingerprint for the at least one subsegment, determining whether the at least one subsegment is identical to a subsegment of the previously stored or transmitted segment without directly comparing the content of the at least one subsegment with the content of the subsegment of the previously stored or transmitted segment.

Abstract: Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

Abstract: According to one embodiment, a memory system includes a non-volatile first memory, a second memory, and a memory controller. The memory controller is configured to store a plurality of translation information in the first memory and perform a first process in a case of starting. The translation information indicates a relation between a first address designated from the outside and a second address indicating a location in the first memory. The first process is a process in which the memory controller acquires the plurality of translation information from the first memory in an order of a storage location of the translation information in the first memory, and stores the plurality of acquired translation information in the second memory.

Abstract: A data processing system includes one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. An accelerator provides a shared resource for a plurality of the applications and has one or more input/output interfaces for the submission of tasks to the accelerator from an application. A hypervisor manages the allocation of the input/output interfaces to the one or more operating systems and a hypervisor interface enables communication between the hypervisor and the accelerator. The system is capable of being configured such that an operating system that has been allocated an input/output interface is capable of communicating with the accelerator via the input/output interface independently of the hypervisor. A memory management unit is capable of providing an isolated region of a memory for use by the operating system while the operating system retains its allocated input/output interface.

Abstract: Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).

Abstract: Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.

Abstract: In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually addressed sub-pages can be mapped to a common memory page. When one bit is allocated for aliasing, dirty bit information can be provided at a granularity that is one-half of a memory page. When M bits are allocated for aliasing, dirty bit information can be provided at a granularity that is 1/(2M)-th of a memory page.

Abstract: Approaches for providing a guest operating system to a virtual machine. A read-only copy of one or more disk volumes, including a boot volume, is created. A copy of a master boot record (MBR) for the one or more disk volumes is also stored. The read-only copy may be, but need not be, made using a Volume Shadow Copy Service (VSS). A virtual disk, for use by the virtual machine, is created based on the read-only copy of the one or more disk volumes and the copy of the master boot record (MBR), wherein the virtual disk comprises the guest operating system used by the virtual machine. In this way, a single installed operating system may provide both the host operating system and the guest operating system.

Abstract: A method of tier management of data comprises performing a tier migration log information setup process which includes selecting an area specified by a virtual volume address and a logical volume address; determining a destination tier for the area based on a number of accesses to the area; and updating a tier migration log information by inputting the determined destination tier and a time; and performing a process using the tier migration log information to determine whether to migrate a specific area which includes loading a tier migration log from the tier migration log information by selecting a specific time; checking if a current tier of the specific area equals a destination tier specified by the tier migration log; and if the current tier is not equal to the destination tier, migrating the specific area to the destination tier.

Abstract: Techniques herein are for sharing data structures between processes. A method involves obtaining a current memory segment that begins at a current base address within a current address space. The current memory segment comprises a directed object graph and a base pointer. The graph comprises object pointers and objects. For each particular object, determine whether a different memory segment contains an equivalent object that is equivalent to the particular object. If the equivalent object exists, for each object pointer having the particular object as its target object, replace the memory address of the object pointer with a memory address of the equivalent object that does not reside in the current memory segment. Otherwise, for each object pointer having the particular object as its target object, increment the memory address of the object pointer by an amount that is a difference between the current base address and the original base address.

Abstract: In a method for SR-IOV Virtual Functions Sharing on Multi-Hosts, implemented in a management system, one or more fake devices are simulated in one or more hosts with each fake device corresponding to one of a plurality of SR-IOV virtual functions. Each of one or more configuration spaces is redirected from each SR-IOV virtual function to each fake device, respectively. Each of configuration space requests is redirected from a corresponding fake device to a corresponding SR-IOV virtual function when the configuration space request is received. And each of memory access operations is redirected from the corresponding SR-IOV virtual function to a mapped memory on a corresponding host with the corresponding fake device, and each of interrupts generated by one or more SR-IOV virtual machines is redirected to the corresponding fake device.

Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include conveying first data from local regions of a local volume of a local storage system to a remote storage system having a remote volume with remote regions in a one-to-one correspondence with the local regions. While conveying the first data, a request is received to update a given local region, and the given local region is marked.

Abstract: To generate a checkpoint for a virtual machine (VM), first, while the VM is still running, a copy-on-write (COW) disk file is created pointing to a parent disk file that the VM is using. Next, the VM is stopped, the VM's memory is marked COW, the device state of the VM is saved to memory, the VM is switched to use the COW disk file, and the VM begins running again for substantially the remainder of the checkpoint generation. Next, the device state that was stored in memory and the unmodified VM memory pages are saved to a checkpoint file. Also, a copy may be made of the parent disk file for retention as part of the checkpoint, or the original parent disk file may be retained as part of the checkpoint. If a copy of the parent disk file was made, then the COW disk file may be committed to the original parent disk file.

Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.

Abstract: A method for treatment of a hypervisor call sequence, in a system having a plurality of hosts, includes assigning a host ID to a plurality of hosts in the system; identifying a first host ID for a host from which a first hypervisor call of a hypervisor call sequence originates; identifying a second host ID for a host from which a second hypervisor call of the hypervisor call sequence originates, wherein the second hypervisor call is a call subsequent to the first hypervisor call; and determining whether the second host ID is equal to the first host ID.

Abstract: A storage control apparatus performs, for each virtual area to which a physical area is allocated, any one of coarse-grained management for managing a correspondence relationship between a virtual area and a physical area in a first size unit, and fine-grained management for managing a correspondence relationship between a virtual area and a physical area in a second size unit smaller than the first size unit. The storage control apparatus manages mapping information that expresses a correspondence relationship between a virtual area and a physical area. The storage control apparatus performs at least one of change of any of fine-grained virtual areas to a coarse-grained virtual area and change of any of coarse-grained virtual areas to a fine-grained virtual area, based on the number of duplication areas of each virtual area and a size of the mapping information.

Abstract: A data processing system comprises one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. The system also comprises an accelerator that provides a shared resource for a plurality of the applications, an input/output module comprising one or more input/output interfaces for the submission of tasks to the accelerator, a hypervisor that manages the allocation of the input/output interfaces to the one or more operating systems and a storage area accessible by the hypervisor and the accelerator. The accelerator is capable of writing one or more selected pieces of information representative of one or more scheduling statistics of the accelerator periodically to the storage area without having received a request for the one or more selected pieces of information from the hypervisor.

Abstract: Provided are an electronic device, an information management program, and an information management method that help reduce the amount of memory for job information. An MFP (electronic device) has a job information generating device which generates, for each job executed by application software, job information including settings used by the application software that executes the job, and an access managing device which manages, when the job is executed, access to the job information from the application software. The job information generating device duplicates general job information including general setting items to generate preliminary job information, accepts, for the job, values for setting items included in the preliminary job information, and then generates the job information such that it includes, out of settings included in the preliminary job information, only settings used by the application software.

Abstract: A technique for providing end-to-end error detection coding between a requesting module and a memory module have been disclosed. A method includes translating a first logical address of a memory request to a physical address. The method includes translating an error control code and data associated with the memory request between a first format and a second format. The error control code and data having the first format is generated based on the first logical address. The error control code and data having the second format is generated based on a second address. The method includes generating an error indicator based on the error control code, the data, and one of the first logical address and the second address.

Abstract: A tagged cache is disclosed for data coherency in multi-domain debug operations. Access requests to a memory within a target device are received for data views associated with debug operations, and access requests include virtual addresses associated with virtual address spaces and client identifiers associated with requesting data views. Virtual addresses are translated to physical addresses within a tagged cache using address translation tables that associate virtual addresses from the different virtual address spaces with client identifiers and with physical addresses within the cache. Data within the cache is cached using the physical addresses. Further, when data is written to the cache, virtual address tags within the cache are used to identify if other virtual addresses are associated with the physical address for the write access request. If so, client identifiers stored within the address translation tables are used to notify affected data views of changed data.

Abstract: A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each instruction references a respective logical register assigned to a respective physical register. The processor also includes logic to reassign a physical register of the second instruction to another logical register before retirement of the first instruction.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable heuristic aware garbage collection in storage systems (e.g., non-volatile data storage systems using one or more flash memory devices). In one aspect, a time parameter (e.g., dwell time) and/or heuristics (e.g., error count, error rate, number of reads, number of times programmed, etc.) are used in a garbage collection scheme. For example, in some implementations, the method of garbage collection for a storage medium in a storage system includes (1) determining a time parameter for a block in the storage medium, and (2) in accordance with a determination that the time parameter for the block is greater than a first threshold time, enabling garbage collection of the block.

Abstract: A data storage system configured to efficiently search and update system data is disclosed. In one embodiment, the data storage system can attempt to correct errors in retrieved data configured to index system data. Metadata stored along with user data in a memory location can be configured to indicate a logical address associated in a logical-to-physical location mapping with a physical address at which user data and metadata are stored. The data storage system can generate modified versions of logical address indicated by the metadata and determine whether such modified versions match the physical address in the logical-to-physical mapping. Modified versions of the logical address can be generated by flipping one or more bits in the logical address indicated by the metadata. Efficiency can do increased and improved performance can be attained.

Abstract: The storage system of the present invention is able to generate one virtual logical device from different logical devices which exist in each of the different storage control units and remote-copy all or part of the virtual logical device to another logical device. The same virtual identifier is set for a volume of the first storage unit and for a volume of the second storage unit. The path control unit of the host identifies a plurality of volumes which have the same virtual identifier as one virtual volume. A remote copy pair can also be set by a virtual volume and a volume of the third storage unit. The setting of the virtual volume and the setting of the remote copy can be performed by means of an instruction from the management server.

Abstract: In several embodiments, a graphics processor couples to a virtual machine monitor (VMM) to present a virtual graphics processor to one or more virtual machines. A mediator for the virtual graphics processor synchronously shadows modifications to a guest graphics translation table (GTT) of a virtual machine to a shadow GTT of the VMM using trap and emulate virtualization. If the mediator detects a frequency of modifications to the guest GTT that exceeds a threshold the mediator may then asynchronously shadow at least a portion of the guest GTT to the shadow GTT and rebuild the shadow GTT prior to submitting commands for the virtual graphics processor to the graphics processor.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: Functionality is described herein for memory-mapping an information unit (such as a file) into virtual memory by associating shared virtual memory resources with the information unit. The functionality then allows processes (or other entities) to interact with the information unit via the shared virtual memory resources, as opposed to duplicating separate private instances of the virtual memory resources for each process that requests access to the information unit. The functionality also uses a single level of address translation to convert virtual addresses to corresponding physical addresses. In one implementation, the information unit is stored on a bulk-erase type block storage device, such as a flash storage device; here, the single level of address translation incorporates any address mappings identified by wear-leveling and/or garbage collection processing, eliminating the need for the storage device to perform separate and independent address mappings.

Abstract: An apparatus includes a storage medium with an opaque key storage and a controller. The controller may be coupled to the storage medium. The controller may be configured to (i) receive from a host device an authentication key, a plurality of I/O requests, and respective virtual media encryption keys associated with a number of the I/O requests, (ii) allow the host device to access the opaque key storage in response to the authentication key received from the host device being authenticated, (iii) generate a first media encryption key for a real band based upon the authentication key from the host device and key material stored on the apparatus, and (iv) generate a number of second media encryption keys for the number of I/O requests based on the first media encryption key and each of the respective virtual media encryption keys associated with each of the number of I/O requests.

Abstract: Embodiments of the invention provide data reduction in storage systems. In one embodiment, a computer comprises: a memory; and a controller operable to manage information, which corresponds to a plurality of addresses, of one or more volumes provided from a storage system to the computer and including at least one set of multiple storage areas sharing same data to be stored in the storage system. The controller is operable to manage storing of the shared same data in the memory of the computer by using the information of the storage areas.

Abstract: Methods, systems, and computer readable media generalize control registers in the context of memory address translations for I/O devices. A method includes maintaining a table including a plurality of concurrently available control register base pointers each associated with a corresponding input/output (I/O) device, associating each control register base pointer with a first translation from a guest virtual address (GVA) to a guest physical address (GPA) and a second translation from the GPA to a system physical address (SPA), and operating the first and second translations concurrently for the plurality of I/O devices.