Abstract: Techniques herein are for sharing data structures between processes. A method involves obtaining a current memory segment that begins at a current base address within a current address space. The current memory segment comprises a directed object graph and a base pointer. The graph comprises object pointers and objects. For each particular object, determine whether a different memory segment contains an equivalent object that is equivalent to the particular object. If the equivalent object exists, for each object pointer having the particular object as its target object, replace the memory address of the object pointer with a memory address of the equivalent object that does not reside in the current memory segment. Otherwise, for each object pointer having the particular object as its target object, increment the memory address of the object pointer by an amount that is a difference between the current base address and the original base address.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: A data storage system includes data storage and random access memory. A sorting module is communicatively coupled to the random access memory and is configured to sort data blocks of incoming write data received in the random access memory. A storage controller is communicatively coupled to the random access memory and the data storage and is configured to write the sorted data blocks as individually-sorted data block sets to a staging area of the data storage. A method and processor-implemented process provide for sorting data blocks of incoming write data received in a random access memory of data storage and writing the sorted data blocks as individually-sorted data block sets to a staging area of the data storage.

Abstract: Techniques are provided for performing OID-to-VMA translations during runtime. Vector registers are used to implement a “software TLB” to perform OID-to-VMA translations. Runtime dereferencing is performed using one or more vector registers to compare each OID that needs to be dereferenced against a set of cached OIDs. When a cached OID matches the OID being dereferenced, the VMA of the cached OID is retrieved from cache. Buffer cache items may be pinned during the period in which the software TLB stores entries for the items. The cache of OID translation information may be single or multi-leveled, and may be partially or completely stored in registers within a processor. When stored in registers, the translation information may be spilled out of the register, and reloaded into the register, as the register is needed for other purposes.

Abstract: A storage management apparatus configured to allocate physical addresses in a physical storage area, to virtual addresses in a virtual storage area for storing data is provided. The storage management apparatus includes a processor that executes a process to define, in the physical area, a continuous area having a plurality of continuous physical addresses, and define, based on a virtual address to which a physical address in the continuous area has initially been allocated, an allocation range of virtual addresses for allocating the defined continuous area; and allocate a physical address in the defined continuous area to a virtual address in the defined relation range.

Abstract: A profile store can include a guest profile. A converter can be in the control domain. The converter can convert a gesture detected on a touch input device to a domain input for the guest domain. The guest profile for the guest domain can be used for the conversion.

Abstract: A first request may be received to update a first set of values. The first set of values may be stored at a first location within a first data page of a database. The first location may be read-only. In response to the receiving of the first request, a first set of records may be inserted into a second data page. The first set of records may include the update of the first set of values. In response to the inserting, a forward pointer may be stored in the first data page that points to the first set of records on the second data page. One or more committed values may be identified on the second data page. In response to the identifying, the one or more committed values may be merged from the second data page to a third data page.

Abstract: Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture.

Abstract: A dynamic monitoring process begins with configuring a start and end method to be monitored. The dynamic monitoring process may intercept both the start and end methods as and when the loader is initiated or at runtime to dynamically attach and detach the instrumentation. A loader may then be modified to call a library method upon detection of the start method. The library method may serve as a notification to the start of the method and causes a reflector to retrieve information from the incoming request. The incoming information may include data from which a business transaction name may be determined. The business transaction name is then associated with the monitoring of the particular request. When an exit call is detected, a call may be made to the library for a method which invokes a decorator. The decorator may insert business transaction name and other data into the outgoing call.

Abstract: Techniques to clone a writeable data object in non-persistent memory are disclosed. The writeable data object is stored in a storage structure in non-persistent memory that corresponds to a portion of a persistent storage. The techniques enable cloning of the writeable data object without having to wait until the writeable data object is saved to the persistent storage and without needing to quiesce incoming operations (e.g., reads and writes) to the writeable data object.

Abstract: Disclosed here are implementations involving an application program that includes an event handling portion. The event handling portion monitors for an event associated with execution of an initial portion of the application program downloaded with the event handling portion that involves an additional portion of the application program not yet downloaded. In response to detecting the event, the execution of the initial portion of the application program is paused by the event handler and downloading of the additional portion is initiated. Upon downloading the additional portion of the application program, execution of the initial portion of the application program can resume.

Abstract: A file processing system includes a system targeting unit to target a distributed file system, a chunk generator to generate a chunk including file blocks and to generate copies of the chunk to be stored in the distributed file system, a data storage medium to store the chunk, and a chunk operation requesting unit to request storage of the generated chunk copies in the distributed file system. A distributed file system includes a first data server and a second data server. Each data server includes a chunk storage unit to store a chunk copy received from a file processing system, and a chunk operation performing unit to generate an identical copy of the stored chunk copy that is undamaged to replace a damaged chunk copy.

Abstract: A method includes outputting for display a first view representing a first plurality of objects stored in a first folder of a hierarchical storage system and receiving one or more selection inputs that designate one or more objects from the plurality of objects as selected objects. The method also includes outputting for display a floating interface element representing the selected objects and receiving a navigation input identifying a second folder of the hierarchical storage system. The method also includes executing, in response to the navigation input, a view transition that removes the first view from display and outputs, for display, a second view representing a second plurality of objects stored in the second folder, wherein the floating interface element representing the selected objects remains displayed during the view transition.

Abstract: The described implementations relate to virtual computing techniques. One implementation provides a technique that can include receiving a request to execute an application. The application can include first application instructions from a guest instruction set architecture. The technique can also include loading an emulator and a guest operating system into an execution context with the application. The emulator can translate the first application instructions into second application instructions from a host instruction set architecture. The technique can also include running the application by executing the second application instructions.

Abstract: A method for sampling management includes establishing, for a multi-core intermediary comprising a plurality of packet evaluation components executing on a corresponding plurality of cores, a frequency at which the multi-core intermediary intercepts a response transmitted from a server to a client and injects data into the intercepted response. For each of the plurality of packet evaluation components, an offset and a frequency based on a number of packet evaluation components in the plurality of packet evaluation components is established, a combination of the established frequencies substantially similar to the frequency established for the multi-core intermediary. One of the plurality of cores intercepts a response from the server to the client, at a time specified by the frequency and the offset. The packet evaluation component executing on the one of the plurality of cores injects data into the intercepted response.

Abstract: A memory system including a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing metadata. A compare circuit is configured to receive metadata retrieved from a plurality of pages sequentially and compare the retrieved metadata to a search pattern. The physical location of the page can be determined by finding the search pattern. The memory array and the compare circuit are formed in different layers of the substrate.

Abstract: A memory system or flash memory device may include identify a bit error rate (BER) mapping for the memory. The BER mapping may be used for identifying erroneous bits, managing them, and using them for the system maintenance and system recovery. A complete BER map may be stored in main memory while a cached version of the BER map may be stored in random access memory (RAM). The cached version may identify only the top and bottom bits rather than the complete map. The cached BER map may be updated based on future reads and future programming may rely on the cached BER map for selecting blocks to program.

Abstract: Methods may provide a virtual system with direct access to one or more sectors of a resource of a computer system. The method may include providing, by a computer system to a virtual system, first access control data associated with a regular computer file that corresponds to a resource on the computer system. The method may additionally include receiving, at the computer system, a direct read from or direct write to one or more sectors of the resource represented by the regular computer file from the virtual system. The method may further include hiding, at the computer system, a hidden computer file from the virtual system. The method may additionally include routing, at the computer system, the direct read from or direct write to the hidden computer file on the computer system.

Abstract: Embodiments of the present invention provide a method and an apparatus for constructing a memory access model, and relate to the field of computers. The method includes: obtaining a page table corresponding to a process referencing a memory block, and clearing a Present bit included in each page table entry stored in the page table; and constructing a memory access model of the memory block according to the number of access times of each page in the memory block and time obtained through timing, where the memory access model at least includes the number of access times and an access frequency of each page in the memory block. The apparatus includes: a first obtaining module, a first monitoring module, a first increasing module, and a second obtaining module. The present invention can reduce the memory consumption and an impact on the system performance, and avoid a system breakdown.

Abstract: A system with a prefetch address generator coupled to a system translation look-aside buffer that comprises a translation cache. Prefetch requests are sent for page address translations for predicted future normal requests. Prefetch requests are filtered to only be issued for address translations that are unlikely to be in the translation cache. Pending prefetch requests are limited to a configurable or programmable number. Such a system is simulated from a hardware description language representation.

Abstract: Provided are an apparatus and method for providing services using a virtual operating system (OS). The apparatus classifies virtual resources into a plurality of mutually exclusive regions and manages the virtual resources based on the provides services regions. The plurality of provides services regions include a virtual region whose resources are stored in and used on an external storage, and an overlay region whose resources refer to host resources. The apparatus uses the region information for virtual resources and a list of resources accessed for each application process to manage the virtual resources.

Abstract: Systems and computer program products may provide a virtual system with direct access to one or more sectors of a resource of a computer system. The system and computer program products may include providing, by a computer system to a virtual system, first access control data associated with a regular computer file that corresponds to a resource on the computer system. The system and computer program products may additionally include receiving, at the computer system, a direct read from or direct write to one or more sectors of the resource represented by the regular computer file from the virtual system. The system and computer program products may further include hiding, at the computer system, a hidden computer file from the virtual system. The system and computer program products may additionally include routing, at the computer system, the direct read from or direct write to the hidden computer file on the computer system.

Abstract: A method for identifying code segments and associated software developers in a software development environment is disclosed. A software development tool detects a memory error in a first code segment. The software development tool associates the memory error with a first software developer that is associated with the first code segment. The software development tool identifies a second code segment related to the first code segment. The software development tool associates the memory error with a second software developer that is associated with the second code segment.

Abstract: Central processing units (CPUs) in computing systems manage graphics processing units (GPUs), network processors, security co-processors, and other data heavy devices as buffered peripherals using device drivers. Unfortunately, as a result of large and latency-sensitive data transfers between CPUs and these external devices, and memory partitioned into kernel-access and user-access spaces, these schemes to manage peripherals may introduce latency and memory use inefficiencies. Proposed are schemes to reduce latency and redundant memory copies using virtual to physical page remapping while maintaining user/kernel level access abstractions.

Abstract: One embodiment of the present invention sets forth a computer-implemented method for altering migration rules for a unified virtual memory system. The method includes detecting that a migration rule trigger has been satisfied. The method also includes identifying a migration rule action that is associated with the migration rule trigger. The method further includes executing the migration rule action. Other embodiments of the present invention include a computer-readable medium, a computing device, and a unified virtual memory subsystem. One advantage of the disclosed approach is that various settings of the unified virtual memory system may be modified during program execution. This ability to alter the settings allows for an application to vary the manner in which memory pages are migrated and otherwise manipulated, which provides the application the ability to optimize the unified virtual memory system for efficient execution.

Abstract: A new approach is proposed virtual machines (VMs) accessing remote storage devices over a network via non-volatile memory express (NVMe) controllers to migrate live from a current host to a destination host. A first virtual NVMe controller running on a first physical NVMe controller enables a first VM running on the current host to perform storage operations to logical volumes mapped to the remote storage devices over the network as if they were local storage volumes. During VM migration, the current host puts the first virtual NVMe controller into quiesce state and saves an image of its states. A second virtual NVMe controller is created on a second physical NVMe controller using the saved image, which is configured to serve a second VM on the destination host. The second virtual NVMe controller resumes the storage operations to the remote storage devices without being interrupted by the VM migration.

Abstract: A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual guest devices or virtual machines (VMs). The lightweight SATA virtualization handler can also perform the scheduling or queuing of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the coprocessor and has commands from one or more VMs. Guest devices or guest operating systems can build associated AHCI data structures in memory, which may be on-chip memory or DDR memory.

Abstract: A method for identifying code segments and associated software developers in a software development environment is disclosed. A software development tool detects a memory error in a first code segment. The software development tool associates the memory error with a first software developer that is associated with the first code segment. The software development tool identifies a second code segment related to the first code segment. The software development tool associates the memory error with a second software developer that is associated with the second code segment.

Abstract: In one embodiment, a method includes creating a first working set of shadow page table hierarchies for a first processor of a plurality of processors, creating a second working set of shadow page table hierarchies for a second processor of the plurality of processors, keeping a record of modified guest page tables, and synchronizing each modified guest page table with a corresponding shadow page table in the first working set. For each modified guest page table in the modified guest page tables record, an entry includes an indication of which of the plurality of processors have a hardware translation lookaside buffer containing a writable reference to the modified guest page table.

Abstract: Examples disclosed herein provide systems, methods, and software to handoff virtual machines between hypervisors. In one implementation, a method of transitioning a virtual machine from a first hypervisor to a second hypervisor includes identifying a request to transition the virtual machine from the first hypervisor to the second hypervisor. The method further provides determining security trust requirements for the virtual machine, and exchanging trust information between the first hypervisor and the second hypervisor. The method further provides determining if the second hypervisor can support the virtual machine based on the security trust requirements and the trust information, and transitioning the device to the second hypervisor if the second hypervisor can support the virtual machine.

Abstract: Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from corresponding to a first physical address to a second physical address and determining if all stores occupying a store queue before the remapping have been retired from the store queue. Loads that are younger than the stores that occupied the store queue before the remapping are prevented from being dispatched and executed until the stores that occupied the store queue before the remapping have left the store queue and become globally visible.

Abstract: According to one or more embodiments of the present invention, a network cache intercepts data requested by a client from a remote server interconnected with the cache through one or more wide area network (WAN) links (e.g., for Wide Area File Services, or “WAFS”). The network cache stores the data and sends the data to the client. The cache may then intercept a first write request for the data from the client to the remote server, and determine one or more portions of the data in the write request that changed from the data stored at the cache (e.g., according to one or more hashes created based on the data). The network cache then sends a second write request for only the changed portions of the data to the remote server.

Abstract: One embodiment of the present invention provides a system. The system includes a high availability module and a data transformation module. During operation, the high availability module identifies a modified object belonging to an application in a second system. A modification to the modified object is associated with a transaction identifier. The high availability module also identifies a local object corresponding to the modified object associated with a standby application corresponding to the application in the second system. The data transformation module automatically transforms the value of the modified object to a value assignable to the local object, including pointer conversion to point to equivalent object of the second system. The high availability module updates the current value of the local object with the transformed value.

Abstract: In a method to zone data to a virtual machine, support information is exchanged between a physical controller and an expander, the support information comprising an indication of an ability of the physical controller and the expander to support thereon a set of virtual controllers and a set of virtual physical layers (virtual PHYs), respectively. In response to a positive indication sending a list of SAS addresses to the expander, a list of SAS addresses is sent to the expander. Then, a first SAS address of the list of SAS addresses is assigned to a first virtual PHY of the set of virtual PHYs, wherein the assigning is performed by the expander, and wherein the first virtual PHY at an assigned SAS address corresponds to a first virtual controller of the set of virtual controllers.

Abstract: In a cloud computing environment, a cache and a memory are partitioned into “colors”. The colors of the cache and the memory are allocated to virtual machines independently of one another. In order to provide cache isolation while allocating the memory and cache in different proportions, some of the colors of the memory are allocated to a virtual machine, but the virtual machine is not permitted to directly access these colors. Instead, when a request is received from the virtual machine for a memory page in one of the non-accessible colors, a hypervisor swaps the requested memory page with a memory page with a color that the virtual machine is permitted to access. The virtual machine is then permitted to access the requested memory page at the new color location.

Abstract: A method for using a partitioned flash transition layer is disclosed. Step (A) receives, at an apparatus from a host, a write command having first write data. Step (B) generates second write data by compressing the first write data in the apparatus. The second write data generally has a variable size. Step (C) stores the second write data at a physical location in a nonvolatile memory. The physical location is a next unwritten location. Step (D) returns, from the apparatus to the host in response to the write command, an indication of the physical location.

Abstract: A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item.

Abstract: A computer comprising: a processor; a memory; and an I/O device, the memory including at least one first memory element and at least one second memory element, wherein a memory area provided by the at least one second memory element includes a data storage area and a data compression area, wherein the computer comprises a virtualization management unit, and wherein the virtualization management unit is configured to: set a working set for storing data required for processing performed by a virtual machine in generating the virtual machine, and control data stored in the working set in such a manner that part of the data stored in the working set is stored in the data compression area based on a state of accesses to the data stored in the working set.

Abstract: A microarchitecture can be configured to allow a thread's speculative state to be stored when the thread is preempted. The stored speculative state can then be loaded back into the microarchitecture when the thread is resumed to thereby enable the thread to resume execution at the speculative state that existed when the thread was preempted. By maintaining the speculative state of threads, a greater amount of parallel processing is achieved.

Abstract: A storage controller configures a plurality of storage tiers. A sub-unit of a storage unit is maintained in a selected storage tier of the plurality of storage tiers, for at least a predetermined duration of time subsequent to an input/output (I/O) request for the sub-unit.

Abstract: A processing apparatus supports execution of executable computer program code, wherein non-instruction data is read from and written to a first address space, while executable instructions are fetched from a second address space. Preferably, the processing apparatus supports execution of a modified or enhanced computer program. The programs and user interfaces in the first address space see only the unmodified first program in the first address space and cannot detect the modified or enhanced program in the second address space.

Abstract: A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.

Abstract: A system and method for adjusting space allocated for different page sizes on a recording medium includes dividing the recording medium into multiple blocks such that a block size of the multiple blocks supports a largest page size, and such that each of the multiple blocks is used for a single page size, and assigning an incoming page to a block based on a temperature of the incoming page.

Abstract: Methods, systems, and computer readable storage medium embodiments for configuring a lookup table, such as an access control list (ACL) for a network device are disclosed. Aspects of these embodiments include storing a plurality of data entries in a memory, each of the stored plurality of data entries including a header part and a body part, and encoding each of a plurality of bit-sequences in the header part of a stored data entry from the plurality of data entries to indicate a bit comparing action associated with a respective bit sequence in the body part of the stored data entry. Other embodiments include searching a lookup table in a network device.

Abstract: A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.

Abstract: Aspects of a method and system for an operating system (OS) virtualization-aware network interface card (NIC) are provided. A NIC may provide direct I/O capabilities for each of a plurality of concurrent guest operating systems (GOSs) in a host system. The NIC may comprise a GOS queue for each of the GOSs, where each GOS queue may comprise a transmit (TX) queue, a receive (RX) queue, and an event queue. The NIC may communicate data with a GOS via a corresponding TX queue and RX queue. The NIC may notify a GOS of events such as down link, up link, packet transmission, and packet reception via the corresponding event queue. The NIC may also support unicast, broadcast, and/or multicast communication between GOSs. The NIC may also validate a buffered address when the address corresponds to one of the GOSs operating in the host system.

Abstract: A computer system includes a translation look-aside (TLB) buffer and a processing unit. The TLB is configured to store an entry that comprises virtual address information, real address information associated with the virtual address information, and additional information corresponding to at least one of the virtual address information and the real address information. The processing unit is configured to control the TLB to modify the additional information while maintaining the entry in a valid state accessible by the processing unit for a translation look-aside operation corresponding to the virtual address information and the real address information.

Abstract: The various implementations described herein include systems, methods and devices used to protect data in a storage device. In one aspect, a method includes, performing a soft power fail operation on a section of the device, the operation including: (1) signaling a power test condition to a first controller on the storage device; (2) providing one or more controllers with power from an energy storage device, where the energy storage device is distinct from a power supply used during normal operation; (3) signaling a power fail condition to the one or more controllers on the storage device, where the one or more controllers communicate with the first controller and correspond to said section of the storage device, and where, in response to the power fail condition, each of the one or more controllers performs a data hardening operation; and (4) resuming normal operation on said section of the storage device.

Abstract: A storage layer presents logical address space of a non-volatile storage device. The storage layer maintains logical interfaces to the non-volatile storage device, which may include arbitrary, any-to-any mappings between logical identifiers and storage resources. Data may be stored on the non-volatile storage device in a contextual format, which includes persistent metadata that defines the logical interface of the data. The storage layer may modify the logical interface of data that is stored in the contextual format. The modified logical interface may be inconsistent with the existing contextual format of the data on the non-volatile storage media. The storage layer may provide access to the data in the inconsistent contextual format through the modified logical interface. The contextual format of the data may be updated to be consistent with the modified logical interface in a write out-of-place storage operation.