Abstract: Memory resource partitioning code allocates a memory partition in response to a process requesting access to memory storage. Memory partition rules may define attributes of the memory partition. The attributes may include a minimum memory allocation and a maximum memory allocation for the memory partition.

Abstract: Disclosed is an apparatus for processing a remote page fault included in an optional local node within a cluster system configuring a large integration memory (CVM) by integrating individual memories of a plurality of nodes. The apparatus includes a memory including a CVM-map, a node memory information table, a virtual memory area, and a CVM page table, and a main controller mapping the large integration memory to an address space of a process when a user process requests memory allocation.

Abstract: A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-blocks, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical blocks during programming and data modification operations.

Abstract: An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

Abstract: A system and associated methods are disclosed for allocating memory in a system providing translation of virtual memory addresses to physical memory addresses in a parallel computing system using memory striping. One method comprises: receiving a request for memory allocation, identifying an available virtually-contiguous physically-non-contiguous memory region (VCPNCMR) of at least the requested size, where the VCPNCMR is arranged such that physical memory addresses for the VCPNCMR may be derived from a corresponding virtual memory addresses by shifting a contiguous set of bits of the virtual memory address in accordance with information in a matching row of a virtual memory address matching table, and combining the shifted bits with high-order physical memory address bits also associated with the determined matching row and with low-order bits of the virtual memory address, and providing to the requesting process a starting address of the identified VCPNCMR.

Abstract: Virtual storage pool creation is simplified by allowing a user to specify what devices to include in virtual storage pool by physical location. The virtual storage pool may be automatically generated based on the simplified user specifications. The user may specify the virtual pool configuration in a configuration file. A configuration application generates the virtual storage pool based on the configuration file. The configuration application utilizes the physical locations of block devices contained in the configuration file to generate the pool. As a result, virtual pool configuration and creation is automated, more efficient and is less error prone than previous methods that involve manually linking between physical device locations and computer generated names.

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract: A method of updating mapping information for a memory system comprises generating write transaction information based on multiple write requests issued by a host, performing program operations in the memory system based on the write transaction information, and following completion of the program operations, updating mapping information based on an order in which the write requests were issued by the host.

Abstract: A translation system can translate a storage request having multiple fields to a physical address using the fields as keys to traverse a map. The map can be made of nodes that include one or more node entries. The node entries can be stored in a hashed storage area or sorted storage area of a node. A hashed storage area can enable a quick lookup of densely addressed information by using a portion of the key to determine a location of a node entry. A sorted storage area can enable compact storage of sparse information by storing node entries that currently exist and allowing the entries to be searched. By offering both types of storage in a node, a node can be optimized for both dense and sparse information. A node entry can include a link to a next node or the physical address for the storage request.

Abstract: Techniques are disclosed relating to storing translations in memory that are usable to access data on a recording medium. In one embodiment, a request is sent for a memory allocation within a non-pageable portion of a memory in a computer system. Responsive to the request, allocated memory is received. Translations usable to map logical addresses to physical addresses within a storage device are stored within the allocated memory. In some embodiments, the translations are usable to access an area within the storage device used to store pages evicted from the memory. In one embodiment, a size of the memory allocation is determined based on a size of the area. In another embodiment, a size of the memory allocation is determined based on a size of a partition including the area. In some embodiments, the storage device is a solid-state storage array.

Abstract: A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.

Abstract: A nonvolatile memory device comprises an interface configured to receive write data and a logical address of the write data, a data storage device comprising multiple physical blocks and configured to store an address mapping table array, and a controller configured to selectively load at least one address mapping table from the address mapping table array based on the logical address. The controller performs a deduplication operation for the write data by comparing the write data with data stored in a physical block having a physical address in the loaded address mapping table, to the exclusion of data stored in other physical blocks.

Abstract: A translation system can translate a storage request to a physical address using fields as keys to traverse a map of nodes with node entries. A node entry can include a link to a next node or a physical address. Using a portion of the key as noted in node metadata, a node entry can be determined. When adding node entries to a node, a node utilization can exceed a threshold value. A new node can be created such that node entries are split between the original and new node. Node metadata of the parent node, new node and original node can be revised to identify which parts of the key are used to identify a node entry. When removing node entries from a node, node utilization can cross a minimum threshold value. Node entries from the node can be merged with a sibling, or the map can be rebalanced.

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract: One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved.

Abstract: An apparatus includes a processor and a virtual address transformation unit coupled with the processor. The virtual address transformation unit includes a register. The virtual address transformation unit is configured to receive an indication of a virtual address and read, from the register, a current page size of a plurality of available page sizes. The virtual address transformation unit is also configured to determine a shift amount based, at least in part, on the current page size and perform a bit shift of the virtual address, wherein the virtual address is bit shifted by, at least, the determined shift amount.

Abstract: A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.

Abstract: An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists.

Abstract: The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.

Abstract: A flash memory controller, a computer readable medium and a method for writing to a flash memory device, the method may include receiving multiple logical pages, each logical page having a logical address; determining to write a logical page into a selected physical page of the flash memory device; calculating a hash value for each logical page of the multiple logical pages in response to (a) a logical address of the logical page and (b) a physical page index, to provide multiple hash values of the multiple logical pages.

Abstract: Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address.

Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

Abstract: A data processing system that includes a host system and an external data storage device with an erase before write memory device thereon can be operated by sending a file delete command from the host to the data storage device for one or more files stored thereon. The file delete command may specify a logical address and data to be invalidated associated with the deleted file. The data storage device may identify one or more units of memory allocation in the erase before write memory as containing invalid data based on the specified logical address and data to be invalidated. The data storage device may maintain a data structure that associates physical addresses for units of memory allocation in the erase before write memory with indications of whether the units of memory allocation contain invalid data. The data structure may be used to mark units of memory allocation associated with deleted files as containing invalid data.

Abstract: A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit.

Abstract: A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

Abstract: A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry.

Abstract: Particular embodiments described herein can offer an electronic fabric for a processing system that includes a fabric adapter to couple to a first fabric associated with a first system and to couple to a second fabric associated with a second system. The fabric adapter is configured to pass bidirectional communications between the first system and the second system. The electronic fabric can further include an address translation agent configured to map a first physical address in a first address space of the first system to a second physical address in a second address space of the second system.

Abstract: A technique for “zero copy” transitive communication of data between virtual address domains maintains a translation table hierarchy for each domain. The hierarchy of each domain includes a portion corresponding to every other domain in the system, where the portion for any particular domain begins at the same offset in the virtual address space of every domain. For each domain, there is a source hierarchy used only by the domain itself, which provides read/write access to the addresses in that domain; and a target hierarchy which provides read-only access to that domain, for use only when another domain is the target of IDC from that domain. Only one instance of the target hierarchy of each domain is provided, for all other domains as targets of IDC from that domain. For further space savings the source and target translation table hierarchies can be combined at all but the top hierarchy level.

Abstract: The present disclosure includes systems and techniques relating to non-volatile memory. A described system, for example, includes a non-volatile memory structure having a plurality of multi-level memory cells, a processing device, and a controller. The controller is configured to map a first portion of a first set of consecutive bits of a data segment to a first page associated with the plurality of multi-level memory cells, and map a second portion of the first set of consecutive bits of the data segment to a second page associated with the plurality of multi-level memory cells. The first page is associated with bits of a first significance, and the second page is associated with bits of a second significance.

Abstract: Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address.

Abstract: A method for optimized address pre-translation for a host channel adapter (HCA) static memory structure is disclosed. The method involves determining whether the HCA static memory structure spans a contiguous block of physical address space, when the HCA static memory structure spans the contiguous block of physical address space, requesting a translation from a guest physical address (GPA) to a machine physical address (MPA) of the HCA static memory structure, storing a received MPA corresponding to the HCA static memory structure in an address control and status register (CSR) associated with the HCA static memory structure, marking the received MPA stored in the address CSR as a pre-translated address, and using the pre-translated MPA stored in the address CSR when a request to access the static memory structure is received.

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, where the vector comprises data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations. The one or more actions comprise modifying the data values representing information for a packet. The block also comprises at least one stateful memory comprising stateful memory data values. The one or more actions includes various stateful actions for reading stateful memory, modifying data values representing information for a packet, as a function of the stateful memory data values; and storing modified stateful memory data value back into the stateful memory.

Abstract: A method for accessing a flash memory, the method includes: receiving a read request that is associated with a logical address that is mapped to a physical address of a set of flash memory cells; accessing multiple mapping data structures of different granularity to obtain the physical address of the set of flash memory cells; wherein during at least one point in time at least one mapping data structure is stored in an erase block and wherein the erase block comprises multiple physical pages that are written in a sequential manner and are associated with logical page addresses that are assigned in a random manner; and reading a content of the set of flash memory cells.

Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.

Abstract: A memory controller includes a reading/writing control unit for controlling writing and reading of data to and from a physical block of a nonvolatile memory, a writing mode table for storing one of a first writing mode of protecting data against a power shutdown during writing and a second writing mode of writing data at a higher speed than the first writing mode, and a setting unit for setting the writing mode received from an access device in a writing mode table. The reading/writing control unit performs data writing based on the writing mode that has been set in the writing mode table.

Abstract: According to an example, in a method for preventing data loss during reboot, a logical storage resource management device may pre-allocate reserved memory for storing a storage resource mapping table, allocate logical storage resources to a data source device before a system is rebooted, record, in the storage resource mapping table, a physical location of the logical storage resources into which data has been written when the data source device writes the data into the logical storage resources, obtain the physical location of the logical storage resources into which the data has been written from the storage resource mapping table when the system is rebooted, set a state of a physical memory block corresponding to the logical storage resources into which the data has been written as used, and release all logical storage resources after the data source device reads the data.

Abstract: Some embodiments provide a network virtualizer for managing several managed switching elements that forward data in a network. The virtualizer includes an interface for receiving input logical forwarding plane data. It also includes a converter for converting the input logical forwarding plane data to output physical control plane data. In some embodiments, the physical control plane data is translation into physical forwarding plane data that direct the forwarding of data by the managed switching elements.

Abstract: Some embodiments provide a network virtualization apparatus for managing a plurality of managed switching elements that forward data in a network. The network virtualization apparatus comprises a controller for converting logical control plane data to logical forwarding plane data. It also includes a virtualizer for converting the logical forwarding plane data to physical control plane data. In some embodiments, the physical control plane data is subsequently translated into physical forwarding plane data that direct the forwarding of data by the managed switching elements.

Abstract: Methods and apparatus for control of On-Die System Fabric (OSF) blocks are described. In one embodiment, a shadow address corresponding to a physical address may be stored in response to a user-level request and a logic circuitry (e.g., present in an OSF) may determine the physical address from the shadow address. Other embodiments are also disclosed.

Abstract: In one embodiment, the present invention includes a translation lookaside buffer (TLB) to store entries each having a translation portion to store a virtual address (VA)-to-physical address (PA) translation and a second portion to store bits for a memory page associated with the VA-to-PA translation, where the bits indicate attributes of information in the memory page. Other embodiments are described and claimed.

Abstract: Methods and apparatuses for managing unusable blocks in a memory module are provided. The memory table may include a plurality of unusable block addresses in the memory module where the plurality of unusable block addresses is arranged in a sequential order in the memory table. A number of unusable blocks in the memory module is identified by reading a word that represents the number of unusable blocks from the memory table. A first pair of addresses comprises a first unusable block address and a first corresponding mapped memory address. The pair of addresses are read from the memory table and stored in a storage element of a controller. Only a single pair of addresses is stored in the storage element of the controller at any one time according to one embodiment.

Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.

Abstract: The disclosure is directed to a system and method for accessing one or more values of a lookup table. In some embodiments, one or more read only memory devices are configured for storing a first plurality of values of the lookup table, and one or more combinational logic circuits are configured for accessing a second plurality of values of the lookup table. At least one of hardware area and timing pressures are mitigated through various storage and access schemes.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Techniques are described herein that can be used to process inbound network protocol units. In some implementations, the techniques may process inbound DDP segments. In some implementations, a steering tag of an inbound network protocol unit may be used to access a context accessible to a network component. In some implementations, the context may include an array useful to determine whether all segments in a group have been received by the network component. In some implementations, the segments may be stored in a first buffer and transferred to a second buffer after all segments in a group have been received.

Abstract: Memory address translation circuitry 14 performs a top down page table walk operation to translate a virtual memory address VA to a physical memory address PA using translation data stored in a hierarchy of translation tables 28, 32, 36, 38, 40, 42. A page size variable S is used to control the memory address translation circuitry 14 to operate with different sizes S of pages of physical memory addresses, pages of virtual memory address and translation tables. These different sizes may be all 4 kBs or all 64 kBs. The system may support multiple virtual machine execution environments. These virtual machine execution environments can independently set their own page size variable as can the page size of an associated hypervisor 62.

Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.

Abstract: A system and method for maintaining a mapping table in a data storage subsystem. A data storage subsystem supports multiple mapping tables including a plurality of entries. Each of the entries comprise a tuple including a key. A data storage controller is configured to encode each tuple in the mapping table using a variable length encoding. Additionally, the mapping table may be organized as a plurality of time ordered levels, with each level including one or more mapping table entries. Further, a particular encoding of a plurality of encodings for a given tuple may be selected based at least in part on a size of the given tuple as unencoded, a size of the given tuple as encoded, and a time to encode the given tuple.

Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.

Abstract: Storage address space to NVM address, span, and length mapping/converting is performed by a controller for a solid-state storage system that includes a mapping function to convert a logical block address from a host to an address of a smallest read unit of the NVM. The mapping function provides span and length information corresponding to the logical block address. The span information specifies a number of contiguous smallest read units to read to provide data (corresponding to the logical block address) to the host. The length information specifies how much of the contiguous smallest read units relate to the data provided to the host. The converted address and the length information are usable to improve recycling of no longer needed (e.g. released) portions of the NVM, and usable to facilitate recovery from outages and/or unintended interruptions of service.