Abstract: The subject matter disclosed herein provides methods for materializing data from an in-memory array to one or more pages. An in-memory array holding a column of data can be maintained. One or more pages can be maintained. Each of the one or more pages can have one or more rows for storing the column of data. At least one of the one or more pages can be marked for materialization. The column of data can be materialized by copying the data from the in-memory array to the one or more rows of the one or more pages. The materializing can be based on the marking. Related apparatus, systems, techniques, and articles are also described.

Abstract: Memory management includes maintaining a plurality of physical pages corresponding to a respective plurality of indirect lines, where each of the plurality of indirect lines corresponds to a set of one or more data lines. Memory management further includes receiving a request to create a new physical page; determining whether there is an existing physical page that has matching content to the new physical page; and in the event that there is an existing physical page that has matching content as the new physical page, associating the new physical page with the same data lines as those corresponding to the matching content referenced by the indirect line associated with the existing physical page.

Abstract: A method, system, and computer program product are provided for utilizing target of opportunity to perform at least one special operation while a key session is opened with a key manager for another purpose. The method of recognizing a target of opportunity includes receiving a command to be performed on a removable storage medium and determining if the command requires interaction with the encryption key manager. If it is determined that the command requires interaction with the key manager the command is held off. A request is sent to the encryption key manager. A target of opportunity is recognized by determining if at least one special operation may be performed. If it is determined that at least one special operation may be performed then the at least one special operation and the request are performed.

Abstract: Address remapping technologies are described. A method can include receiving, at a paging device of a system memory, a first physical address of an input/output (IO) device from a sub-page translator, where a sub-page location indicator may be associated with the first physical address. The method can further include identifying a virtual address in a sub-page translation table based on the physical address when the sub-page location indicator may be set to a sub-page lookup mode. The method can further include determining when to look-up the physical address in a sub-page translation table based on the sub-page location indicator. The method can further include communicating, to a virtual machine, the virtual address.

Abstract: A system and method for deterring malicious network attacks. The system and method is configured to execute instructions on at least one of the processors to generate a plurality of random blocks of data; generate a first XOR result by using the XOR function with the plurality of random blocks of data as the XOR function inputs; generate a tail value by using the XOR function with the first XOR result and a random encryption key as the XOR function inputs; encrypt a designated file using the random encryption key; write the plurality of random blocks and tail value to at least one storage medium; and write the encrypted designated file to at least one storage medium.

Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.

Abstract: A method is used in managing file system checking in file systems. Metadata of a file system is evaluated upon receiving a request to perform file system checking on the file system. Based on the evaluation, determination is made as to whether file system checking has been performed previously on the file system. Based on the determination, file system checking is performed on the file system.

Abstract: Systems and methods for scanning signatures in a string field. In one implementation, the invention provides a method for signature scanning. The method includes receiving a particular string field, scanning the particular string field for a plurality of signatures using a larger scan step size, scanning the particular string field for the remaining signatures that are shorter than what can be scanned by the larger scan step size separately either using the same scanning method but a smaller scan step size or using a different scan method and the same or a smaller scan step size, and outputting any identified signatures in the particular string field.

Abstract: The invention concerns a method of exchanging information items, e.g. HTTP headers, between a server device and a plurality of clients, and also concerns such a server device. The server device establishes connections with clients, wherein each connection involves a server-initiated indexing table for the server device to encode information items to be sent over the connection in the server-to-client direction. The method comprises the following steps performed at the server device: obtaining a same single indexing table as the server-initiated indexing table of the connections; in response to receiving a request for data from a client, pushing entries of the table to the client to configure the latter for item exchange in the server-to-client direction, encoding information items associated with the requested data using item indexing based on the table and sending the encoded information items to the client over the connection established with it.

Abstract: Embodiments relate to an enhancement of a function measurement block. An aspect includes obtaining common statistics from a function table. An aspect includes obtaining adapter-specific statistics from an adapter. An aspect includes providing the common statistics and the adapter-specific statistics in the function measurement block. An aspect includes providing adapter-specific counters in the function measurement block.

Abstract: Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a processor maintains a page directory and a page table within a system memory that contain information for translating virtual addresses to physical addresses. Virus processing of a content object is offloaded to a hardware accelerator coupled to the processor by storing scanning parameters, including the content object and a type of the content object, to the memory using one or more virtual addresses and indicating to the hardware accelerator that the content object is available for processing. Responsive thereto, the hardware accelerator: (i) translates the virtual addresses to corresponding physical addresses based on the page directory and the page table; (ii) accesses the scanning parameters based on the physical addresses; (iii) scans the content object for viruses by applying multiple virus signatures; and (iv) returns a result of the scanning to the processor.

Abstract: A multi-boundary address protection range is provided to prevent key operations from interfering with a data move performed by a dynamic memory relocation (DMR) move operation. Any key operation address that is within the move boundary address range gets rejected back to the hypervisor. Further, logic exists across a set of parallel slices to synchronize the DMR move operation as it crosses a protected boundary address range.

Abstract: A page compression strategy classifies uncompressed pages selected for compression. Similarly classified pages are compressed and bound into a single logical page. For logical pages having pages with more than one classification, a weighting factor is determined for the logical page.

Abstract: A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.

Abstract: A storage module may include a controller that is configured to perform a read operation to read data stored in at least one memory, where the data is associated with logical address information. In order to perform the read operation, the controller may be configured to retrieve a preliminary physical address associated with the logical address information, and initiate a data retrieval process for a first version of the data stored at the preliminary physical address prior to confirming a final physical address associated with the logical address information.

Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.

Abstract: Embodiments of apparatuses, methods, and systems for providing multiple virtual device controllers by redirecting an interrupt from a physical device controller are disclosed. In one embodiment, an apparatus includes a processor, a physical device controller, and virtualization logic. The virtualization logic is to receive a first interrupt from the physical device controller, and in response, send a second interrupt to the processor from one of a plurality of virtual device controllers.

Abstract: A device identifies, based on a program code instruction, an attempted write access operation to a fenced memory slab, where the fenced memory slab includes an alternating sequence of data buffers and guard buffers. The device assigns read-only protection to the fenced slab and invokes, based on the attempted write access operation, a page fault operation. When a faulting address of the attempted write operation is not an address for one of the multiple data buffers, the device performs a panic routine. When the faulting address of the attempted write operation is an address for one of the multiple data buffers, the device removes the read-only protection for the fenced slab and performs a single step processing routine for the program code instruction.

Abstract: In a wireless mobile communication system, user equipment receives downlink data and downlink control information including resource allocation information for the downlink data from a base station. Downlink data is mapped to physical resource blocks (PRBs) based on the downlink control information. The resource allocation information indicates virtual resource block (VRB) allocations for the user equipment. Indexes of PRBs to which the downlink data are mapped are determined based on mapping relationship between VRBs and the PRBs. The mapping relationship is defined such that indexes of the VRBs are mapped to indexes of the PRBs for a first part and a second part of a subframe.

Abstract: The present invention provides a method and apparatus for data swap in a virtual machine environment. The present invention provides a method for data swap in a virtual machine environment, including: in response to a swap request from a virtual machine, looking up storage space associated with the swap request; and allocating to the virtual machine free physical storage space, in a host, which matches the storage space, so that the free physical storage space logically becomes available storage space to the virtual machine; the virtual machine is running on the host, and the storage space is physical storage space in the host.

Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.

Abstract: A method includes running in a computer a hypervisor that allocates physical memory pages of the computer to a Virtual Machine (VM). A guest Operating System (OS), a virtual memory and a virtual storage device run in the VM. The guest OS maps the allocated physical memory pages to respective virtual memory pages, retains virtual memory pages that are frequently-accessed by the VM in the virtual memory, and swaps-out virtual memory pages that are rarely-accessed by the VM to the virtual storage. In the hypervisor, one or more of the physical memory pages allocated to the VM are selected, and the corresponding virtual memory pages preventing from being swapped-out by the guest OS, by marking the corresponding virtual memory pages in the guest OS as accessed thus causing the guest OS to regard the corresponding virtual memory pages as frequently-accessed.

Abstract: Systems and methods are provided that facilitate retrieval of a hash index in an electronic device. The system contains an addressing component that generates a hash index as a function of an exclusive-or identity. The addressing component can retrieve the hash index as a function of a tag value. Accordingly, required storage area can be reduced and electronic devices can be more efficient.

Abstract: A DMA-capable device of a virtualization host stores a DMA write record, indicating a portion of host memory that is targeted by a DMA write operation, in a write buffer accessible from a virtualization management component of the host. The virtualization management component uses the DMA write record to identify a portion of memory to be copied to a target location to save a representation of a state of a particular virtual machine instantiated at the host.

Abstract: A system on chip, includes a memory, a bus, a plurality of intellectual property (IP) blocks, and a unified input/output memory management unit (IOMMU) connected between the memory and the bus and configured to determine whether to perform address conversion for a transaction transferred from the bus based on transaction information.

Abstract: Circuits and methods are provided for detecting, identifying and/or removing undesired content. According to one embodiment, a method for virus co-processing is provided. A general purpose processor stores a data segment to its system memory using a virtual address. The system memory has stored therein a page directory and a page table containing information for translating virtual addresses to physical addresses within a physical address space of the system memory. A virus processing hardware accelerator translates the virtual address of the data segment to a physical address of the data segment based on the page directory and the page table. The hardware accelerator accesses the data segment based on the physical address. The hardware accelerator scans the data segment for viruses by executing multiple pattern comparisons against the data segment. The hardware accelerator returns a result of the scanning to the general purpose processor via the system memory.

Abstract: In an embodiment of the present invention, a method includes partitioning a plurality of remote direct memory access context objects among a plurality of virtual functions, establishing a remote direct memory access connection between a first of the plurality of virtual functions, and migrating the remote direct memory access connection from the first of the plurality of virtual functions to a second of the plurality of virtual functions without disconnecting from the remote peer.

Abstract: Mobile devices, systems, and methods for end-user transparent utilization of computational, storage, and network capacity of mobile device are described herein. A communication interface may be responsive to a request for a resource from a network of mobile devices. A database may store mobile device information and, in response to the request, identify at least one mobile device having the resource. A virtual machine dispatcher may generate a command to a virtual machine dispatch agent of the at least one mobile device to create a virtual machine to perform the resource.

Abstract: According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

Abstract: Subject matter disclosed herein relates to validating memory content in persistent main memory of a processor.

Abstract: A method of cloning data in a memory for a source virtual machine (VM) and at least one cloned virtual machine is proposed. A mapping relationship between a guest physical address from the source VM or the cloned VM and a host physical address of the memory is defined by a plurality of page tables configured in a plurality of hierarchical levels. In the method, metadata of the page tables in the highest level or the higher levels of the plurality of hierarchical levels is copied to the virtual machine. Remaining metadata of the page tables in the levels other than the highest level or the higher levels of the plurality of hierarchical levels is replicated to the virtual machine in response to the access operation. Data stored in the corresponding address of the memory is accessed according to the metadata and the replicated metadata.

Abstract: A method and a circuit configuration for generating a bit vector are described. At least two configurations, each having state machines of the same design, are used, to whose inputs an input signal is sent and which generate an output signal as a function of their state, each state machine always having a different state than the other state machine of one configuration, so that the bit vector is generated by a linear gating of the output signals of the state machines of different configurations.

Abstract: A method and system for managing a flash memory system facilitates the use of TRIM or similar operations so as to release physical memory space of logical block addresses (LBAs) that are declared to be deleted by a user file management system. A plurality of data structures corresponding to levels of indirection are used to manage the mapping between a user logical block address and the physical location of the data in the flash memory system and to respond to user read and write requests by determining the current status of the user logical block address in the frame of reference of the memory system. This process substantially decouples TRIM management from garbage collection and wear leveling operations.

Abstract: A method of reading data in a data storage device with a controller and a memory includes generating, in the memory, a set of bits corresponding to a particular storage element of the memory. The set of bits indicates a group of threshold voltage intervals. A threshold voltage of the particular storage element corresponds to one of the threshold voltage intervals within the group. At least one threshold voltage interval within the group is separated from another threshold voltage interval within the group by an intervening threshold voltage interval that is not within the group. The method also includes sending the set of bits to the controller. The set of bits includes a first hard bit that corresponds to a value read from the particular storage element and a first soft bit that corresponds to a reliability measure.

Abstract: For data backup and recovery based on linked file repositories with each of the linked file repositories representing an individual file system capable of storing at least one version of a file and being connected to at least one server system, each of the linked file repositories are placed in a certain position for storing a certain version of the file. Each position of each of the linked file repositories is continuously numbered. A number of the versions of the file are determined by the position of the one of the linked file repositories.

Abstract: Provided is a profiling unit and method for profiling a number of times that an input/output address of a semiconductor device is accessed. The profiling unit includes a hash unit configured to produce at least one hash value by perform a hash operation on the input/output address, and a profiling circuit configured to profile the number of times that the input/output address is accessed by using the at least one hash value.

Abstract: Provided is a virtual machine including a first virtualization module operating on a physical CPU, for providing a first CPU, and a second virtualization module operating on the first CPU, for providing second CPU. The second virtualization module includes first processor control information holding a state of the first CPU obtained at a time of execution of the user program. The first virtualization module includes second processor control information containing a state of the physical CPU obtained at the time of the execution of the second virtualization module, third processor control information containing a state of the physical CPU obtained at the time of the execution of the user program, and prefetch entry information in which information to be prefetched from the third processor control information is set, and, upon detection of a event, the information set in the prefetch entry information is reflected to the first processor control information.

Abstract: A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.

Abstract: A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB is an additional cache storing collapsed translations derived from the MTLB. Entries in the MTLB, the collapsed TLB, and other caches can be maintained for consistency.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: Scalable, common reference-clocking architecture and method for blade and rack servers. A common reference clock source is configured to provide synchronized clock input signals to a plurality of blades in a blade server or servers in a rack server. The reference clock signals are then used for clock operations related to serial interconnect links between blades and/or servers, such as QuickPath Interconnect (QPI) links or PCIe links. The serial interconnect links may be routed via electrical or optical cables between blades or servers. The common reference clock input and inter-blade or inter-server interconnect scheme is scalable, such that the plurality of blades or servers can be linked together in communication. Moreover, when QPI links are used, coherent memory transactions across blades or servers are provided, enabling fine grained parallelism to be used for parallel processing applications.

Abstract: A computer processor receives a plurality of execution items corresponding to a computer process. The computer processor allocates a first memory portion corresponding to a first stack, wherein the first stack corresponds to a first class of execution items. The computer processor allocates a second memory portion corresponding to a second stack, wherein the second stack corresponds to a second class of execution items. The computer processor identifies a first execution item of the plurality of execution items and determining a class corresponding to the first execution item.

Abstract: An apparatus and method for converting between a full memory address and a compressed memory address. For example, one embodiment comprises one or more translation tables having a plurality of translation entries, each translation entry identifiable with a pointer value and storing a portion of a full memory address usable within the processor to address data and instructions; and address translation logic to use the translation tables to convert between the full address and a compressed version of the full address, the compressed version of the full address having the pointer value substituted for the portion of the full memory address, wherein a first portion of the processor performs operations using the compressed version of the full address and a second portion of the processor performs operations using the full address.

Abstract: Processes are disclosed for decreasing contention in caches in order to increase the efficiency of multi-threaded or multi-processor systems. By using multiple locks in a cache, smaller portions of the cache can be locked during cache updates (e.g., during a data update or a storage block eviction). As only small portions of the cache are locked at any given time, contention between threads, particularly in multi-processor implementations, will likely be reduced. For example, if different threads are trying to update different entries in the cache, the threads can proceed with updating the cache concurrently.

Abstract: A fault occurs in a virtual environment that includes a base space, a first subspace, and a second subspace, each with a virtual address associated with content in auxiliary storage memory. The fault is resolved by copying the content from auxiliary storage to central storage memory and updating one or more base space dynamic address translation (DAT) tables, and not updating DAT tables of the first and second subspace. A subsequent fault at the first subspace virtual address is resolved by copying the base space DAT table information to the first subspace DAT tables and not updating the second subspace DAT tables. A fault occurring with association to the virtual address of the first subspace is resolved for the base space and the base space DAT table information is copied to the first subspace DAT tables, and the second subspace DAT tables are not updated.

Abstract: A method, computer program product, and computing system for receiving a read request on a first cache system, wherein the read request identifies previously-written content included within a data array. The previously-written content identified in the read request may be obtained from the data array. The previously-written content identified in the read request may be compressed, thus generating compressed previously-written content. A compression ratio may be determined for the compressed previously-written content.

Abstract: The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register.

Abstract: The present invention provides a virtual machine system and a method for sharing a graphics card amongst virtual machines. A VMM of the virtual machine system is provided with a resource-converting module, which converts data exchanged between a graphics card drive module of a GOS in the foreground and the graphics card based on a resource-converting table, and also intercepts accesses to the real graphics card by a GOS in the background and then responds to its operations on the graphics card. The VMM is further provided with a switching module, which alters a state of a VM based on a command for switching the VM, saves a graphics card state before the VM is switched to the background and restores the stored graphics card state to the graphics card when the VM is switched back to the foreground. Further, the GOSs each comprise a graphics card drive module corresponding to the real graphics card for accessing the real graphics card.

Abstract: An exemplary method in accordance with embodiments of this invention includes, at a virtual machine that forms a part of a cluster of virtual machines, computing a key for an instance of a memory page that is to be swapped out to a shared memory cache that is accessible by all virtual machines of the cluster of virtual machines; determining if the computed key is already present in a global hash map that is accessible by all virtual machines of the cluster of virtual machines; and only if it is determined that the computed key is not already present in the global hash map, storing the computed key in the global hash map and the instance of the memory page in the shared memory cache.

Abstract: Systems and methods for offloading computations of an integrated circuit (IC) to a processor are provided. In particular, a programmable logic designer, compiler, etc. may dictate particular logic to offload to a processor. This offloading may enhance programmable logic area utilization and/or increase throughput.