Abstract: Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described.

Abstract: For managing a database in a data-processing system, a polymorph table and a mapping structure are provided. The polymorph table includes a discrimination column and a total number of columns of each type equal to a maximum of the virtual columns of the type. The mapping structure stores information mapping each virtual column to a polymorph column of the same type. A virtual access request is received based on one of the virtual columns of one of the virtual tables. Selected mapping information is retrieved that maps each selected virtual column to one of the polymorph columns. The virtual access request is converted into a polymorph access request according to an identifier of the selected virtual table and the selected mapping information. The polymorph table is accessed according to the polymorph access request.

Abstract: Systems and methods presented herein provide for locating data in non-volatile memory by decoupling a mapping unit size from restrictions such as the maximum size of a reducible unit to provide efficient mapping of larger mapping units. In one embodiment, a method comprises mapping a logical page address in a logical block address space to a read unit address and a number of read units in the non-volatile memory. The method also comprises mapping data of the logical page address to a plurality of variable-sized pieces of data spread across the number of read units starting at the read unit address in the non-volatile memory.

Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes: a first virtual layer interfacing with the hosts, operable to represent a logical address space characterized by logical block addresses and available to said hosts and characterized by an Internal Virtual Address Space (IVAS) and operable, responsive to a configuration or I/O request addressed to the logical block addresses, to translate said logical block addresses into IVAS addresses; and a second virtual layer interfacing with the physical storage devices, operable to represent an available physical space to said hosts and characterized by a Physical Virtual Address Space (PVAS), addresses in PVAS having corresponding address in IVAS. The second virtual layer is operable to translate said respective IVAS addresses into addresses in the physical address space.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: Embodiments of the disclosure include a method for optimizing large page processing. The method includes receiving an indication that a real memory includes a first page. The first page includes a plurality of smaller pages. The method also includes determining a page frame table entry associated with a first smaller page of the first page and storing data associated with the first page in the page frame table entry associated with the first smaller page. The page frame table entry associated with the first smaller page of the first page is a data repository for the plurality of smaller pages of the first page.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: A virtual memory management apparatus of an embodiment is embedded in a computing machine 80 and is provided with an application program 21, an operating system 22, a volatile memory 11, and a nonvolatile memory 12. The volatile memory 11 is provided with a plurality of clean pages. The nonvolatile memory 12 is provided with a plurality of dirty pages and a page table memory unit 51. The operating system 22 is provided with a virtual memory management unit 23 which includes a page transfer unit 25.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: Embodiments of the invention describe an apparatus, system and method for sub-block based wear leveling for memory devices. Embodiments of the invention may receive a write request to a physical memory address including a physical block address and a physical sub-block address. An address remapping table is accessed to translate the physical block address to a memory device block address to locate a plurality of memory device sub-blocks. A plurality of sub-block activity counters are accessed, each sub-block activity counter associated with one of the memory device sub-blocks. One of the plurality of memory device sub-blocks is selected to store write data of the write request based, at least in part, on values of the plurality of sub-block activity counters, and the value of the sub-block activity counter associated with the selected memory device sub-block is updated.

Abstract: A data read method for reading data to be accessed by a host system from a plurality of flash memory modules is provided. The data read method includes receiving command queuing information related to a plurality of host read commands from the host system, each of the host read commands is corresponding to one of a plurality of data input/output buses coupled to the flash memory modules. The data read method also includes re-arranging the host read commands and generating a command giving sequence according to the data input/output buses corresponding to the host read commands. The data read method further includes sequentially receiving and processing the host read commands from the host system according to the command giving sequence and pre-reading data corresponding to a second host read command. Thereby, the time for executing the host read commands can be effectively shortened.

Abstract: A method for translation map simplification may include determining a translation map based on a predetermined criterion in response to receiving input data. The method may also include determining if the translation map extends another map or a referenced map and determining if the translation map includes at least one map fragment. The referenced map is loaded in response to a determination that the translation map includes an extension of the referenced map. The map fragment is loaded in response to a determination that the translation map comprises the map fragment. A new map is compiled based on at least the translation map, the referenced map and the at least one map fragment, in response to the translation map not including a new map reference or a modification to the translation map. The input data is processed based on the new map to produce translated data specific to the new map.

Abstract: The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization.

Abstract: A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.

Abstract: An enhanced dynamic address translation facility is provided. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

Abstract: A method and apparatus for reporting events into at least one event log are presented. An “access” event entry may be added to an event log stored in memory when a peripheral device accesses an address of a memory page described by a page table entry (PTE). A “dirty” event entry may be added to an event log stored in memory when a page writes to a memory page. The event log may reside in an input/output memory management unit (IOMMU) that includes a translation lookaside buffer (TLB). The IOMMU may report the event log entries to system memory. When there is no entry in the TLB and a direct memory access (DMA) read operation enters the IOMMU, a PTE may be loaded into the TLB after updating an access log to calculate an address. If the DMA operation is not a read operation, both dirty and access logs may be updated.

Abstract: A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.

Abstract: An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

Abstract: Some embodiments of the present invention include a memory management unit (MMU) configured to, in response to a write access targeting a guest page mapping of a guest virtual page number (GVPN) to a guest physical page number (GPPN) within a guest page table, identify a first page mapping that associates the GVPN with a physical page number (PPN). The MMU is also configured to determine whether a traced write indication is associated with the first page mapping and, if so, record update information identifying the targeted guest page mapping. The update information is used to reestablish coherence between the guest page mapping and the first page mapping. The MMU is further configured to perform the write access.

Abstract: In one embodiment, a processor can operate in multiple modes, including a direct execution mode and an emulation execution mode. More specifically, the processor may operate in a partial emulation model in which source instruction set architecture (ISA) instructions are directly handled in the direct execution mode and translated code generated by an emulation engine is handled in the emulation execution mode. Embodiments may also provide for efficient transitions between the modes using information that can be stored in one or more storages of the processor and elsewhere in a system. Other embodiments are described and claimed.

Abstract: An addressing device and method is provided to enable an electronic system having a less addressing capability to address a memory device having a larger storage space, thereby reducing the manufacture cost of the electronic system. The addressing device includes an address decoder and an address translator. The address decoder receives a first access address belonging to a smaller address space, and determines whether to map the first access address to the larger storage space of the memory device. The address translator is coupled to the address decoder. When the first access address is mapped to the storage space of the memory device, the address translator translates the first access address into a second access address of the larger storage space according to an adjustable base address.

Abstract: A data storage apparatus includes a command processor that receives write commands and data blocks from a host, the write commands comprising block ID's (BID) corresponding to data blocks; storage resources including semiconductor memory and mass storage; a data manager that selects storage resources and allocates selected resources to block ID's; a translation table to map a storage resource to the allocated block ID, and storage resources that are selected after receipt of the write command. A method is further provided for increasing performance in a storage device comprising a plurality of storage resources, transferring data to a storage resource that is available to transfer the data.

Abstract: A method for managing memory operations includes reading a first memory page from a storage device responsive to a request for the first memory page. The first memory page is stored to a system memory. Based on a pre-established set of association rules, one or more associated memory pages are identified that are related to the first memory page. The associated memory pages are read from the storage device and compressed to generate corresponding compressed associated memory pages. The compressed associated memory pages are also stored to the system memory to enable faster access to the associated memory pages during processing of the first memory page. The compressed associated memory pages are individually decompressed in response to the particular page being required for use during processing.

Abstract: A mechanism for random cache line selection in virtualization systems is disclosed. A method includes maintaining a secondary data structure representing a plurality of memory pages, the secondary data structure indexed by a subset of each memory page, determining an index of a received new memory page by utilizing a subset of the new memory page that is a same size and at a same offset as the subset of each memory page, comparing the index of the new memory page with the indices of the secondary data structure for a match, utilizing a main data structure to perform a full page memory comparison with the new memory page if a match is found in the secondary data structure, and updating at least one of the size of the subset, the number of subsets, and the offsets of the subsets used to index the memory page.

Abstract: A disk drive is disclosed comprising a head actuated over a rotatable disk. A write operation is processed to write data on the disk using the head, wherein prior to writing the data on the disk, logical-to-physical mapping information is stored in a circular buffer, wherein the logical-to-physical mapping information identifies locations on the disk to write the data. A plurality of metadata files are written on the disk using the head, wherein the plurality of metadata files are interspersed with the data on the disk and each of the metadata files includes contents of the circular buffer at a time the metadata file is written on the disk. When the write operation is aborted, the logical-to-physical mapping information in the circular buffer is modified to identify the locations on the disk actually written.

Abstract: Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.

Abstract: In a memory system using a storage medium, which is inserted into an electronic apparatus via a connector to add a memory function thereto, the storage medium has a GROUND terminal, a power supply terminal, a control terminal and a data input/output terminal, and the connector has a function of being sequentially connected to each of the terminals. When the storage medium is inserted into the connector, the GROUND terminal and control terminal of the storage medium are connected to corresponding terminals of the connector before the power supply terminal and data input/output terminal of the storage medium are connected to corresponding terminals of the connector. Thus, it is possible to improve the stability when a memory card is inserted into or ejected from the memory system.

Abstract: Translation management instructions are used in a multi-node data processing system to facilitate remote management of address translation data structures distributed throughout such a system. Thus, in multi-node data processing systems where multiple processing nodes collectively handle a workload, the address translation data structures for such nodes may be collectively managed to minimize translation misses and the performance penalties typically associated therewith.

Abstract: A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities. The shared resource management unit overrides a stream of access denials (e.g., NACKs) associated with an access problem. The memory management system and method facilitate efficient and flexible access to memory while controlling translation between virtual and physical memory “spaces”. In one embodiment the memory management system includes a translation lookaside buffer and a fill component. The translation lookaside buffer tracks information associating a virtual memory space with a physical memory space.

Abstract: Some embodiments provide a controller for managing a plurality of managed switching elements that forward data through a network. The controller comprising a first set of tables for storing input logical control plane data, and a second set of tables for storing output logical forwarding plane data. It also includes a table mapping engine for mapping the input logical control plane data in the first set of tables to output logical forwarding plane data in the second set of tables by performing a set of database join operations on the input logical control plane data in the first set of tables. The logical forwarding plane data is subsequently translated into physical forwarding behaviors that direct the forwarding of data by the managed switching elements.

Abstract: A detection module selects logically adjacent first and second control areas of a cluster. The detection module further determines that the first and second control areas satisfy a migration test wherein the first control area has free space exceeding a free threshold, the free space is at least equal to a space requirement for each second control area control interval, and the second control area has fewer control intervals than a control interval threshold. In addition, a copy module copies each second control area control interval to the first control area in response to determining that the first and second control areas satisfy the migration test.

Abstract: An approach identifies an amount of high order bits used to store a memory address in a memory address field that is included in a memory. This approach calculates at least one minimum number of low order bits not used to store the address with the calculation being based on the identified amount of high order bits. The approach retrieves a data element from one of the identified minimum number of low order bits of the address field and also retrieves a second data element from one of the one of the identified minimum number of low order bits of the address field.

Abstract: In one embodiment, rule-based virtual address translation is performed for accessing data (e.g., reading and/or writing data) typically stored in different manners and/or locations among one or more memories, such as, but not limited to, in packet switching devices. A virtual address is matched against a set of predetermined rules to identify one or more storing description parameters. These storing description parameters determine in which particular memory unit(s) and/or how the data is stored. Thus, different portions of a data structure (e.g., table) can be stored in different memories and/or using different storage techniques. The virtual address is converted to a lookup address based on the identified storing description parameter(s). One or more read or write operations in one or more particular memory units is performed based on the lookup address said converted from the virtual address.

Abstract: A single application can be executed across multiple execution environments in an efficient manner if at least a relevant portion of the virtual memory assigned to the application was equally accessible by each of the multiple execution environments. A request by a process in one execution environment can, thereby, be directed to an operating system, or other core software, in another execution environment and can be made by a shadow of the requesting process in the same manner as the original request was made by the requesting process itself. Because of the memory invariance between the execution environments, the results of the request will be equally accessible to the original requesting process even though the underlying software that responded to the request may be executing in a different execution environment. A similar thread invariance can be maintained to provide for accurate translation of requests between execution environments.

Abstract: Embodiments of an invention for generating multiple address space identifiers per virtual machine to switch between protected micro-contexts are disclosed. In one embodiment, a method includes receiving an instruction requiring an address translation; initiating, in response to receiving the instruction, a page walk from a page table pointed to by the contents of a page table pointer storage location; finding, during the page walk, a transition entry; storing the address translation and one of a plurality of address source identifiers in a translation lookaside buffer, the one of the plurality of address source identifiers based on one of a plurality of a virtual partition identifiers, at least two of the plurality of virtual partition identifiers associated with one of a plurality of virtual machines; and re-initiating the page walk.

Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Abstract: A memory system comprises a central processing unit. A memory management unit receives a virtual address from the central processing unit. The memory management unit converts the virtual address into a physical address. A main memory is assessed based on the physical address. The main memory stores data used the central processing unit. The main memory includes a first area including a non-volatile memory. First file data having a first characteristic is included in the first area of the main memory. The main memory includes a second area including a volatile memory. Second file data having a second characteristic different from the first characteristic is included in the second area of the main memory. A management table manages only the first area of the first and second areas of the main memory.

Abstract: Memory modules and methods of operating memory modules embed mapping information within blocks of memory cells to which the mapping information pertains. In particular, when a page is written for a logical data block, that page includes a snapshot of the current mapping information for that logical data block. In this manner, the last valid physical page of a logical data block will contain a physical/logical mapping of that block. Thus, instead of scanning every valid page of the memory device to rebuild the mapping information, the memory module may scan only for the last valid physical page of each logical data block. Once the last valid physical page is discovered for a logical data block, the latest mapping information for that logical data block may be read from that page.

Abstract: The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.

Abstract: The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.

Abstract: A system and method for efficiently performing user storage virtualization for data stored in a storage system including a plurality of solid-state storage devices. A data storage subsystem supports multiple mapping tables. Records within a mapping table are arranged in multiple levels. Each level stores pairs of a key value and a pointer value. The levels are sorted by time. New records are inserted in a created newest (youngest) level. No edits are performed in-place. All levels other than the youngest may be read only. The system may further include an overlay table which identifies those keys within the mapping table that are invalid.

Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.

Abstract: A graphics memory device includes a memory array configured to store data for a display device comprising b*y rows by a*x columns of pixels, where b>a. The memory array is arranged in a*y rows by b*x columns of memory locations. Each memory location is adapted to store n-bit image data for one of the pixels of the display device. A memory location remapping circuit is adapted to map image data stored in the b*x columns of memory locations in the memory device to the a*x columns of the display device.

Abstract: A memory operative to provide concurrent two-port read and two-port write access functionality includes a memory array comprising first and second pluralities of single-port memory cells organized into a plurality of rows of memory banks, and multiple checksum modules. The second plurality of memory cells are operative as spare memory banks. Each of the checksum modules is associated with a corresponding one of the rows of memory banks. The memory further includes a first controller and multiple mapping tables. The first controller and at least a portion of the first and second pluralities of memory cells enable the memory array to support two-port read or single-port write operations. A second controller is operative to receive read and write access requests, and to map logical and spare memory bank identifiers to corresponding physical memory bank identifiers via the mapping tables to thereby emulate concurrent two-port read and two-port write access functionality.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: In response to a determination to allocate additional storage, within a real address space employed by a system memory of a data processing system, for translation control entries (TCEs) that translate addresses from an input/output (I/O) address space to the real address space, a determination is made whether or not a first real address range contiguous with an existing TCE data structure is available for allocation. In response to determining that the first real address range is available for allocation, the first real address range is allocated for storage of TCEs, and a number of levels in the TCE data structure is retained. In response to determining that the first real address range is not available for allocation, a second real address range discontiguous with the existing TCE data structure is allocated for storage of the TCEs, and a number of levels in the TCE data structure is increased.

Abstract: An address provided in a request issued by an adapter is converted to an address directly usable in accessing system memory. The address includes a plurality of bits, in which the plurality of bits includes a first portion of bits and a second portion of bits. The second portion of bits is used to index into one or more levels of address translation tables to perform the conversion, while the first portion of bits are ignored for the conversion. The first portion of bits are used to validate the address.

Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

Abstract: In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.