Abstract: A memory controller including a type determining module and a page determining module. The type determining module is configured to determine a type of memory to which the memory controller is connected, wherein the memory includes a memory block comprising a plurality of pages, and each page includes a plurality of memory cells. The page configure module is configured to generate a memory map based on the determined type of the memory. The memory map specifies, for each page, (i) a number of memory cells for storing data, and (ii) a number of memory cells for storing overhead. The number of memory cells for storing data and the number of memory cells for storing overhead in a first page is configurable to be different from the number of memory cells for storing data and the number of memory cells for storing overhead in a second page.

Abstract: Provided are a method and apparatus for wear-leveling of a nonvolatile data storage device, whereby a wear-leveling effect is maximized by storing an age value indicating a write time in each data unit of the nonvolatile data storage device and detecting a static data area based on age values. The method includes storing an age value indicating a write time in each unit assigned to write data therein, reading an age value stored in a unit, and determining a static data area based on the read age value. Accordingly, a static data area can be correctly detected without additional overhead, and a wear-leveling effect of the entire storage device can be increased by moving data to and from the static data area, thereby extending the lifespan of the storage device.

Abstract: A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.

Abstract: According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.

Abstract: Data array manipulation is described. In an embodiment, concurrent access to a multi-dimensional data array stored on a storage device is enabled by providing separate computational elements with access to a model of the data array for processing the data and consequently request changes to the model. The data array is updated in accordance with the changes, and notification of the changes is provided to the other computational elements concurrently accessing the model. In another embodiment, a data interface apparatus is provided that comprises a storage interface that generates a model of the data array, and an application interface that provides access to the model to the computational element for processing. The application interface receives changes to the model resulting from the processing, and a command to commit the changes to the data array. The storage interface then writes the changes to the data array as an atomic operation.

Abstract: A storage apparatus for storing data includes a plurality of physical media provided with storage areas to store data, a storage group determining unit configured to determine, upon detecting a request to write new data to a virtual volume to be accessed, a storage group from which to allocate storage area by selecting a storage group from among a plurality of storage groups made up of the plurality of physical media, wherein the selected storage group is other than any storage groups that include a physical medium where a failure has occurred, and a storage area allocator configured to allocate storage area on the physical media existing within the storage group that was determined by the storage group determining unit to the virtual volume, the size of the storage area corresponds to the data size of the new data.

Abstract: A technique to provide an integrated circuit that performs memory partitioning to partition a memory into a plurality of regions, in which the memory is accessed by a plurality of heterogeneous processing devices that operate to access the memory. The integrated circuit also assigns a security level for each region of the memory and permits a memory access by a transaction to a particular region of the memory, only when a level of security assigned to the transaction meets or exceeds the assigned security level for the particular region. The integrated circuit also performs sandboxing by assigning which of the plurality of processing devices are permitted access to each of the plurality of regions. The integrated circuit may implement only the security level function or only the sandboxing function, or the integrated circuit may implement them both. In some instances, a scrambling/descrambling function is included to scramble/descramble data.

Abstract: A storage medium stores a set of program instructions including: acquiring a number of at least one virtual unit with which at least one of a plurality of storage units is associated, the number of at least one virtual unit being set smaller than a total number of the plurality of storage units; receiving, from an operating system, a first command that specifies one of the at least one virtual unit; registering, as an accessible storage unit, a single storage unit from among the at least one of the plurality of storage units that is associated with the one of the at least one virtual unit specified by the first command, the single storage unit being in condition for communicating data with a data processing device; and outputting, to a peripheral device, a second command that specifies the accessible storage unit based on the first command.

Abstract: Apparatus, method and program product for relocating Bad Block Relocation Directory (BBRD) on a disk storage pre-allocate a number of areas for BBRD in different locations of the disk storage. The locations for the BBRD are calculated based upon the size of the disk and BBRD count. If the update of BBRD fails due to defective media at the location to be updated, that location is abandon and the next pre-allocated location is used. A copy of the BBRD is stored in RAM and maintained by the kernel. By so doing, when a bad block in the BBRD is detected the kernel causes the BBRD to be written in a good one of the locations reserved for BBRD. When the number of alternate BBRD locations used hits a pre-defined threshold, this indicates a situation where many sections of the disk are going bad and the disk needs replacement. If all BBRD locations are used, the disk is presumed bad and all future I/O activities to the disk is suspended.

Abstract: A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map.

Abstract: Disclosed are a column-based data managing method and apparatus, and a column-based data searching method. The column-based data managing method includes determining whether the size of the column-group data file exceeds a partitioning threshold, dividing the column-group data if the size exceeds the partitioning threshold, and generating divided column-group data files.

Abstract: A storage controller of the present invention can input and output data even when the track size, which is the host management unit, is not consistent with the block size of the storage device. A boundary correction unit adds gap data corresponding to a gap size to data in a buffer memory so that the boundary of the track and boundary of the block inside the storage device match. A guarantee code is added to each logical block received from the host, and these guarantee code-appended blocks are stored in a cache memory. By providing a gap in the storage device every 116 extended logical blocks, the start position of the lead block of a track matches up with the start position of the logical blocks of the storage device.

Abstract: A method for deploying one or more virtual machines on a host computing system is provided. The method comprises receiving mapping information from a data storage system. The mapping information associates a first data chunk stored in the data storage system with a unique identifier to support deployment of a first virtual machine on a host computing system. Once the mapping information is received, the mapping information is utilized to determine whether any copies of the first data chunk have already been loaded into a memory of the host computing system in association with deployment of the first virtual machine or a second virtual machine on the host computing system. If no copies of the first data chunk have already been loaded into the memory, the first data chunk is retrieved from the data storage system, loaded into the memory, and utilized to deploy the first virtual machine on the host computing system.

Abstract: A method for operating an electronic control unit during a calibration phase; the method contemplating the steps of: dividing an area of a FLASH storage memory connected to a microprocessor in two pages between them identical and redundant, each of which is aimed at storing all the calibration parameters used by a control software; and using the two pages alternatively so that a first page contains the values of the calibration parameters and is queried by the microprocessor, while a second page is cleared and made available to store the updated values of the calibration parameters.

Abstract: A thin provisioning storage system is able to present a thin provisioned volume to a computer, such that the computer stores data to the volume as if storage space on disk drives was already allocated for the volume. Upon receiving a write request from the computer, in which the write request is directed to an area of the volume for which storage space on the disk drives has not yet been allocated, the storage system allocates new space on the disk drives. When allocating the new space, the storage system obtains a designated performance level for the volume, and determines a number of storage extents to be allocated to the volume based upon the determined performance level. The storage system also is able to take into account performance metrics for the disk drives and/or array groups when selecting locations from which to allocate the storage extents.

Abstract: To provide a technology for stopping recording in an improper state by detecting whether an electronic device is in the process of being carried or not, and so on. Data signals that have been broadcast are received, the data signals are recorded on a storage unit at preset time, a state related to the recording of the data signals is detected, the data signals are recorded, and the recording of the data signals is stopped corresponding to a result of the detection.

Abstract: A fault-tolerant system for storage arrays that stored parity values both on separate disks from the data elements (horizontally aligned) and on the same disks as the data elements (vertically aligned), a so-called horizontal-vertical code or HoVer code. The fault-tolerant system has embodiments that are supported on a variety of array sizes and has significant flexibility in parameter selection. Certain embodiments can tolerate all combinations of T failed disks and, among those, some embodiments can tolerate many instances of more than T failures. The fault-tolerant system has efficient XOR-based encoding, recovery, and updating algorithms and has simple redundancy formulas.

Abstract: The present invention proposes a method and a system for dynamic cache partitioning for application tasks in a multiprocessor. An approach for dynamically resizing cache partitions based on the execution phase of the application tasks is provided. The execution phases of the application tasks are identified and updated in a tabular form. Cache partitions are resized during a particular instance of the execution of application tasks such that the necessary and sufficient amount of cache space is allocated to the application tasks at any given point of time. The cache partition size is determined according to the working set requirement of the tasks during its execution, which is monitored dynamically or statically. Cache partitions are resized according to the execution phase of the task dynamically such that unnecessary reservation of the entire cache is avoided and hence an effective utilization of the cache is achieved.

Abstract: Systems, methods, and computer readable media for managing digital media in a memory storage device associated with a mobile smart device are disclosed. According to one aspect, the subject matter described herein includes a method for configuring a rewriteable non-volatile memory for presentation of media by a selected media presentation device model. The method includes providing a rewriteable non-volatile memory configuration interface through which a user can select at least one media file and one of a plurality of media presentation device models.

Abstract: In order to further develop a method of and a system (100) for controlling the programming of, in particular the erase/write access to, a memory device (10) comprising multiple memory cells (20, 22), said memory cells (20, 22) being exposed to wear resulting from repeated programming, in such way that an increased lifetime of the memory device (10), in particular on an integrated circuit, is provided even under exceptional stress of the memory device (10), it is proposed to provide—at least one quality measuring/determining means (40, 42) being assigned to each memory cell (20, 22) in order to measure and/or to determine the quality of the respective memory cell (20, 22), in particular in order to measure and/or to determine the prospective endurance specified according to a number of change cycles which the respective memory cell (20, 22) can endure within a performance tolerance, and—at least one control means (50), in particular by at least one access load distributor, —being coupled to each quality measur

Abstract: A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.

Abstract: A storage resource including one or more first storage devices; a first logical volume formed according to storage space of the storage resource; a member for accommodating a removable second storage device selected by a user; and a backup unit, the backup unit executing a backup of data stored in the first logical volume to a second logical volume formed according to storage space of the removable second storage device mounted in the member and paired with the first logical volume; and storing, in said storage resource, of backup generation information elements pertaining to what generation of the backup the current backup of the first logical volume is.

Abstract: A controller configures a plurality of solid state disks as a redundant array of independent disks (RAID), wherein the plurality of solid state disks store a plurality of blocks, and wherein storage areas of the plurality of solid state disks corresponding to at least some blocks of the plurality of blocks have different amounts of estimated life expectancies. The controller includes in data structures associated with a block that is to be stored in the storage areas of the plurality of solid state disks an indication that the block includes parity information corresponding to the RAID, wherein parity information comprises information corresponding to an error correction mechanism to protect against a disk failure.

Abstract: A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel.

Abstract: To provide a tape feeder and an electronic component mounting apparatus that enables easy, reliable recognition of a model of an individual subjected to a specification change after factory shipment. A storage unit 20 of a feeder control unit 8 includes a first memory area 21 for storing a code (model code) pertaining to a model of a tape feeder 2 at factory shipment along with a serial code showing an individual of the tape feeder 2 and a second memory area 22 for storing a code (a specification change code) pertaining to a change made to specifications of the tape feeder 2 after factory shipment. The second memory area is empty at factory shipment. Every time a change is made to specifications with elapse of a time after factory shipment, a new code is additionally stored in the second memory area.

Abstract: A method and system for binding a preferred CPU to a virtual partition of a computer is disclosed. In one embodiment, a preferred CPU for a virtual partition of a computer is determined upon a receipt of a request to assign a CPU to the virtual partition. Then, the preferred CPU is assigned to the virtual partition when the preferred CPU is available for assignment. Further, the preferred CPU is retained in the virtual partition when the virtual partition is rebooted.

Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

Abstract: A system and method for managing an electronic storage volume is described. The method includes assigning a threshold to a constrained storage space to define a first state in which an amount of data stored in the constrained storage space exceeds the threshold and a second state in which the amount of data stored in the confined storage space does not exceed the threshold. The method also includes comparing the amount of data to be stored in the constrained storage space and the threshold, and performing a predefined action if the comparison indicates that the amount data to be in the confined storage space would cause a transition between the first state and the second state.

Abstract: To store a plurality of input bits, the bits are mapped to a corresponding programmed state of one or more memory cells and the cell(s) is/are programmed to that corresponding programmed state. The mapping may be many-to-one or may be an “into” generalized Gray mapping. The cell(s) is/are read to provide a read state value that is transformed into a plurality of output bits, for example by maximum likelihood decoding or by mapping the read state value into a plurality of soft bits and then decoding the soft bits.

Abstract: A computer system includes a north bridge chipset, a south bridge chipset, a memory, and a rapid startup apparatus. The rapid startup apparatus includes a DRAM module to install application programs or operation system programs, a battery, a control chip to control data reading and writing for the DRAM module, a PCI-E interface, and a switch circuit. The application programs or the operation system programs are loaded into the memory via the PCI-E interface, the south bridge chipset, and the north bridge chipset in series. The switch circuit processes voltage of the battery or the PCI-E interface and supply power to the DRAM module.

Abstract: Disclosed is memory apparatus (20) in which an area (34) of a memory element (24) is reserved for configuration data relating to parameters of the memory apparatus (20), the area (34) being accessible using a command issued by a device driver (10). Including the configuration data in the memory apparatus (20) simplifies the design and maintenance of the device driver (10).

Abstract: An apparatus and method provide parallel installation of logical partitions on a computer system. The function of a hardware maintenance console is built into a logical partition configuration mechanism that resides in the system firmware. A virtual local area network (VLAN) is used by the logical partition configuration mechanism to define an I/O bridge that allows installing multiple logical partitions in parallel. Because multiple logical partitions may be installed in parallel, the time required to install logical partitions is greatly reduced.

Abstract: In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.

Abstract: One or more registers used to form an address usable in accessing storage are examined to determine if a zero address event has occurred in forming the address. In response to an indication that a zero address event has occurred in address formation, an alert is provided to the program using the address to access storage.

Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.

Abstract: A system includes a virtualized I/O device coupled to one or more processing units. The virtualized I/O device includes programmed I/O (PIO) configuration registers corresponding to hardware resources, and a storage for storing a resource table that includes a plurality of entries. Each entry corresponds to a respective hardware resource. A system processor may allocate the hardware resources to functions that may include physical and virtual functions, and may program each entry of the resource discovery table for each function with an encoded value that indicates whether a requested hardware resource has been allocated to a requesting process, and whether the requested hardware resource is shared with another function. Processing units may execute a device driver instance associated with a given process to discover allocated resources by requesting access to the resource discovery table. The virtualized I/O device protects the resources by checking access requests against the resource discovery table.

Abstract: An operation method of file system includes retrieving the first header of the first file, adding the auxiliary data to the first header to generate the second header, writing the dummy data into the second header to adjust the data length of the second header, thereby serving as the third header, and modifying the link relation of clusters recorded in the file allocation table such that the third header and the second data segment are linked together, thereby generating the second file.

Abstract: A management device obtains, from the plurality of storage nodes, information of accesses which are made to the actual storage areas included in the storage nodes, generating load information of the actual storage areas based on the access information, and storing the generated load information in a load information storage unit. The device changes, based on the load information stored in the load information storage unit, the assignment relations of the actual storage areas with respect to the virtual storage areas such that loads of the storage nodes are leveled. The device instructs the plurality of storage nodes to move the data in the actual storage areas depending on change in the assignment of the actual storage areas to the virtual storage areas.

Abstract: A memory management device includes a memory area, an allocator generating unit that generates a plurality of allocators, which allocates a memory resource of the memory area to a task, for respective rules of allocation/deallocation of the memory resource, and a task correlating unit that selects one of generated allocators based on an allocator specification that is different for each task by the task and sets such that the task is capable of using selected allocator.

Abstract: A data storage device comprising: at least two flash devices for storing data; a circuit board, wherein each of the flash devices are integrated on the circuit board; a controller integrated on the circuit board for reading and writing to each flash devices, wherein the controller interfaces each flash devices; at least one NOR Flash device in communication with the controller through a host bus; at least one host bus memory device in communication with the controller and at least one NOR Flash device through the host bus; at least one interface in communication with the controller and adapted to physically and electrically couple to a system, receive and store data therefrom and retrieve and transmit data to the system.

Abstract: Disclosed is a method and a system for identifying a resource allocation in computer program code. The method comprises the steps of identifying computer program code that initiates a resource allocation process, generating a certificate for the identified computer program code and storing the certificate as a parameter in the computer program code initiating the resource allocation process, and in a table which further comprises adhering file and line data of the computer program code that initiates the resource allocation process, and performing a resource allocation call including the certificate.

Abstract: An embodiment of the invention provides a method for effective memory clustering to minimize page faults and optimize memory utilization. More specifically, the method monitors data access requests to secondary storage and identifies data addresses in secondary storage having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein a cross-sectional partition is created (sliced) from the multi-dimensional cluster. The method receives a request for a data object in secondary storage and identifies a data address corresponding to the requested data object. The data address is mapped to the multi-dimensional cluster and/or the memory page; and, the memory page is transferred to a data cache in primary storage.

Abstract: A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell.

Abstract: A safety device is disclosed for a gantry crane configured to lift containers from a truck driven chassis. The safety device estimates truck movement when the gantry crane lifts the container and sends an alert to avert lifting the truck when the container fails to decouple from the chassis. Motion sensors are disclosed that are configured to coupled to a trolley of a gantry crane and used to create an estimate of the front or back region near a container being lifted. A processor may use the motion sensor signals to avert lifting the truck and/or to avert an Optical Character Recognition (OCR) system reporting a container identification failure when a hatch cover is lifted off of a ship. In various embodiments, the processor may be included in the safety device and/or in the OCR system.

Abstract: A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

Abstract: In one embodiment, a hybrid storage device including a persistent memory, a volatile memory, a processor, a memory loader module that enables the processor to load a first set of information from the persistent memory device to the volatile memory device, to organize the first set of information according to a predetermined format, and a storage drive interface controller that enables the processor to receive information access requests from a host computer, to provide a second set of information from the volatile memory device to the host computer, and to provide a metadata descriptive of the first set of information to the host computer is disclosed. A host computer is enabled to access the first set of information using metadata provided by the storage drive interface controller without having the first set of information in a local memory of the host computer.

Abstract: A method and system are disclosed that permit a storage device to remain fully functional despite running out of a sufficient supply of spare blocks in memory. The storage device includes a non-volatile memory and a controller, where the controller is configured to detect an insufficiency of spare blocks and convert operative blocks to spare blocks. The method includes techniques for selecting certain operative blocks for conversion to spare blocks using the storage manager on the storage device and a file system manager that may or may not be part of the storage device.

Abstract: A method and apparatus optimizes storage on solid-state memory devices. The system aggregates object storage write requests. The system determines whether objects associated with the object storage requests that have been aggregated fit in a block of the solid-state memory device within a defined tolerance.

Abstract: A memory system and corresponding method of wear-leveling are provided, the system including a controller, a random access memory in signal communication with the controller, and another memory in signal communication with the controller, the other memory comprising a plurality of groups, each group comprising a plurality of first erase units or blocks and a plurality of second blocks, wherein the controller exchanges a first block from a group with a second block in response to at least one block erase count within the group; and the method including receiving a command having a logical address, converting the logical address into a logical block number, determining a group number for a group that includes the converted logical block number, and checking whether group information comprising block erase counts for the group is loaded into random access memory, and if not, loading the group information into random access memory.