Abstract: An access control device which writes data to each of predetermined storage block sets in a storage device of which a storage area has been divided into a plurality of storage blocks. The control device includes a management information storage section and an access processing section. The management information storage section stores, for each of said storage blocks, record enable/disable information indicating whether said storage block is a non-defective block in which the data can be recorded or a defective block in which the data cannot be recorded. If the data is written to each of said storage block sets, the access processing section writes the data only to non-defective blocks in said storage block set based on the record enable/disable information stored in said management information storage section.

Abstract: A RAID testing method and a RAID testing system including a reading unit, an option-ROM, a recording unit and several RAID configuration data are provided. These data are either contained in several binary files or stored in a memory. In the method, first, these data are read by the reading unit under a first mode to simulate connecting to several physical disk drives in a first manner. Then, a global RAID configuration information is generated according to these RAID configuration data. Further, these data are read by the reading unit under a second mode to simulate connecting to these physical disk drives in a second manner. Afterwards the global RAID configuration information is updated by the option-ROM in accordance with the second mode. Moreover, the global RAID configuration information is recorded by the recording unit.

Abstract: A solid-state storage subsystem, such as a non-volatile memory card or drive, includes multiple interfaces and a memory area storing information used by a data arbiter to prioritize data commands received through the interfaces. As one example, the information may store a priority ranking of multiple host systems that are connected to the solid-state storage subsystem, such that the data arbiter may process concurrently received data transfer commands serially according to their priority ranking. A host software component may be configured to store and modify the priority control information in solid-state storage subsystem's memory area.

Abstract: Provided is a method for managing a memory storage region used by a processor. The processor is connected to the memory that stores data accessed while a task is being executed. The memory management method including the steps of: dividing the memory area of the memory into blocks having a plurality of different sizes; selecting a block having a size matching a size of the data accessed while the task is being executed; and storing the data accessed while the task is being executed in the selected block.

Abstract: A memory profiling system profiles memory objects in volatile memory and identifies memory objects as candidates to be stored and read directly from nonvolatile memory. The profiling system monitors memory accesses via page faults and identifies a memory object to be loaded in volatile memory. The profiling system uses page faults to determine a page fault type and a write frequency for the memory object, and determines the memory object's memory access type. The profiling system determines whether the object's memory access type meets the capabilities of the nonvolatile memory technology. If the memory access type meets the nonvolatile memory technology capabilities, the profiling system identifies the memory object as a candidate to be transitioned to and read directly from nonvolatile memory (e.g., NOR and PCM). The profiling system stores the memory object candidates in nonvolatile memory such that the memory objects are read directly from nonvolatile memory.

Abstract: Techniques for adjusting memory in virtual machines are disclosed.

Abstract: A semiconductor device disclosed herein is provided with a plurality of function reconfigurable cells, each comprising a memory circuit and a control circuit, for realizing variable logical functions. A function reconfigurable cell autonomously controls a read address in the memory circuit storing true value data by itself. For example, the control circuit takes feedback input of information that has been read from the data field and control field of the memory circuit synchronously and uses feedback input information from the data field or another information as address information for next synchronous reading of the data field and control field, based on feedback input information from the control field. Because each function reconfigurable cell is capable of autonomous control of reading of the memory circuit storing true value data by itself, it is possible to handle the memory circuit for realizing variable logical functions as a circuit equivalent to a logic circuit.

Abstract: A system and method for managing disk space in a thin-provisioned storage subsystem. If a number of free segments in a free segment pool at a storage subsystem is detected as below a desired minimum, one or more of the following is performed: selecting and adding logical devices (LDEVs) from an internal storage as free segments to the free segment pool, transitioning LDEVs to a virtual device (VDEV), and/or selecting and adding LDEVs from an external storage as free segments to the free segment pool. The transitioning includes identifying partially used or completely used LDEVs and transitioning these to the VDEV. Data migration may also occur by: selecting a source segment at a VDEV for migration, reading data from the source segment, writing the data to a target segment, the target segment being a free segment from the free segment pool, and assigning the target segment to the VDEV.

Abstract: A method for initializing a control device of a memory, the control device executing commands for accessing the memory transmitted to the memory by a control signal, the method comprising steps of detecting the switching on of the memory and of at least partially initializing the control device following the switching on of the memory. According to one embodiment of the present invention, the method comprises steps of detecting a specific event in the control signal, and of at least partially initializing the control device following the detection of the specific event.

Abstract: According to one embodiment, an extreme data rate DRAM is a DRAM resetting data thereof in response to a reset signal. When power is initially supplied to a system, a system controller outputs the reset signal to the extreme data rate DRAM in response to a reset signal input from a memory controller through a level shifter. When shutting down power of a system while suspending data stored in the extreme data rate DRAM, the system controller shuts down power of the memory controller while maintaining supply of power to the extreme data rate DRAM in response to the reset signal input from the memory controller through the level shifter.

Abstract: An apparatus and method to allocate memory in a storage system. Firmware running the method uses an iterative approach to find the best optimal memory configuration for a particular storage system given a variety of configuration data parameters stored as persistent data in non-volatile flash memory. The configuration data relates to resources in the environment that the storage system is found in, such as the number of virtual ports, targets and initiators supported by a storage system IOC. The configuration data is alterable, to allow flexibility in updating and changing parameters, and is employed at runtime when the storage system powers on, to enable the most flexible resource allocation.

Abstract: A system and method for managing an electronic storage volume is described. The method includes assigning a threshold to a constrained storage space to define a first state in which an amount of data stored in the constrained storage space exceeds the threshold and a second state in which the amount of data stored in the confined storage space does not exceed the threshold. The method also includes comparing the amount of data to be stored in the constrained storage space and the threshold, and performing a predefined action if the comparison indicates that the amount data to be in the confined storage space would cause a transition between the first state and the second state.

Abstract: A system and method for enabling one or more memories to maintain, update, and provide counter values. In a first version a dynamic random access memory, or DRAM, is bi-directionally communicatively coupled with a processor. The DRAM is divided into a plurality of banks. In the first version a set of subcounters is established, wherein each subcounter element is separately and singly located within a different DRAM bank. The value of a counter can be derived by reading and processing, e.g., adding, all of the values of each of an assigned set of subcounter subvalues maintained within the plurality of banks. Conversely, a counter value may be updated by updating a single assigned subcounter of a single bank. The first method allows a hosting computer to select a subcounter having a shortest access time, where the subcounter is an element of a set of subcounters assigned to maintain a given counter value.

Abstract: A software-based RAID system is provided that enables configuration conflicts to be detected and resolved between a PD that is logically present but physically missing, and a PD that is physically and logically present. In accordance with the invention, a determination is made as to whether such a configuration conflict exists, and if so, the logically-present, but physically missing, reference identifier associated with the PD is remapped to a port number that currently is not in use.

Abstract: Address generation by an integrated circuit is described. An aspect relates generally to an address generator which has first and second processing units. The second processing unit is coupled to receive a stage output from the first processing unit and configured to provide an address output. The stage output is in a first range, and the address output is in a second range. The first range is from ?K to ?1 for K a block size, and the second range is from 0 to K-1.

Abstract: A computer system is able to adopt a RAM module belonged to a first specification with a RAM slot belonged to a second specification. The computer system comprises: a RAM module belonged to the first specification, a RAM sot belonged to the second specification, and a RAM controller connected to the RAM slot. The data, derived from the RAM module and only existed in the first specification, is transmitted to the RAM controller via the N/A pins of the RAM slot when the RAM module is plugged in the RAM slot.

Abstract: A snapshots data structure provides compilers and other tools with snapshots of a buffer at different points in time. Snapshot heads identify trees within a directed acyclic graph (DAG) of nodes. Leaf nodes of a given tree collectively hold data elements representing information that was resident in the buffer at a particular point in time regardless of subsequent editing of the buffer. During buffer editing operations a new tree is created in the DAG with leaf nodes holding data elements that match one-to-one a subsequence of data elements held by leaf nodes of an existing tree.

Abstract: In a particular embodiment, a controller is adapted to control read/write access to a storage media including a pre-allocated area having multiple meta-blocks. The controller includes logic adapted to control the multiple meta-blocks as a first in first out (FIFO) circular queue. The logic selects one or more meta-blocks from the multiple meta-blocks based on an order associated with the FIFO circular queue and selectively writes a logical block address (LBA) mapping table to the selected one or more meta-blocks.

Abstract: System and method for dynamic chunk allocation to data volumes in storage systems. The system includes host computer, management computer and storage system. A dynamic chunk allocation program in the storage system allocates chunks from chunk pool to a volume using a chunk pool management table and a chunk table. A chunk allocation rule table holds rules for allocating chunks from the HDDs. The dynamic chunk allocation program refers to the chunk allocation rule table, to allocate a chunk to a volume. The storage system may have a chunk move program for moving a chunk from one HDD to another HDD or from parity group to parity group for load balancing. A host ID identifying program in the storage system is also used for load balancing. The chunk allocation rule table may be updated by the management computer or rule creation program for changing the rules.

Abstract: A wireless Universal Serial Bus (USB) host that optimizes the data transfer between the Wireless Host Controller Driver (WHCD) and the Wireless Host Controller (WHC). The data transfer between the WHCD and the WHC is optimized by reducing the overhead of data fragmentation. Higher performance without sacrificing memory and computation power is achieved with the optimization of the data transfer.

Abstract: An object of the invention is to provide a memory control unit and a memory control method capable of making the operation setting of SDRAM without intentionally stopping access to the SDRAM. A switch signal generation section (18) for generating a switch signal to switch the operation setting of SDRAM (200), a switch control section (16) for switching the operation setting of the SDRAM (200) using a switch setup value (17) as the switch signal is output from the switch signal generation section (18), and an access control section (14) for suppressing acceptance of an access request to the SDRAM (200) in the time period from the switch start time of the operation setting to the switch completion time are provided. Accordingly, when the operation setting of the SDRAM (200) is changed, it is not necessary to intentionally stop access to the SDRAM (200) and it is made possible to change the operation setting of the SDRAM (200) without being affected by the access situation to the SDRAM (200).

Abstract: In a serial memory device which performs reception and transmission of command, address, and data via serial communication with a host controller, a base address holding circuit holds a base address which serves as a base for effective address calculation. An address operation circuit calculates an effective address based on the base address and an address input from the host controller.

Abstract: A method and apparatus for supporting multiple device numbers on point-to-point interconnect upstream ports. In one embodiment, the method includes a downstream component (DC) that performs discovery of internal device components of the DC during initialization of the DC. Subsequent to the discovery of internal devices of the DC, the DC may issue a multiple device number (MDN) request to an upstream component (UC) of the DC. In one embodiment, the MDN request may include an indication that the DC supports a “multiple device number capability,” as well as a quantity of the internal device components of the DC. The DC may receive an acknowledgement MDN from the UC to indicate a quantity of device numbers allocated to the DC. Subsequently, the DC may assign device numbers to the internal device components of the DC according to configuration requests received from the UC. Other embodiments are described and claimed.

Abstract: A method for establishing an initial state in a computer system having at least two execution units, a switchover between a performance mode and a compare mode being performed, and during the switchover from the performance mode to the compare mode, an initial state for the compare mode being generated, wherein memories or memory areas that are potentially to be adapted for the initial state are provided with an identifier that indicates whether or not the data and/or instructions in these memories or memory areas must be modified for the initial state.

Abstract: In one embodiment, the present invention includes a method for reading configuration information from a multi-function device (MFD), building a dependency tree of a functional dependency of functions performed by the MFD based on the configuration information, which indicates that the MFD is capable of performing at least one function dependent upon another function, and loading software associated with the functions in order based at least in part on the indicated functional dependency. Other embodiments are described and claimed.

Abstract: Available storage locations are identified by searching through a free blocks object non-sequentially. The free blocks object may be logically divided into sections, and the sections may be searched non-sequentially. Each section may be logically divided into a number of sub-sections, and the sub-sections of the various sections may be searched non-sequentially. A new section may be added to the free blocks object, and the added section may be searched until a predetermined threshold or condition is reached, at which point non-sequential searching may begin or resume.

Abstract: According to one embodiment, a first memory device is configured to receive write data from a controller and transmit read data to the controller via a first data pin included in the first memory device. The second memory device is configured to receive write data from the controller and transmit read data to the controller via a second data pin included in the second memory device. A redelivery module within the first memory device is configured to receive an address and a command output from the controller via a predetermined signal line, and output the address and the command to the second memory device via remaining first data pin.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: An approach is provided that retrieves a time spent value corresponding to a selected partition that is selected from a group of partitions included in a virtualized environment running on a computer system. The virtualized environment is provided by a Hypervisor. The time spent value corresponds to an amount of time the selected partition has spent processing interrupts. A number of virtual CPUs have been assigned to the selected partition. The time spent value (e.g., a percentage of the time that the selected partition spends processing interrupts) is compared to one or more interrupt threshold values. If the comparison reveals that the time that the partition is spending processing interrupts exceeds a threshold, then the number of virtual CPUs assigned to the selected partition is increased.

Abstract: A switch device includes two cascade ports each connected to another switch device; at least one direct port connected to a storage medium; a hop-count determining unit that determines whether a frame input from one cascade port has already gone through a predetermined number of switch devices; an output unit that outputs the frame from another cascade port when it is determined that the frame has not gone through the predetermined number of switch devices; and a port determining unit that determines a direct port for outputting the frame when it is determined that the frame has already gone through the predetermined number of switch devices.

Abstract: In a computer system, even when the virtual storage capacity of pools is increased, it is possible to keep the availability of each pool at least at a desired level. The managing server compares a reference value beforehand stored therein with an evaluation value of availability which represents a degree of resistivity against destruction, the degree being derived by use of physical configuration information which is obtained from the controller and which is associated with the pool; and determines necessity of addition of an element to the pool if the availability evaluation value exceeds the reference value and indicates the addition of the element to the pool to the storage apparatus.

Abstract: With this storage apparatus and its control method for presenting multiple virtual volumes to a host apparatus and dynamically allocating to each of the multiple virtual volumes a physical storage area for storing data according to the usage status of each of the multiple virtual volumes, the importance set to each of the multiple virtual volumes is managed, and a storage area is dynamically allocated to each of the multiple virtual volumes. Here, upon dynamically allocating the storage area to each of the multiple virtual volumes, a storage area provided by a plurality of memory apparatus groups respectively configured from a plurality of memory apparatuses is allocated to one or more virtual volumes with low importance among the multiple virtual volumes, and a storage area provided by one of the memory apparatus groups is allocated to other virtual volumes among the multiple virtual volumes.

Abstract: A memory controller is disclosed that provides refresh control circuitry to generate first refresh commands directed to a first row of storage cells within a memory device at a first rate. The refresh control circuitry generates second refresh commands directed to a second row of storage cells within the memory device at a second rate. Output circuitry outputs the first and second refresh commands to the memory device.

Abstract: Techniques for efficiently loading data into a partition of a partitioned table of a database are provided. Data is stored in a swap table and the high water mark of the swap table has been reset prior to storing the data. The swap table is swapped with the partition. After the swap, the swap table becomes the partition of the partitioned table and the partition of the partitioned table becomes the swap table, and the swap table is truncated to reset the high water mark of the swap table.

Abstract: A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.

Abstract: Storage virtualization systems and methods that allow customers to manage storage as a utility rather than as islands of storage which are independent of each other. A demand mapped virtual disk image of up to an arbitrarily large size is presented to a host system. The virtualization system allocates physical storage from a storage pool dynamically in response to host IO requests, e.g., SCSI I/O requests, allowing for the amortization of storage resources-through a disk subsystem while maintaining coherency amongst I/O RAID traffic. In one embodiment, the virtualization functionality is implemented in a controller device, such as a controller card residing in a switch device or other network device, coupled to a storage system on a storage area network (SAN). The resulting virtual disk image that is observed by the host computer is larger than the amount of physical storage actually consumed.

Abstract: A method for automatic firmware upgrade on a target embedded system connected to a TFTP server and a web console is disclosed. The method includes generating a single image from Linux kernel image and file system image and providing single image name as input to web console for firmware upgrade. The web console write upgrade flag and single image name in the kernel configuration and issue a restart command to the embedded system. At boot up time, the start up module checks for firmware upgrade flag set and issue commands for loading the image on target board and boots up with the upgraded image. The firmware upgrade is performed over the network. Further, the embedded system is upgraded with very less user interaction reducing firmware upgrade time and by reducing dependence of experienced/skilled person.

Abstract: Embodiments of the invention enable application programs running across multiple compute nodes of a highly-parallel system to selectively migrate objects from one node to another. For example, when an object becomes too large, a node containing the object may migrate the object to another node, thereby freeing memory space. Whether a large object is migrated can be dependent on how frequently the object is used by the application. Because the memory used by such an object is freed for other uses by the application, overall application performance may be improved. On large parallel systems with thousands of compute nodes, even relatively small improvements in application performance an individual compute node may be magnified many times, resulting in dramatic improvements in overall application performance.

Abstract: A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a loss of memory space in the second memory system. Advantageously, the memory mapping system can be applied to hardware emulator memory systems to more efficiently map design memory systems into an emulation memory system during compilation.

Abstract: Techniques for optimizing configuration partitioning are disclosed. In one particular exemplary embodiment, the techniques may be realized as a system for configuration partitioning comprising a module for providing one or more policy managers, a module for providing one or more applications, the one or more applications assigned to one or more application groups, a module for associating related application groups with one or more blocks, and a module for assigning each of the one or more blocks to one of the one or more policy managers, wherein if one or more of the one or more blocks cannot be assigned to a policy manager, breaking the one or more blocks into the one or more application groups and assigning the one or more application groups to one of the one or more policy managers.

Abstract: A method to configure a storage library, comprising the steps of establishing a logical configuration for said storage library comprising a plurality of physical objects, by configuring a plurality of logical objects using a plurality of logical configuration commands, and adding that plurality of logical objects to the logical configuration. The method further adds the plurality of logical configuration commands to a Configuration Library, and saves that Configuration Library for later use.

Abstract: Proposed are a storage system and its management method having at least two storage apparatuses capable of partitioning an internal resource into logical partitions and managing the logical partitions, and which replicates data written into a primary volume of a primary storage apparatus as the replication source storage apparatus to a secondary volume of a secondary storage apparatus as the replication destination storage apparatus. With this storage system and its management method, configuration information of the logical partition, to which the primary volume belongs, is sent to the secondary storage apparatus, and the configuration of the logical partition to which the secondary volume belongs is set based on the configuration information of the logical partition to which the primary volume belongs.

Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with the type of access. Accordingly, when an application with specific memory access needs is initiated, the memory access profile that is most optimized for that particular access need is utilized to configure access to the memory device. The configuration may be effected for a portion of the memory device, a partition of the memory device, or even one single access location on the memory device.

Abstract: A method and apparatus migrates partition memory in a logically partitioned computer system by utilizing input/output (I/O) space located outside the logical memory blocks (LMBs) to be migrated. The transmit/receive (X/R) queues that are used by network storage adapters and any fixed memory items such as transmit/receive buffers are placed outside the logical memory blocks (LMBs) of the partition. Without the fixed memory items, these LMBs may be migrated without affecting the operation of the network storage adapters or the software in partition memory. The I/O space may be placed outside the partition in a specialized LMB that holds fixed memory items for one or more I/O adapters.

Abstract: A plurality of global LDEV managed by a plurality of controller modules are provided above local LDEV under the control of each controller module. Each global LDEV is correlated to any of the plurality of local LDEV. The controller modules judge whether or not a local LDEV correlated to a global LDEV specified by an I/O request received from a host device or a first other controller module is a management target itself, and if the result of that judgment is affirmative, the controller modules access the local LDEV correlated to the specified global LDEV, while if the result of the judgment is negative, the controller modules transfer the received I/O request to a second other controller module.

Abstract: Systems and methods are described for managing applications in a computer system. An operating system kernel such as Linux can be started and executed at different addresses other than the address typically used for such kernels. An operating system kernel can accommodate end of memory and size of memory that do not comply with normal system specifications. Mechanisms are described that change methods for exception vector handling using a software fix. Dual and/or multi-core systems can run applications in both SMP and ASMP modes without needing any hardware changes. Separate instances or similar copies of an OS such as Linux can be executed on multiple cores in ASMP mode. In SMP mode, Linux or another OS can run as a single instance of the OS.

Abstract: A data management method for network storage system that said network storage system includes a storage network, a cluster of storage servers that provide data storage services for application servers connecting to the storage network and storage space corresponding to each storage server, setting a core manager in storage server, said core manager centralizing the metadata of all storage servers in a common storage space; separating the metadata from said storage servers to make a storage server become a storage manager and the storage spaces corresponding to each storage server form the common storage space, allocating the storage space of metadata in said common storage space, and managing the corresponding relationship between metadata and said storage manager.

Abstract: System, method and computer program product for allocating physical memory to processes. The method includes enabling a kernel to free memory in a physical memory space corresponding to arbitrarily sized memory allocations released by processes or applications in a virtual memory space. After freeing the memory, the system determines whether freed physical memory in the physical memory space spans one or more fixed size memory units (e.g., page frames). The method further includes designating a status of the one or more page frames as available for reuse; the freed page frames marked as available for reuse being available for backing a new process without requiring the kernel to delete data included in the freed memory released by the process.

Abstract: Systems and methods for allocating blocks at a reprogrammable non-volatile mass storage system are disclosed. Generally, a controller identifies a group of data to be written to a block at the mass storage system, and allocates one of a new block or a partial block to the identified group of data based on whether a total unprogrammed capacity in partial blocks of the mass storage system exceeds an amount of valid data in obsolete blocks of the mass storage system. In one implementation, the identifier group of data may be associated with a single file.

Abstract: Methods, apparatus, and products for managing virtual addresses of blade servers in a data center are disclosed that include storing by a blade server management module (‘BSMM’), in non-volatile memory of a blade server, a parameter block, the parameter block including one or more virtual addresses for communications adapters of the blade server and one or more action identifiers, each action identifier representing a type of address modification; detecting, by a basic input-output system (‘BIOS’) module of the blade server upon powering on the blade server, the parameter block; and modifying, by the BIOS module of the blade server in dependence upon the one or more action identifiers of the parameter block, an address of at least one communications adapter of the blade server.