Abstract: A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.

Abstract: A method maintains a hierarchy of application objects in a computer system. The method includes automatically detecting an exit of a child application object, the exit resulting from a failed process, the child application object launched by a parent application object. A grandchild application object is automatically terminated after the exit of the child application object, the grandchild application object launched by the child application object. Notwithstanding the exit of the child application object, the computer system, which maintains the hierarchy of application objects, the parent application object, and the grandchild application object, remains active.

Abstract: Methods and systems for facilitating risk management decisions are provided. Example embodiments provide a Risk Management Decision Facilitator System “RMDFS”, which enables users to normalize all risk management decisions so that they are made consistently, in-line with entity policy, regardless of who is making them and their point in a product lifecycle. An example RMDFS accomplish these goals by providing components and processes that are linked together using a normalized risk matrix, so that all decisions are viewed against a standardized set of severity terms, likelihood terms, and risk classifications regardless of the particulars of the product or process being manipulated. All problem assessments, risk assessments, and risk controls are automatically evaluated quantitatively and qualitatively. This abstract is provided to comply with rules requiring an abstract, and it is submitted with the intention that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method and a system is provided for the processing of data or signals with a number of functional units which are each adapted to apply one or several functions to the data or signals, and which are connected with each other via a connection matrix for the exchange of data or signals between the functional units. At least one functional unit of the system is programmable and/or configurable such that it performs a particular function out of a number of different functions. The connection matrix is programmed and/or configured such that the functional units are connected with each other in a particular configuration out of a number of different configurations.

Abstract: A method of sending data from a memory to a host, and a data storage device that uses the method. The controller of the data storage device sends the data directly from the memory to a buffer in an interface to the host while simultaneously checking the data for errors. If sufficiently few errors are found, the data are sent from the buffer to the host. Otherwise, the data are corrected, the data in the buffer are replaced with the corrected data, and the corrected data are written to the memory. If the data are stored by segments, the simultaneous sending and checking is effected segmentwise. When a bad segment is found, an error flag is set. When all the data have been sent and checked, or when the buffer is full, if the error flag has not been set, the data in the buffer are sent to the host.

Abstract: A semiconductor manufacturing apparatus includes a first program on a controller and a second program on an interface board between the controller and controlled devices. Both of the programs update their own counters and exchange their counter values with each other, serving as bi-directional software watchdog timers (WDT). If a counter value of the first program on the controller sent to the second program on the interface board is determined to be abnormal by the second program, the second program on the interface board sends commands to the controlled devices to terminate output so that the apparatus is navigated to a safe mode. The first program similarly monitors the counter values of the second program for anomalies. This bi-directional software WDT can be implemented as add-on to software programs that already exist in the controller and the interface board, therefore, this implementation does not incur extra cost of hardware of the apparatus.

Abstract: In a control method for a storage system including a plurality of storage devices connected via a network, when starting operation, a first storage device on the network determines whether data of a control program for controlling the first storage device is broken. When the data of the control program is broken, the first storage device transmits a signal indicating that the data of the control program is broken to the network. Upon receipt of the signal, a second storage device on the network determines whether it stores the same control program as that stored in the first storage device. When storing the same control program, the second storage device transmits the control program to the first storage device. The first storage device rewrites the broken control program with the control program received from the second storage device.

Abstract: A method to control an application installed on an image forming apparatus includes checking current status information of the image forming apparatus, comparing the checked current status information with executability information to execute a pre-stored application, and if the application is executable as a result of the comparing, executing the application, and if the application is not executable, displaying information that the application is not executable.

Abstract: A system, method, and computer-accessible medium for storage management are disclosed. A failure condition is detected in a storage stack comprising a first host and a storage device. Data from the storage device is exported to a plurality of additional hosts. The data is validated using the plurality of additional hosts.

Abstract: An apparatus accepts an injustice (grievance) report containing injustice report source terminal information for identifying a terminal device transmitting the injustice report and injustice content holding terminal information identifying a terminal device holding the content altered from the original content and content identification information for identifying the content; accesses a correspondence relation recording unit recording, in association with content identification information identifying the content, notification destination terminal information identifying a terminal device to which the content holding terminal information is notified, and content holding terminal information notified to the notified terminal device; determines that the injustice report accepted by the injustice report accepting is false and discards the false injustice report, when the injustice report source terminal information contained in the injustice report is not coincident with the notification destination terminal in

Abstract: The invention discloses a data filtering method for filtering a 3G data stream which is received. The data filtering method according to the invention includes the following steps. At first, a step (a) of receiving a 3G data stream continually is performed. Then, a step (b) of determining whether the 3G data stream comprises a complete filtering unit is performed. If the 3G data stream comprises a complete filtering unit, a step (c) of determining whether the 3G data stream includes invalid data is performed. If the 3G data stream includes invalid data, a step (d) of marking the invalid data according to a predetermined protocol is performed. Finally, a step (e) of filtering out the marked invalid data is performed.

Abstract: In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an output (pattern body) of the pattern body generation circuit during jitter test. A transmitting-end MAC circuit performs transmitting-end processing of a MAC layer on the data selected by the selector to thereby obtain a MAC frame. A receiving-end MAC circuit performs receiving-end processing of a MAC layer on a received frame in MAC frame format to thereby obtain a payload. A pattern body verification circuit verifies a pattern body that is a payload obtained by the receiving-end MAC circuit during jitter test against a corresponding pattern body before transmission.

Abstract: Progress of a development cycle, such as for the development of a release of a software product, is tracked and managed using a release management system. Such a system allows groups and managers to retain any project planning or status files, in any appropriate structure. A manager can simply upload the file to the system as information is updated, and the system will apply appropriate templates and store the information in such a way that reporting and tracking can be done for any aspect of the development process at any level. For example, a single system can provide a high-level executive overview down to a detail level view of a particular group, using substantially current data for all aspects the process.

Abstract: A Device-to-Device Communication Bus protocol may facilitate transmission of a two to four byte packet by any device sharing the bus. All devices on the bus may monitor the bus, receiving all packets transmitted by other devices and recognizing when they may initiate transmission. The first byte of the packet may be an Address byte uniquely identifying the sender and allowing hardware arbitration to uniquely select one of any number of senders who may wish to transmit and begin transmission simultaneously. Arbitration may take place during transmission of the Address byte, with the transmitting device monitoring a bus bit value as it is transmitting the Address byte. If the data value observed by the transmitting device doesn't match the transmitting device's desired transmit value, the transmitting device may recognize loss of arbitration and suspend transmission to retry once the packet is complete. The receive function in every device may accept the packet as a normal received packet.

Abstract: An administrator can specify a script sequence including one or more system scripts and database scripts. A graphical user interface is provided to allow the administrator to specify an execution order of individual scripts in the script sequence and a timeout interval for when the script sequence will complete. Once the script sequence is specified, the script sequence can be run without further intervention by the administrator.

Abstract: Logical circuit identifiers for rerouted logical circuits in a data network are automatically renamed. A failure is determined in a first logical circuit and a second logical failover circuit is utilized to reroute data from the failed logical circuit. A logical circuit identifier for the failed circuit is compared to a logical circuit identifier for the logical failover circuit. The logical circuit identifiers are utilized to identify and track logical circuits in the data network and are stored in a network database. If the logical circuit identifier for the failed logical circuit is different than the logical circuit identifier for the logical failover circuit, the identifier for the failed logical circuit is renamed to the logical failover circuit in the database. Upon determining that the failed logical circuit has been restored, the identifier for the restored logical circuit is renamed to its original logical circuit identifier.

Abstract: A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: Embodiments of the present invention are directed to digitally encoded hierarchical timestamps that are stored in computer readable mediums. The hierarchical timestamps of the present invention include a first field that stores a timestamp value and a second field that stores a processing-level indication that indicates the scope of the timestamp within a hierarchical processing system.

Abstract: In a software development environment, a system and method for associating an assert with a unique identifier (“assert tag”), and using the unique identifier to store information associated with the assert in a database. Based on the unique identifier, information associated with the assert can be stored in a database or repository that contains assert information. This information can be updated, as well as displayed to the developer or tester. Information for the bugs associated with the assert can be retrieved from a database containing bug information and displayed to the developer or tester. Once the developer or tester has been presented with the information concerning the bugs associated with the assert, or other information associated with-the assert, the developer or tester can choose to enter or log-in a new bug into the database containing bug information.

Abstract: The following description includes a method and a system of detecting bit errors in a multi-core processor. When a subatomic particle, or other matter, impacts the processing cores of the processor, bit flips may occur. To detect these bit flips and thereby prevent erroneous results, operations performed by one core are inversely performed by another core. By comparing the results of the original operation and the inverse operation, embodiments of the invention can detect errors in binary data. If an error is detected, then the operations are performed again. Alternatively, multiple cores do not perform inverse operations, but instead perform identical operations in parallel. The results from the parallel operations are compared and if the results are not identical, then the operations are repeated.

Abstract: Methods and systems to detect virtualization of computer system resources, such as by malware, include methods and systems to evaluate information corresponding to a computer processor operating environment, outside of or secure from the operating environment, which may include one or more of a system management mode of operation and a management controller system. Information may include processor register values. Information may be obtained from within the operating environment, such as with a host application running within the operating environment. Information may be obtained outside of the operating environment, such as from a system state map. Information obtained from within the operating environment may be compared to corresponding information obtained outside of the operating environment. Direct memory address (DMA) translation information may be used to determine whether an operating environment is remapping DMA accesses.

Abstract: A method, system and machine-readable storage medium for providing fault tolerance in a distributed mobile architecture (dMA) system. The method includes receiving a message or failing to receive the message within a predetermined time relating to a first dMA gateway (dMAG) at a second dMAG. It is determined whether the first dMAG is not operational or is otherwise offline based on the received message or the failure to receive the message. One or more dMA nodes associated with the first dMAG are notified in order to request connections to an external system via the second dMAG. The external system is also notified to request connections to one or more dMA nodes associated with the first dMAG via the second dMAG.

Abstract: A control method for an information storage apparatus has the steps of: providing redundancy of information stored in the information storage apparatus; a redundancy failure recording part recording a record of a redundancy failure in a state recording part, when the failure has occurred in keeping of the redundant state of the information; a redundancy monitoring part reading the record of the redundancy failure from the state recording part the record; and a reporting part reporting the redundancy failure when the record of the redundancy failure is read by the redundancy monitoring part.

Abstract: A system and method are provided for presenting trading information. One example method includes displaying a plurality of effective trade indicators corresponding to price levels at which effective trades have been initiated, and displaying trading information corresponding to each effective trade. The effective trades can be determined based on user-configured trade definitions. The trading information can include a traded quantity and profit/loss corresponding to each effective trade. In addition to the trading information, current market information could be displayed as well in relation to the plurality of effective trades.

Abstract: A method of correcting corrupted primitives transmitted between a serial advanced technology attachment (SATA) host and a SATA device includes detecting the presence of a corrupted primitive; analyzing a current state, a previously transmitted primitive, or a previously received primitive; selecting at least one candidate primitive according to at least one of the current state, the previously transmitted primitive, and the previously received primitive; predicting the identity of the corrupted primitive according to at least one candidate primitive and the corrupted primitive; and replacing the corrupted primitive with the predicted primitive.

Abstract: Hypervisor page fault processing logic is provided for a shared memory partition data processing system. The logic, responsive to an executing virtual processor of the shared memory partition data processing system encountering a hypervisor page fault, allocates an input/output (I/O) paging request to the virtual processor from an I/O paging request pool and increments an outstanding I/O paging request count for the virtual processor. A determination is then made whether the outstanding I/O paging request count for the virtual processor is at a predefined threshold, and if not, the logic places the virtual processor in a wait state with interrupt wake-up reasons enabled based on the virtual processor's state, otherwise, it places the virtual processor in a wait state with interrupt wake-up reasons disabled.

Abstract: In order to protect a software program, at least one corruption function is included in the program. Also included in the program is at least one instruction that causes the program to be directed to the corruption function. An available breakpoint is then set such that, when the starting location of the corruption function is reached, an exception is generated and the handling of the exception causes the corruption function not to run. This has the effect that, if a malicious user attempts to use the available hardware breakpoint to perform unauthorized actions on the software program, the corruption function will run, and the software program will be unusable.

Abstract: There is provided an information processing apparatus that includes a CPU board 1 having a processing unit, a control device (CPU 11, CPU board controller 12, and the like) that is mounted on the CPU board 1 and includes hardware replacement management area 16 that stores replacement information indicating that the CPU board 1 has been replaced, the replacement information initialized at the time when the information processing apparatus is started or when the CPU board 1 is replaced, a memory 13 that stores error information based on occurrence of an error in the control device, the error information initialized at the time when the information processing apparatus is started, an initialization control section 18 that initializes the information processing apparatus, and a unit control section 45 that includes an error monitoring section 42 that monitors the error information stored in the memory 13 and controls the CPU board 1.

Abstract: A method for error handling of corrupted repeating primitives during frame reception is disclosed. The method comprises identifying a portion of a received frame including a repeating primitive sequence, determining whether data in the repeating primitive sequence has one or more errors, and indicating a successful reception of the received frame with the one or more errors in the repeating primitive sequence if the number of errors is less than a determined threshold. Other embodiments are also disclosed.

Abstract: One embodiment of the present invention provides a system that reports reasons for failure during transactional execution. During operation, the system transactionally executes a block of instructions in a program. If the transactional execution of the block of instructions completes successfully, the system commits changes made during the transactional execution, and resumes normal non-transactional execution of the program past the block of instructions. Otherwise, if transactional execution of the block of instructions fails, the system discards changes made during the transactional execution, and records failure information indicating why the transactional execution failed.

Abstract: There are provided a message processing device and a method improved to store a plenty of messages used for processing. When a message is transmitted to another node for providing a service, a message processing unit (26) monitors the message transferred and stores it in a storage region whose allocation is released when the remaining memory amount has become little. When an error has occurred in the processing of a service providing unit (200), the message processing unit (26) stores the error type and a session identifier associated with it. When a message transmission is requested from outside and the error type, the session identifier, and a message associated with them are stored, the message processing unit (26) transmits them. If the storage region which was containing a message is released and no message exists, the message processing unit (26) transmits the other two items.

Abstract: Methods and apparatus for implementing peer-to-peer relay. In one implementation, a method of detecting and recovering from violations in a peer-to-peer relay network includes: receiving a message at a peer system from a sending peer system connected to said peer system in a peer-to-peer relay network detecting a violation in said received message; and sending an alert message to each peer system connected to said peer system in said peer-to-peer relay network; wherein each peer system in said peer-to-peer relay network stores a connection limit defining a number of other peer systems up to which that peer system is permitted to connect, and each peer system stores a set of one or more relay rules for relaying data to other peer systems connected to that peer system.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A system and method are provided for presenting trading information. One example method includes displaying a plurality of effective trade indicators corresponding to price levels at which effective trades have been initiated, and displaying trading information corresponding to each effective trade. The effective trades can be determined based on user-configured trade definitions. The trading information can include a traded quantity and profit/loss corresponding to each effective trade. In addition to the trading information, current market information could be displayed as well in relation to the plurality of effective trades.

Abstract: According to one embodiment, an information processing apparatus includes a plurality of execution modules, a system memory shared by the plurality or execution modules, and a scheduler which controls assignment of a plurality of basic modules to the plurality of execution modules in order to execute a program in parallel by the plurality of execution modules. The scheduler saves data items, which is to be input by the execution modules as input data items of the basic modules and is stored in the storage areas of the system memory, in other storage areas of the system memory before the basic modules are executed, and compares the data items stored in the storage areas of the system memory and accessed by the execution modules with the data items saved in the other storage areas of the system memory after the basic modules have been executed.

Abstract: An information processing apparatus includes a plurality of hardware resources and operates on a first power supply. The apparatus includes a non-volatile first storage unit that holds first fault information on a fault developed in one or more of the hardware resources even when the first power supply is shut down, a volatile second storage unit that holds second fault information different from the first fault information and is adapted not to hold the second fault information when the first power supply is shut down, a hardware monitoring unit that acquires component information of the plurality of the hardware resources mounted in the information processing apparatus and a system control unit that makes a fault information management unit restore the second fault information held in the second storage unit based on the component information and the first fault information stored in the first storage unit.

Abstract: A main controller sends a “rewrite mode” command to an engine controller. Receiving the command, the engine controller 12 sends a “roger” status. This switches the mode from a print mode to a rewrite mode. In the rewrite mode, the engine controller 12 serves as a master and the main controller 11 serves as a slave, a communication which is necessary for rewriting of firmware takes place between the two, and the firmware is rewritten.

Abstract: Endpoint crashes in a real time communication system are detected by a home server providing presence and other services to the endpoint upon receipt of an error message from an access server between the endpoint and the home server. The home server uses a cookie inserted into a dialog between itself and the endpoint identifying the endpoint, a session state created by the access server identifying the endpoint, or a transaction state maintained by the home server to look up the endpoint associated with the error message. Race conditions occurring when an endpoint crashes and recovers rapidly can be avoided employing a timestamp or sequence number incremented for each new endpoint registration and comparing a current timestamp or sequence number to the stored one before updating records at the home server. By notifying other subscribers about crashed endpoints, routing fidelity is enhanced.

Abstract: A method, computer program product, and data processing system for detecting and identifying data crossover errors in servlet code are disclosed. According to a preferred embodiment, techniques of aspect-oriented programming (AOP) are used to instrument JAVA Servlet code to detect potential data crossover errors. Specifically, pointcuts are defined to intercept both the association follow an object with a particular session and the “getting” and “setting” of such objects. Advice code associated with these pointcuts is used to update and/or consult a “collator” data structure, which is used to determine if an object or variable associated with one session is being accessed by a different session. In a preferred embodiment, the AspectJ aspect-oriented programming language/system is used to define the pointcuts and advice code.

Abstract: A system and method are provided for detecting and recovering from errors in a control store memory of an electronic data processing system. In some cases, errors in the control store memory are detected and recovered from without any required interaction with an operating system of the data processing system. Thus, errors in the control store memory can be handled seamlessly and efficiently, without requiring a maintenance technician, or in some cases, a specialized operating system routine, to help diagnose and fix the error.

Abstract: A method and apparatus for detecting soft errors in a storage subsystem is provided. Write data generated for a write operation in a first controller is concurrently generated in a second controller and written to a storage device by the first controller. Soft errors are detected by comparing the two sets of write data by comparing respective checksums or the write data read back from the storage device by the second controller.

Abstract: A timing controller includes a control unit, an error signal generating unit, and an operation detecting unit. The control unit transfers a plurality of input data and outputs a plurality of completion signals according to transfer states of the respective data. The error signal generating unit generates a plurality of error signals with different waveforms, and the operation detecting unit selectively outputs one of the plurality of error signals in response to the plurality of completion signals.

Abstract: Described are techniques for obtaining configuration information and conditionally executing a system call in accordance with a specified configuration state. A host issues a request for configuration information from a data storage system. The data storage system maintains a separate table of configuration information representing a configuration state of the data storage system. The host receives a response including a custom value indicating the current configuration state. The host may issue a request to the data storage system to conditionally execute a call if the data storage system is in a configuration state corresponding to the custom value.

Abstract: Provided is a compensating device for a received data can be used in a wide application by a single apparatus for various wiring configurations and transmission media.

Abstract: Input/output processing is facilitated by readily enabling access to information associated with input/output processing. This information includes status information and measurement data provided by a control unit executing input/output commands. The status and measurement data are provided in a status control block identified in a transport control word, which is further used to specify a location in memory that includes the input/output commands to be executed.

Abstract: The use of a simple (e.g., magnitude comparator) circuit, and of a flag bit, for detecting and preventing errors from occurring in the FSM state bits that could otherwise cause the system to hang. Preferably, the flag bit is set with all the valid state transitions, and a magnitude comparator (for instance) is used to continuously monitor the value of the current state bits. When a FSM state transition occurs based on the flag bit and the output of the magnitude comparator, a potential error condition can be detected and the FSM transition can be blocked or the FSM can be safely transitioned into a predetermined “reset state”.

Abstract: Embodiments of the present invention relate to systems and methods for optimizing and reducing the memory requirements of state machine algorithms in pattern matching applications. Memory requirements of an Aho-Corasick algorithm are reduced in an intrusion detection system by representing the state table as three separate data structures. Memory requirements of an Aho-Corasick algorithm are also reduced by applying a banded-row sparse matrix technique to the state transition table of the state table. The pattern matching performance of the intrusion detection system is improved by performing a case insensitive search, where the characters of the test sequence are converted to uppercase as the characters are read. Testing reveals that state transition tables with sixteen bit elements outperform state transition tables with thirty-two bit elements and do not reduce the functionality of intrusion detection systems using the Aho-Corasick algorithm.

Abstract: One or more computer-readable media store executable instructions that, when executed by processing logic, perform parallel processing. The media store one or more instructions for receiving one or more portions of an inner context of a program created for a technical computing environment, allocating one or more portions of the inner context of the program to two or more labs for parallel execution, receiving one or more results associated with the parallel execution of the one or more portions from the two or more labs, and providing the one or more results to an outer context of the program.

Abstract: A portable electronic device includes a storage unit in which information indicating correct process contents is stored. A reception unit of the portable electronic device receives a command for requesting a process from an external device, and the portable electronic device determines whether or not process contents to be executed according to the received command are matched with process contents stored in the storage unit. When it is determined that process contents according to the received command are matched with process contents stored in the storage unit, the portable electronic device executes a process according to the command received by the reception unit.

Abstract: An operational optical transceiver configured to preserve a portion of volatile memory during a warm reboot process. The optical transceiver includes a persistent memory, a processor, and a system memory. The system memory includes a preserved memory space. The optical transceiver loads microcode from the persistent memory to the system memory without writing into the preserved memory space. The processor processes the microcode and writes certain information into the preserved memory space that will be preserved during a warm reboot. The optical transceiver may then initiate a warm reboot and load microcode from the persistent memory to the system memory that overwrites the existing microcode. However, the information written in the preserved memory space is not overwritten by the microcode loaded from the persistent memory. In this way, a portion of the information contained in the system memory prior to the warm reboot is preserved.