Of Memory Patents (Class 714/6.1)
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Patent number: 10616144Abstract: A buffer logic unit of a packet processing device including a power gate controller. The buffer logic unit for organizing and/or allocating available pages to packets for storing the packet data based on which of a plurality of separately accessible physical memories that pages are associated with. As a result, the power gate controller is able to more efficiently cut off power from one or more of the physical memories.Type: GrantFiled: March 30, 2015Date of Patent: April 7, 2020Assignee: Cavium, LLCInventor: Enrique Musoll
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Patent number: 10614098Abstract: A system and method for determining consensus within a distributed database are provided. According to one aspect, a protocol is provided that reduces or eliminates heartbeat communication between nodes of a replica set. Nodes may communicate liveness information using existing database commands and metadata associated with the database commands. According to another aspect, improved systems and methods are provided for detection of node failures and election of a new primary node.Type: GrantFiled: May 25, 2017Date of Patent: April 7, 2020Assignee: MongoDB, Inc.Inventors: Eliot Horowitz, Andrew Michalski Schwerin, Siyuan Zhou, Eric Andrew Milkie
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Patent number: 10592329Abstract: A fault tolerant operating method and an electronic device using the same are provided. The method includes: performing a first procedure by a first executive file installed in the electronic device; when an error occurs to cause the first procedure to abort, sending an aborted notification to a fault tolerant module by an operating system (OS) and obtaining an aborted address information of the first procedure by the fault tolerant module; and sending the aborted address information to the OS by the fault tolerant module, such that the OS calls the first executive file to continue executing the first procedure based on the aborted address information.Type: GrantFiled: September 1, 2017Date of Patent: March 17, 2020Assignee: Acer IncorporatedInventor: Kuan-Ju Chen
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Patent number: 10592438Abstract: Technologies are disclosed herein that allow configuration of firmware by a firmware configuration device connected to a target computer. The firmware configuration device may emulate keystroke and/or mouse movement data to transmit firmware configuration data to the target computer. The target computer can also transmit status information and/or commands through keyboard status light signals.Type: GrantFiled: November 3, 2015Date of Patent: March 17, 2020Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLCInventors: Kai Yau, Muthu Kumar Sathiyanesan
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Patent number: 10567507Abstract: A message processing method and apparatus on a cloud computing platform, and a message processing system on a cloud computing platform are provided. In the message processing method, after an input request message sent to an active server and a standby server is received, the input request message is sent to all active servers and standby servers. After input response messages returned by the active server and the standby server are received, one of the input response messages is sent to an external device.Type: GrantFiled: April 7, 2017Date of Patent: February 18, 2020Assignee: Huawei Technologies Co., Ltd.Inventor: Jian Zhu
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Patent number: 10496295Abstract: A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes includes a first plurality of storage nodes configured to communicate together as a first storage cluster and a second plurality of storage nodes configured to communicate together as a second storage cluster. Each of the first and second pluralities of storage nodes has nonvolatile solid-state memory for user data storage and each of the first and second pluralities of storage nodes is configured to distribute user data and metadata associated with the user data throughout a respective plurality of storage nodes such that a respective storage cluster maintains ability to read the user data, using erasure coding, despite a loss of one or more of the respective plurality of storage nodes.Type: GrantFiled: May 10, 2017Date of Patent: December 3, 2019Assignee: Pure Storage, Inc.Inventors: Par Botes, John Colgrove, John Hayes
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Patent number: 10459792Abstract: A method for a dispersed storage network begins by receiving one or more revisions of a data object for storage within a time frame and facilitating, for each revision of the one or more revisions, storage of the revision in the selected primary storage target including at least some encoded data slices of each set of encoded data slices of a plurality of sets of encoded data slices are stored in the selected primary storage target and, for each of the revisions, facilitating subsequent storage of remaining encoded data slices of each set of encoded data slices that were not stored in the selected primary storage target, and determining to store the remaining encoded data slices in another storage target, identifying a most recently stored revision of the data object and facilitating storage of the remaining encoded data slices of the most recently stored revision in the other storage target.Type: GrantFiled: February 23, 2018Date of Patent: October 29, 2019Assignee: PURE STORAGE, INC.Inventor: Jason K. Resch
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Patent number: 10437675Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices comprises one or more of a plurality of storage devices. A plurality of failure resilient address spaces are distributed across the plurality of storage devices such that each of the plurality of failure resilient address spaces spans a plurality of the storage devices. Each one of the plurality of failure resilient address spaces is organized into a plurality of stripes. Each one or more stripes of the plurality of stripes is part of a respective one of a plurality of forward error correction (FEC) protection domains. Each of the plurality of stripes may comprise a plurality of storage blocks. Each block of a particular one of the plurality of stripes may reside on a different one of the plurality of storage devices.Type: GrantFiled: August 2, 2017Date of Patent: October 8, 2019Assignee: Weka.IO Ltd.Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel
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Patent number: 10382446Abstract: A computerized method of managing a computer remote session operation, comprising providing a server for hosting application execution; configuring a number of predefined user accounts with low security permissions on said server, where said user accounts are not tied to any specific real user; Whenever a remote user requests to start a remote session, finding an available user account not currently in use on said computer, allocating it for the remote session and marking it as unavailable for subsequent session requests; Generating a one-time password for said user account; Communicating the assigned user account identifier and temporary password to client component on the user's side, either directly or through an intermediate broker, causing the client component to connect to the server using said user account identifier and temporary password; and, upon termination of the remote session, deleting the assigned user account's data and marking it as available again.Type: GrantFiled: May 23, 2016Date of Patent: August 13, 2019Assignee: Cameyo Inc.Inventor: Eyal Dotan
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Patent number: 10360370Abstract: Examples include an authenticated access to manageability hardware components in a computing device. Some examples enumerate manageability hardware components connected to an operative system kernel of the computing device, the manageability hardware components comprising a bus configuration space and the bus configuration space comprising memory map registers. Some examples include encoding an address stored in the memory map registers of each of the manageability hardware components to produce encoded address to control unauthorized accesses and locks the bus configuration space of each manageability hardware component by setting a read-only attribute to the bus configuration space. Some examples reprogram, in response to a request for access of an authenticated OS component to a manageability hardware component, the memory map register of the requested manageability hardware component with an accessible address to provide the authenticated OS component with access to the manageability hardware component.Type: GrantFiled: May 11, 2017Date of Patent: July 23, 2019Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LPInventors: Suhas Shivanna, Srinivasa Ragavan Rajagopalan, Nagaraj S Salotagi
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Patent number: 10360193Abstract: A system and method for archiving and analyzing data are disclosed. The system receives event data associated with a process; responsive to receiving the event data, determines process data associated with the process; generates process metadata from the event data and the process data; and stores the event data, the process data, and the process metadata in a data repository organized by the process metadata. Since the process data is determined early on in the data pipeline, the system can significantly reduce the amount of computation required for generating data analytics. The system is also capable of providing analytic results computed against a massive amount of archived data in real-time or near real-time as user requests are initiated. Efficiency of process mining and process optimization is also improved due to enhanced information stored for archived processes.Type: GrantFiled: March 24, 2017Date of Patent: July 23, 2019Assignee: Western Digital Technologies, Inc.Inventors: Sanhita Sarkar, Kannan J. Somangili, Shanker Valipireddy, Harold Woods
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Patent number: 10324664Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.Type: GrantFiled: March 24, 2016Date of Patent: June 18, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hirokazu So, Toshiyuki Honda, Shigekazu Kogita
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Patent number: 10303560Abstract: In accordance with embodiments of the present disclosure, a method may include, during a cache flush of data of a cache entry from a non-volatile memory to a storage resource, wherein the non-volatile memory is integral to a persistent write-back cache and storing the data in response to a power event associated with the write-back cache: (a) calculating a calculated parity value by undertaking a read-modify-write operation with respect to the storage resource; and (b) storing the calculated parity value and a target address of the storage resource associated with the calculated parity value in a parity journal.Type: GrantFiled: February 14, 2017Date of Patent: May 28, 2019Assignee: Dell Products L.P.Inventors: Chandrashekar Nelogal, Anand Nunna
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Patent number: 10289593Abstract: A hot swap management device includes a bus buffer, a hot swap switch, and a controller. The bus buffer is selectively coupled to a host system management bus of a server. The hot swap switch is coupled to the bus buffer and a hardware expansion device. The controller is coupled to the bus buffer and the hot swap switch. When the hot swap management device is coupled to a board system management bus of the server, the controller assigns a hardware address to the bus buffer. A computational unit of the server controls the hardware expansion device through the host system management bus according to the hardware address.Type: GrantFiled: January 7, 2018Date of Patent: May 14, 2019Assignees: Inventec (Pudong) Technology Corp., Inventec CorporationInventor: Po-Chung Chang
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Patent number: 10289507Abstract: A storage server comprises a plurality of storage devices arranged in a redundant storage array and a plurality of controllers. One of the controllers determines that a storage device in the redundant storage array has failed, determines a first portion of the storage device to be recovered by a first controller and determines a second portion of the storage device to be recovered by a second controller. The first controller recovers the first portion of the storage device and the second controller recovers the second portion of the storage device.Type: GrantFiled: October 26, 2016Date of Patent: May 14, 2019Assignee: Pavilion Data Systems, Inc.Inventors: Kiron Balkrishna Malwankar, Karagada Ramarao Kishore, Sundar Kanthadai
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Patent number: 10282135Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device operates based on a store data request from a requesting entity to dispersed error encode a data segment associated with a data object to generate a set of encoded data slices (EDSs). The computing device selects a write threshold number of EDSs based on a desired consistency level indicator and issues a write request to storage unit(s) (SU(s)). The computing device receives write response(s) from the SU(s) and, based on write response(s) received from the at least some of the SU(s), provides a store data response to the requesting entity.Type: GrantFiled: December 13, 2017Date of Patent: May 7, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: S. Christopher Gladwin, Jason K. Resch
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Patent number: 10228993Abstract: As the file system of an operating system program might be damaged by a crash, the file system is usually used neither for the selection of data to be dumped from a memory nor for the analysis of the dumped data, and all data contained in one or several areas of the memory are dumped. In order to preserve the integrity of the file system and enable its use after the crash, the memory is divided into a primary and a secondary memory section during a memory setup, file system data are transferred from the primary memory section to the secondary memory section widely out of the control of the operating system program, and a read access of a dump program is directed to the secondary memory section in order to select file system data to be dumped after the crash using error data.Type: GrantFiled: November 21, 2016Date of Patent: March 12, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Rafael Escobar Olmos, Jakob Christopher Lang, Angel Nunez Mencias, Albert Schirmer, Jochen Schweflinghaus
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Patent number: 10223033Abstract: Methods for use in a dispersed storage network (DSN) to coordinate data slice arrival times. In various examples, a DSN computing device receives a store data request, the store data request including a data object. A set of storage units associated with the store data request is identified, and the data object is dispersed storage error encoded to produce a plurality of sets of encoded data slices. One or more sets of write slice requests that include one or more sets of encoded data slices are also generated for reception by storage units of the set of storage units. For each set of write slice requests, a transmission schedule is determined for each write slice request such that the set of write slice requests arrives at corresponding storage units at substantially the same time frame. Each of the write slice requests is then transmitted in accordance with the transmission schedule.Type: GrantFiled: December 15, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventor: Jason K. Resch
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Patent number: 10204003Abstract: A failure region is specified when a failure occurs in a non-volatile semiconductor memory. When a device controller reads data stored in a specific page in a plurality of non-volatile semiconductor memories to detect an uncorrectable error (UE) of the data stored in the specific page, the device controller executes a diagnosis process including specifying a specific storage circuit that is a storage circuit including the specific page, reading data stored in a part of blocks of the specific storage circuit, and specifying, on the basis of a result of reading data stored in the block, a failure region in the specific storage circuit.Type: GrantFiled: August 27, 2014Date of Patent: February 12, 2019Assignee: Hitachi, Ltd.Inventors: Kenta Ninose, Takuji Itou, Fumio Yoshioka, Takashi Tsunehiro, Go Uehara, Shigeo Homma
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Patent number: 10200949Abstract: A technique is described herein for saving power (e.g., battery power) at a receiving device (e.g., wireless device) by having a transmitting device (e.g., wireless access node) add an indicator to repeated radio blocks, where the indicator can be used by the receiving device (e.g., wireless device) to stop monitoring one or more of the repeated radio blocks.Type: GrantFiled: September 8, 2017Date of Patent: February 5, 2019Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Paul Schliwa-Bertling, MÃ¥rten Sundberg, John Walter Diachina
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Patent number: 10191799Abstract: A memory system is configured to perform a test operation to determine a deviation of a target storage location's bit error rate response relative to a model. The memory system determines the deviation level by measuring data sets stored in the target storage location to determine an actual bit error rate value and another actual parameter value used to estimate bit error rate. The memory system obtains an estimated value from the model based on the actual values and identifies the deviation by comparing the estimated value with the actual values.Type: GrantFiled: December 29, 2016Date of Patent: January 29, 2019Assignee: SanDisk Technologies LLCInventors: Yonatan Karlik, Judah Gamliel Hahn, Ariel Navon, Alex Bazarsky, Ofer Shapira
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Patent number: 10192015Abstract: Methods of estimating yields of integrated circuits and methods of optimizing designs for the integrated circuits are provided. In a method of estimating a yield of an integrated circuit, critical paths are extracted from timing paths included in the integrated circuit by performing a static timing analysis for the integrated circuit. The critical paths are grouped into criticality sigma level groups according to criticality sigma levels of the critical paths, and the yield of the integrated circuit is determined based on numbers of the critical paths belonging to the respective criticality sigma level groups.Type: GrantFiled: April 12, 2016Date of Patent: January 29, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon-Su Kim, Kyoung-Hwan Lim, Cheol-Jun Bae
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Patent number: 10191809Abstract: One embodiment provides a method comprising arranging a first data chunk into a ring structure, tagging the first data chunk by appending extra data to the first data chunk, and performing erasure coding on the first data chunk utilizing only exclusive or (XOR) operations.Type: GrantFiled: August 17, 2016Date of Patent: January 29, 2019Assignee: International Business Machines CorporationInventor: Zhenxing Han
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Patent number: 10191816Abstract: A storage system according to certain embodiments includes a client-side repository (CSR). The CSR may communicate with a client at a higher data transfer rate than the rate used for communication between the client and secondary storage. During copy operations, for instance, some or all of the data being backed up or otherwise copied to secondary storage is stored in the CSR. During restore operations, copies of the data stored in the CSR is accessed from the CSR instead of from secondary storage, improving performance. Remaining data blocks not stored in the CSR can be restored from secondary storage.Type: GrantFiled: March 30, 2015Date of Patent: January 29, 2019Assignee: Commvault Systems, Inc.Inventors: Manoj Kumar Vijayan, Deepak Raghunath Attarde, Hetalkumar N. Joshi
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Patent number: 10175892Abstract: An adaptive read algorithm for accessing information stored on a nonvolatile medium. The nonvolatile medium can be organized as a plurality of storage units. A method of servicing a read request to the nonvolatile medium can include recording a history of read-retries for read requests to individual storage units of the nonvolatile medium. The method can include adapting a read algorithm for a read request to a particular storage unit based on the history of the read-retries for the read requests to the individual storage units of the nonvolatile medium.Type: GrantFiled: June 23, 2017Date of Patent: January 8, 2019Assignee: Amazon Technologies, Inc.Inventors: Kevin Kim, Jingyu Kang, Wenzhou Chen, Sujan Biswas, Truong Nguyen
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Patent number: 10169163Abstract: Provided are techniques for managing backup operations from a client system to a primary server and secondary server. A determination is made at the client system of whether a state of the data on the secondary server permits a backup operation in response to determining that the primary server is unavailable when a force failover parameter is not set. The client system reattempts to connect to the primary server to perform the backup operation at the primary server in response to determining that the state of the data on the secondary server does not permit the backup operation. The client system performs the backup operation at the secondary server in response to determining that the state of the secondary server permits the backup operation.Type: GrantFiled: September 15, 2016Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Matthew J. Anglin, David M. Cannon, Ken Eugene Hannigan, Kevin Patrick Hoyt, Erick Christian Kissel, Howard N. Martin, Michael Harry Segapeli
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Patent number: 10157005Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.Type: GrantFiled: September 30, 2016Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Robert C. Swanson, Tony S. Baker, Theodros Yigzaw, Chris Ackles, Celeste M. Brown
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Patent number: 10140053Abstract: A computer program product, system, and method for generating coded fragments comprises receiving, at a primary data protection appliance (DPA), an I/O write for a user volume; determining a distributed consistency group (DCG) associated with the user volume, the DCG having a plurality of replica copies; determining one or more secondary DPAs assigned to one or more of the replica copies; sending the I/O write from the primary DPA to each of the secondary DPAs; and applying, at each of the secondary DPAs, the I/O write to at least one of the replica copies assigned to the secondary DPA.Type: GrantFiled: September 26, 2016Date of Patent: November 27, 2018Assignee: EMC IP HOLDING COMPANY LLCInventors: Lev Ayzenberg, Leehod Baruch, Valerie Lotosh
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Patent number: 10135385Abstract: Systems and methods for local and master management units in a photovoltaic energy system. In one embodiment, a method implemented in a computer system includes sending a first identification code from a local management unit to a master management unit. The first identification code is associated with the first local management unit, and the local management unit controls a solar module. An authentication of the first identification code is received from the master management unit. In response to receiving the authentication, active operation of the local management unit is continued (e.g., for a set time period).Type: GrantFiled: August 4, 2015Date of Patent: November 20, 2018Assignee: TIGO ENERGY, INC.Inventors: Daniel Eizips, Shmuel Arditi, Ron Hadar, Maxym Makhota
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Patent number: 10127152Abstract: Provided are a computer program product, system, and method for populating a second cache with tracks from a first cache when transferring management of the tracks from a first node to a second node. Management of a first group of tracks in the storage managed by the first node is transferred to the second node managing access to a second group of tracks in the storage. After the transferring the management of the tracks, the second node manages access to the first and second groups of tracks and caches accessed tracks from the first and second groups in the second cache of the second node. The second cache of the second node is populated with the tracks in a first cache of the first node.Type: GrantFiled: October 20, 2015Date of Patent: November 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Matthew J. Kalos, Brian A. Rinaldi
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Patent number: 10108370Abstract: A method of reading a nonvolatile memory device including a plurality of pages coupled to a plurality of word lines and a plurality of bit lines, each of the plurality of pages including a data region storing a data and a flag region storing a flag, includes applying a first read voltage to a selected word line to generate first sensing data and a first sensing flag; applying a second read voltage to the selected word line to generate second sensing data and a second sensing flag, generating determination data by performing a logical operation on the first and second sensing data; determining a shift voltage based on the determination data and the read flag; and applying a third read voltage, based on the shift voltage, to the selected word line to generate a read data.Type: GrantFiled: February 17, 2017Date of Patent: October 23, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Makoto Hirano
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Patent number: 10102060Abstract: In a storage apparatus including a storage medium including a plurality of pages as a unit of reading and writing data, a first data block including a data block received from a higher-level device is generated, a second data block of a predetermined size including one or more undivided first data blocks is generated, a third data block in which a correction code is added to the second data block is generated, the third data block is stored in a page buffer, and one or more of the third data blocks stored in the page buffer is written in a page, which is a write destination, out of the pages of the storage medium.Type: GrantFiled: August 30, 2013Date of Patent: October 16, 2018Assignee: Hitachi, Ltd.Inventors: Hideyuki Koseki, Takashi Tsunehiro, Junji Ogawa, Nagamasa Mizushima, Atsushi Kawamura
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Patent number: 10095582Abstract: Methods for use in a dispersed storage network (DSN) to rebuild data. In various examples, at least one data segment of a data object is dispersed storage error encoded to produce a set of encoded data slices that includes an information dispersal algorithm (IDA) width number of encoded data slices, wherein the IDA width number is at least twice the number of storage units of a set of storage units utilized to store the data object. At least two encoded data slices are stored in each of the storage units. In response to detecting a storage error indicating an error slice, a partial threshold number of partial encoded data slices (generated by performing a partial encoding function on stored encoded data slices) are generated. The partial threshold number of partial encoded data slice responses are combined to produce a rebuilt encoded data slice corresponding to the error slice.Type: GrantFiled: December 19, 2017Date of Patent: October 9, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Greg R. Dhuse, Trevor J. Vossberg, Jason K. Resch
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Patent number: 10067879Abstract: Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.Type: GrantFiled: December 16, 2015Date of Patent: September 4, 2018Assignee: INTEL CORPORATIONInventors: Woojong Han, Andy M. Rudoff, Mark A. Schmisseur, Richard P. Mangold
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Patent number: 10031822Abstract: Various embodiments are generally directed to techniques for determining whether one node of a HA group is able to take over for another. An apparatus includes a model derivation component to derive a model correlating node usage level to node data propagation latency through and to node resource utilization from a first model of a first node of a storage cluster system and a second model of a second node of the storage cluster system, the first model based on a first usage level of the first node under a first usage type, and the second model based on a second usage level of the second node under a second usage type; and an analysis component to determine whether the first node is able to take over for the second node based on applying to the derived model a total usage level derived from the first and second usage levels.Type: GrantFiled: April 28, 2016Date of Patent: July 24, 2018Assignee: NETAPP, INC.Inventors: Alma Dimnaku, Curtis Hrischuk, Kevin Faulkner
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Patent number: 9946578Abstract: A method and apparatus for managing the persistent data of a pre-installed application in an elastic virtual machine instance is disclosed, the method comprising: in response to installing an application into a master virtual machine image, obtaining a persistent data point of a function component of the application, the persistent data point comprising a file directory for storing the persistent data of the function component; in response to launching an elastic virtual machine instance from the master virtual machine, creating a storage volume, attaching the storage volume to the elastic virtual machine instance, and mounting the storage volume to the file directory based on the persistent data point. Other features and aspects may be realized, depending upon the particular application.Type: GrantFiled: September 28, 2012Date of Patent: April 17, 2018Assignee: International Business Machines CorporationInventors: Yun Song Huang, Xin Peng Liu, Shaw-Ben Shi, Xia Zhang
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Patent number: 9921953Abstract: A hint bit detection and correction method and system that uses two additional bits as part of every cache directory. These bits represent the lwarx and stwcx instructions (larx disp, stcx disp). When a hint bit event occurs, depending the on combination of these two bits, there can be an indication of a hint bit error. Once a hint bit error is detected a software interrupt is issued and the hint bit correction method identifies and corrects the incorrect hint bit.Type: GrantFiled: September 9, 2015Date of Patent: March 20, 2018Assignee: International Business Machines CorporationInventors: Benjamin Carter Nowak, Guy Lynn Guthrie, Venkat R Indukuru
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Patent number: 9916114Abstract: A method for deterministic sharing of a plurality of processing resources with respect to one or more distributed network actionable items begins by the plurality of processing resources executing a scoring function using one or more properties of the one or more distributed network actionable items and one or more properties of each of the plurality of processing resources to produce a plurality of scoring resultants. The method continues with each of the plurality of processing resources independently determining a first priority processing resource of the plurality of processing resources based on a corresponding one of the plurality of scoring resultants for a first distributed network actionable item of the one or more distributed network actionable items. The method continues with the first priority processing resource assuming by responsibility for the first distributed network actionable item and executing one or more functions regarding the first distributed network actionable item.Type: GrantFiled: September 8, 2015Date of Patent: March 13, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Jason K. Resch
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Patent number: 9891847Abstract: A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for the secondary copy blocks may be used to increase the endurance for those blocks. Before programming the secondary copy, the trim parameters may be adjusted to increase endurance and after programming the secondary copy, the trim parameters may be adjusted back to the default value that is used when programming the primary copy.Type: GrantFiled: July 28, 2015Date of Patent: February 13, 2018Assignee: SanDisk Technologies LLCInventors: Narendhiran Chinnaanangur Ravimohan, Abhijeet Manohar, Muralitharan Jayaraman
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Patent number: 9892153Abstract: Techniques are described that determine occurrences of lost write by comparing version identifiers of corresponding replica data blocks and checkpoints of data files that include the data blocks. A method determines lost writes that may have occurred among a first set of data blocks and a second set of data blocks. Each data block in the first set of data blocks corresponds to a respective data block in the second set that is a version of data blocks in the first set. The data blocks in the first set and the second set are associated with version identifiers. The second set of data blocks is associated with a second checkpoint for which any version of a data block in the second set associated a version identifier below the second checkpoint has been acknowledged to a database server as having been written to persistent storage.Type: GrantFiled: December 19, 2014Date of Patent: February 13, 2018Assignee: Oracle International CorporationInventors: Yunrui Li, Mahesh Baburao Girkar, Hongyi Yao
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Patent number: 9891845Abstract: Embodiments of the present invention provide methods, program products, and systems for reusing a duplex storage medium resource. Embodiments of the present invention can be used to transition between duplex media by determining that a prior transition from a first duplex storage media to a second duplex storage media is being performed and reinitializing the second duplex storage media to receive, for storage, duplex data transferred from the first duplex storage media. Embodiments of the present invention can be used to reduce potential collisions with naming conventions and reduce unwanted delay that results in forcing an offload by managing the recovery medium and keeping it available through policy based medium changes.Type: GrantFiled: June 24, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Joseph W. Gentile, Jie Hou, Andrew M. Sica, Douglas M. Zobre
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Patent number: 9875052Abstract: Method and system are provided for storage capacity allocation. The method includes: providing a storage pool having multiple storage drive arrays; designating an initial available storage capacity in the storage pool; and allocating the remaining storage capacity in the storage pool to distributed spare space, wherein distributed spare space spreads portions of a spare drive across multiple storage drives in an array. The method also includes: monitoring an amount of available storage capacity as data is stored to the storage pool and determining when a threshold of a minimum available storage capacity is reached; and re-allocating one or more distributed spare drives from an array to available storage capacity when the threshold of the minimum available storage capacity is reached.Type: GrantFiled: March 15, 2016Date of Patent: January 23, 2018Assignee: International Business Machines CorporationInventors: John P. Agombar, Ian Boden, Gordon D. Hutchison, Lee J. Sanders
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Patent number: 9870222Abstract: An air-conditioning system is provided with an air-conditioning apparatus management apparatus and an air-conditioning apparatus which transmits and receives various signals to and from the air-conditioning apparatus management apparatus. The air-conditioning apparatus management apparatus manages the air-conditioning apparatus, an operational state of the air-conditioning apparatus management apparatus is linked to an operational state of the air-conditioning apparatus, and software set in the air-conditioning apparatus management apparatus is updated based on the operational state of the air-conditioning apparatus management apparatus.Type: GrantFiled: May 10, 2013Date of Patent: January 16, 2018Assignee: Mitsubishi Electric CorporationInventor: Mitsuhiro Sugimura
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Patent number: 9841900Abstract: A storage control apparatus, that controls a storage apparatus that includes a storage drive in which a plurality of logical volumes are set, includes a storage unit that stores load information for each of the plurality of logical volumes, and a control unit that determines to-be-rebuilt volumes, which are targets to be rebuilt, from the plurality of logical volumes, sequentially selects a logical volumes for which a volume-specific taken time is estimated, determines, for each selected logical volume, a volume-specific start time at which a rebuild will be started, estimates, by using the volume-specific start time and the load information about the selected logical volume, the volume-specific taken time for rebuilding the selected logical volume, and totals the volume-specific taken time estimated for each selected logical volume to calculate a total taken time taken for rebuilding the to-be-rebuilt volumes.Type: GrantFiled: July 23, 2015Date of Patent: December 12, 2017Assignee: FUJITSU LIMITEDInventors: Kazuhiro Urata, Kazuhiko Ikeuchi, Chikashi Maeda, Yukari Tsuchiyama, Takeshi Watanabe, Guangyu Zhou
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Patent number: 9792340Abstract: Each of a plurality of data items has an associated update time. Identifying updated data items comprises identifying those data items that have an update time later than a last synchronization time. The data items are updated such that each data item is associated with one of a plurality of update tokens. Each update token is associated with updates performed up to a respective bound period from a time at which the update token is superseded by a successive update token. The update tokens are allocated successively in a monotonic sequence. Data indicating a last synchronization time is received. An update token is identified that is associated with one or more updates performed relative to a point in time related to the last synchronization time by the bound period. Data items having an update time after the last synchronization time are identified on the basis of the identified update token.Type: GrantFiled: February 28, 2014Date of Patent: October 17, 2017Assignee: METASWITCH NETWORKS LTDInventors: Keith Wansbrough, Alistair Dundas
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Patent number: 9785501Abstract: A data storage device includes a non-volatile memory and a controller. A method includes writing a first logical page to a physical page of the non-volatile memory. In response to a multistate error indication satisfying a threshold, the method further includes rewriting the first logical page at the non-volatile memory. The multistate error indication is determined based on the first logical page.Type: GrantFiled: February 18, 2014Date of Patent: October 10, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Idan Alrod, Eran Sharon
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Patent number: 9778879Abstract: Writing data to storage utilizing a diverged thread for asynchronous write operations is provided. On a first thread, an analysis engine analyzes and identifies changed information to write to storage and an I/O manager copies the writes into buffers and places the buffers into a queue, while on a second thread, a flushless transactional layer (FTL) drive executes the writes to storage. By allowing the analysis to continue and enqueue writes on a first thread while the writes are written to storage on a second thread, the CPU and I/O of the system are utilized in parallel. Accordingly, efficiency of the computing device is improved.Type: GrantFiled: October 23, 2015Date of Patent: October 3, 2017Assignee: Microsoft Technology Licensing, LLCInventor: Marcus Eduardo Markiewicz
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Patent number: 9769748Abstract: A technique is described herein for saving power (e.g., battery power) at a receiving device (e.g., wireless device) by having a transmitting device (e.g., wireless access node) add an indicator to repeated radio blocks, where the indicator can be used by the receiving device (e.g., wireless device) to stop monitoring one or more of the repeated radio blocks.Type: GrantFiled: June 24, 2015Date of Patent: September 19, 2017Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Paul Schliwa-Bertling, MÃ¥rten Sundberg, John Walter Diachina
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Patent number: 9761326Abstract: According to one embodiment, a memory system includes: a non-volatile memory; a memory interface that reads a received word from the non-volatile memory; a decoder that decodes the received word; a control unit that predicts the number of error bits in the received word read from the non-volatile memory, predicts decoding time on the basis of the number of error bits predicted, and determines an operating clock frequency of the decoder on the basis of the predicted decoding time and requested decoding time being the decoding time requested; and a frequency control unit that supplies the operating clock frequency determined by the control unit to the decoder and supplies voltage corresponding to the operating clock frequency being determined to the decoder.Type: GrantFiled: March 9, 2016Date of Patent: September 12, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yu Nakanishi, Daisuke Iwai, Kiwamu Watanabe, Kenji Funaoka, Tetsuya Sunata, Keigo Hara, Marie Takada
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Patent number: 9740405Abstract: An information processing device includes a processor. The processor is configured to transmit to a tape drive a write request in one of a first mode and a second mode for accompanying data. The write request in the first mode requests to store the accompanying data in a buffer memory included in the tape drive without writing the accompanying data to a magnetic tape. The write request in the second mode requests to write data stored in the buffer memory and the accompanying data to the magnetic tape. The processor is configured to transmit a write request for one of multiple pieces of data in the first mode if a remaining amount of the buffer memory is larger than a predetermined threshold value, and in the second mode if the remaining amount is equal to or smaller than the predetermined threshold value.Type: GrantFiled: September 10, 2015Date of Patent: August 22, 2017Assignee: FUJITSU LIMITEDInventor: Yoshiaki Ochi