Abstract: Process control system and methods are disclosed. An example method includes operating a first cluster including first virtual machines and first servers and operating a second cluster including second virtual machines and second servers. The example method also includes storing first data from the first virtual machines at a first data store of the first cluster and storing a replica of the first data at a second data store of the second cluster. The example method also includes storing second data from the second virtual machines at the second data store and storing a replica of the second data at the first data store and identifying a failure of the first cluster. The method also includes, in response to the failure, restarting the first virtual machines using the second servers and the replica of the first data at the second data store.

Abstract: Approaches for a packet format for error reporting in a content addressable memory (CAM) device are disclosed. The CAM device may comprise a CAM array that includes a plurality of rows, each row including a plurality of CAM cells coupled to a match line, and an error notification circuit capable of forming a packet that indicates whether the CAM device is experiencing an error condition. If an error condition was experienced by the CAM device, the response packet may also indicate the type(s) of error that was encountered. Advantageously, information about any error condition experienced by the CAM device may be quickly ascertained by a host device in which the CAM device is incorporated.

Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

Abstract: The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a data request for a solid state memory; identifying a logical block grouping corresponding to the data request, wherein the logical block grouping indicates physical data storage blocks spanning at least two distinct memory units of the solid state memory; reading stored data and parity information from at least a portion of the physical data storage blocks spanning the at least two distinct memory units; and recovering data of at least one block of the logical block grouping based on the stored data and the parity information.

Abstract: Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.

Abstract: The present disclosure provides techniques for operating a tape drive. A method of operating a tape drive includes monitoring a parameter of the tape drive during a data access operation. The method also includes detecting an access failure. The method further includes selecting a treatment based on the parameter, applying the treatment, and performing a retry.

Abstract: A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response to the detection of the occurrence of the event. A system may include a storage resource and a power management module communicatively coupled to the storage resource. The storage resource may be disposed in an array of storage resources. The power management module may be operable to detect an occurrence of an event associated with the storage resource, and may be operable to transition the storage resource into a specified power state in response to the detection of the occurrence of the event.

Abstract: Torn write mitigation circuitry determines if a write operation to memory is in progress at or about a time of power loss. In response to the write operation being in progress at or about the time of the power loss, the torn write mitigation circuitry causes torn write data and metadata to be stored to a non-volatile cache. The torn write data comprise data left in a degraded or uncorrectable state as a result of the loss of power. The metadata describe the torn write data.

Abstract: A memory region can durably self-identify as being faulty when read. Information that would have been assigned to the faulty memory region can be assigned to another of that sized region in memory using a replacement encoding technique. For phase change memory, at least two fault states can be provided for durably self-identifying a faulty memory region; one state at a highest resistance range and the other state at a lowest resistance range. Replacement cells can be used to shift or assign data when a self-identifying memory fault is present. A memory controller and memory module, alone or in combination may manage replacement cell use and facilitate driving a newly discovered faulty cell to a fault state if the faulty cell is not already at the fault state.

Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a user area and a non-user area. The user area is generally enabled to store and retrieve data in a logical block address space of a host. The non-user area stores a failure-specific recovery routine. The controller may be communicatively coupled to the non-volatile memory. The controller is generally enabled, when operationally coupled to the host, (i) to respond to host commands to read and to write data into the user area of the non-volatile memory and (ii) upon detection of a predefined failure of a controller boot process, to respond to host read requests by returning the failure-specific recovery routine stored in the non-user area of the non-volatile memory.

Abstract: In an embodiment, a partition is executed at a primary server, wherein the partition accesses a first memory location at a first memory block address at the primary server. If a first corresponding memory location at a secondary server has an error, wherein the first corresponding memory location at the secondary server corresponds to the first memory location at the primary server, then an object is moved from the first memory location at the primary server to a second memory location at the primary server.

Abstract: According to one embodiment, a storage device has a plurality of memory modules and a memory controller. The memory controller has a first unit configured to receive data to be stored in the memory modules from a host device as a write data stream and transmit data read from the memory modules to the host device as a read data stream, a second unit having a plurality of subunits, each of which is configured to write data in one of the memory modules corresponding to the subunit and read data from one of the memory modules corresponding to the subunit, and a data stream converter configured to parallelize the write data stream into a plurality of data blocks each of which is to be stored in one of the memory modules and to serialize a plurality of data blocks read from the memory modules into the read data stream.

Abstract: In one embodiment, a system for dynamically allocating a ring buffer includes a processor and logic integrated with and/or executable by the processor, the logic being configured to divide a ring buffer into a first portion and a second portion after detecting an error condition in data read from a data storage medium, wherein the first portion is allocated for processing normal read and/or write requests, and wherein the second portion is allocated for processing error recovery procedure (ERP) requests. In another embodiment, a method for dynamically allocating a ring buffer includes dividing a ring buffer into a first portion and a second portion after detecting an error condition in data read from a data storage medium, wherein the first portion is allocated for processing normal read and/or write requests, and wherein the second portion is allocated for processing ERP requests.

Abstract: Provided is an operating method of a data processing system which includes a data storage device and a host device. The operating method includes reading data at the data storage device based on a request from the host device, and performing an error correction code (ECC) decoding operation on the read data, and performing an additional ECC decoding operation at the host device when the ECC decoding operation performed by the data storage device fails.

Abstract: Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: When an address indicating an access destination of a data storing unit, and a command indicating a content of a process for the address are input, block information corresponding to the input address is output from an information holding unit. Whether or not to execute the command for the address is decided on the basis of the output block information and the input command.

Abstract: A semiconductor memory device includes, a memory cell array configured to include a plurality of memory cells each having a plurality of logic pages, an error detector configured to detect a recovery target data among the data stored in the memory cell array, and output a logic page information of the recovery target data, a data recoverer configured to recover the recovery target data by using adjustment of a read reference voltage in response to the logic page information of the recovery target data, and a page buffer configured to read the recovery target data output from the memory cell array and write a recovered data output from the data recoverer in the memory cell array.

Abstract: Controlling a boot operation form an alternate operating system by pressing a single predetermined key or simultaneously pressing a set of unique keys on the keyboard which causes the computer system to reboot using the operating system on an attached drive to be booted. The user can recover operational use of their computer system when the internal system drive suffers a software application or operating system failure. An attached storage device containing a bootable operating system, an application program in the host computer that can detect the pressing of a single or set of unique keys on the keyboard which will then cause the application to process boot files and force a reboot of the operating system with the attached storage device as the boot device.

Abstract: Techniques for assigning memory reserved for high availability (HA) failover to virtual machines in high availability (HA) enabled clusters are described. In one embodiment, the memory reserved for HA failover is determined in each host computing system of the HA cluster. Further, the memory reserved for HA failover is assigned to one or more virtual machines in the HA cluster as input/output (I/O) cache memory at a first level.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The flash memory is capable of operating in a SLC mode and a non-SLC mode. The controller is configured to perform a first read operation to read a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host, and perform an adjustable read operation when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to enable the flash memory to operate in the non-SLC mode in the adjustable read operation, and write logic 1 into a most-significant-bit page corresponding to the first word line in the non-SLC mode to adjust voltage distribution of the first page.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure.

Abstract: In accordance with embodiments of the present disclosure, a method may comprise identifying one or more portions of the memory having defects. The method may also include storing one or more addresses in the memory defect list, each of the one or more addresses associated with a portion of the one or more identified portions. The method may further include indicating to components of an information handling system that the one or more identified portions are unusable such that the other components are prevented from allocating and using the one or more identified portions.

Abstract: An information processing device includes: a storage device that has a plurality of storage areas; a detection unit that carries out error detection from read data out of the storage area belonging to the storage device; a readout unit that, in a case that the detection unit detects an error, identifies an area where error occurrence is estimated including a storage area in which the data where the error is detected is written and carries out readout of data individually from each storage area in the identified area; and a movement unit that, in a case of detecting an error from the data read out by the readout unit, moves the data to another storage area.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that enable a controller of a storage device having storage media to perform one or more error recovery operations on the storage media, and to convey, while performing the one or more error recovery operations, a message indicating a status of the one or more error recovery operations to a host processor in communication with the storage device. Storage devices implementing embodiments of the present invention include hard disk drives and solid state disk drives.

Abstract: A method includes, in at least one aspect, receiving a command for a group of data units to be transmitted to a host in a first sequence; for each data unit of the group of data units, receiving an identifier of the data unit and a signal indicating that the data unit has been retrieved and processed for errors, wherein the identifiers and the signals are received in accordance with the group of data units being retrieved from one or more memory devices in a second sequence that is different from the first sequence; tracking the group of data units retrieved in the second sequence; determining, by processing circuitry, that the group of data units has been retrieved and processed for errors; and initiating transmission of the group of data units to the host in accordance with the first sequence.

Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.

Abstract: According to one embodiment, a memory device includes a semiconductor memory and a controller that controls the semiconductor memory. The controller includes a first command issuing module, second command issuing module, error correction module and control module. The first command issuing module is configured to issue a read command to the semiconductor memory. The second command issuing module is configured to issue a first command instructing a process that does not involve reading data from the semiconductor memory independently from the first command issuing module to the semiconductor memory. The error correction module is configured to correct an error contained in data supplied from the semiconductor memory. The control module is configured to control the error correction module, first command issuing module and second command issuing module.

Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.

Abstract: A method and a system for testing a storage system to which is applied a command or a sequence of commands. The storage system has a storage medium and a controller, and each command results in an outcome, and the method comprises: storing in a dataset; information related to the command and/or the sequence of commands including for each command: an address of the storage system the command is applied to, and an outcome of the command. When a sequence of commands is applied, the information stored in the dataset includes an outcome of the sequence of commands. This method further comprises selecting one or more commands from the dataset to be subsequently replayed when the outcome of the at least one command indicates an error.

Abstract: A token value is maintained based on an allowable number of low power transitions of a hard disk drive without adversely affecting reliability, compared to an actual number of low power transitions of said hard disk drive. The allowable number of low power transitions increases over the hard disk drive's lifetime. Before the hard disk drive performs a low power transition, the token is evaluated to determine if the hard disk drive is allowed to perform a low power transition. Low power transitions discussed include parking the head and spinning-down the hard disk drive.

Abstract: A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.

Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.

Abstract: A data processing device includes a cache having a plurality of cache lines. Each cache line has a lockout state that indicates whether an error has been detected for data accessed at the cache line. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. When a cache line is in a locked-out state, the cache line is not used by the cache. Accordingly, a locked-out cache line is not employed by the cache to satisfy a cache accesses, and is not used to store data retrieved from memory in response to a cache miss. In response to determining the detected error likely did not result from a hardware failure or other persistent condition, memory error management software can reset the lockout state of the cache line.

Abstract: This invention discloses a hard disk data recovery method, apparatus, and system. The method includes: recording a logical block address corresponding to erroneous data if an error is discovered when data is read from the hard disk; performing a recovery operation for data at a first physical block address corresponding to the logical block address according to a preset algorithm to obtain recovered data; and sending an instruction of writing the recovered data into the logical block address to the hard disk so that the hard disk writes the recovered data into the logical block address according to the instruction, where the logical block address corresponds to a remapped second physical block address. Therefore, the method repairs an erroneous sector or a bad block of the hard disk quickly and improves efficiency of repairing the erroneous sector of the hard disk or the bad block of the hard disk.

Abstract: A method and system is used in managing drive error information. An error is detected in connection with a drive. Error data associated with the drive error is collected in response to detecting the error. The error data is stored on the drive. The error data being sufficiently complete to allow a comprehensive evaluation of the error.

Abstract: New data storage devices and techniques are provided. In some aspects of the invention, a new remote supplementation based media and system are provided. A local file and control system comprises a data density distribution that varies depending on Media Depth. A remote supplementation source and control system are also provided in a common network with the local control system. The local control system reports local file attributes, authorization and factors impacting media depth in real time, and the supplementation control system delivers permanent and streaming data corrections, supplementation and format updates to the local control system. In additional aspects of the invention, a patterned reference media device aids in building the local data density distribution. In some embodiments, the 3D arrangement, or other attributes, of structural storage device elements may serve as the patterned reference device.

Abstract: A method may be performed in a data storage device that includes a memory including a three-dimensional (3D) memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.

Abstract: Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system may receive a command to write data in a memory of the memory system; determine a physical location of the memory that is associated with the data write; write data associated with the data write to the physical location; and store the physical location of the memory that is associated with the data write in a Tag cache. The controller may further identify a data keep cache of a plurality of data keep caches that is associated with the data write based on the physical location of the memory that is associated with the data write; update an XOR sum based on the data of the data write; and store the updated XOR sum in the identified data keep cache.

Abstract: Techniques, related to a flash memory device having a non-volatile memory array (NVM), for recovering from a write interrupt resulting from host-supplied memory voltage fault are disclosed. A memory controller is configured to control a response to an occurrence of the write-interrupt, the response including writing to the NVM, after the memory voltage is verified as being within an acceptable range, one or more of a safe copy of a portion of a first sector of upper-page data and a safe copy of a portion of a second sector of lower-page data, and terminating the write interrupt. Terminating the write-interrupt may include receiving new data from the host while avoiding sending an error message to the host.

Abstract: Disclosed is a fault repair apparatus capable of reducing time which fault repair processing needs. The fault repair apparatus according to an exemplary aspect of the invention includes, a detection unit that detects a fault in the integrated circuit being equipped with a memory storing configuration data (config-data), and a circuit element whose logic operation is defined by the config-data; and outputs fault information; a memory unit that memorizes a fault area specification table which correlates whether or not a description in the config-data related to the fault information exists in any of memory areas to identification information which identifies the memory area; a specification unit that specifies a failed memory area from the fault information and the fault area specification table; and a correction unit that, about the config-data stored in the failed memory area, detects and corrects error data which does not agree with an expected value.

Abstract: A storage module and method are disclosed for determining whether to back-up a previously-written lower page of data before writing an upper page of data. In one embodiment, a storage module receives a command to write an upper page of data to memory cells that have already been programmed with a lower page of data. The storage module determines whether a command to protect the lower page of data was previously received. The storage module backs-up the lower page of data in another area of the memory before writing the upper page of data to the memory cells only if it is determined that the command to protect the lower page of data was previously received. The storage module then writes the upper page of data to the memory cells.

Abstract: A storage controller includes: an error information management section configured to manage information in a plurality of addresses of a memory; and a refresh object determination section configured to determine a refresh object address in the memory based on the error information.

Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.

Abstract: A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.

Abstract: An approach to providing diagnostics of data storage medium units may be performed automatically without interruption to system operations. Upon receipt of one or more error messages occurring on a first data storage medium unit, data content from the first data storage medium unit may be copied to a second data storage medium unit. A system may operate using the second data storage medium unit while the first data storage medium unit is diagnosed for possible disk failure.

Abstract: A data scrubbing apparatus corrects disturb errors occurring in a memory cell array, such as SMT MRAM cells. The data scrubbing apparatus activates scrubbing of the data and associated error correction bits based on a number of errors corrected, at a power up of the memory cell array, or a programmed time interval. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data, the associated error correction bits, and reference bits. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Abstract: An electronic device capable of communicating with a plurality of servers includes a storage unit, a vibration unit, a control unit, and a communication unit. The storage unit stores a vibration threshold value. The vibration sensor senses a vibration magnitude of the electronic device. The control unit generates control signals and transmits the control signals to the servers via the communication unit to direct the servers to take certain actions to protect data when the vibration magnitude sensed by the vibration sensor is equal to or greater than the vibration threshold value.

Abstract: The subject disclosure is directed towards a data storage service that uses hash values, such as substantially collision-free hash values, to maintain data integrity. These hash values are persisted in the form of mappings corresponding to data blocks in one or more data stores. If a data error is detected, these mappings allow the data storage service to search the one or more data stores for data blocks having matching hash values. If a data block is found that corresponds to a hash value for a corrupted or lost data block, the data storage service uses that data block to repair the corrupted or lost data block.