Abstract: The present invention is an apparatus, system, and method for allowing a user to boot to an alternate operating system by pressing a single button on an externally attached storage device with a push button. The invention helps a user recover operational use of his computer system when the internal system drive suffers a software application or operating system failure. The invention consists of an attached storage device with a push button and supporting electronics capable of formatting and transmitting a recognizable data packet to the host computer and an application program in the host computer that can receive the data packet, process boot files, and force a reboot of the operating system with the attached storage device as the boot device.

Abstract: A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port.

Abstract: Components of a memory system, such as a memory controller and memory device, which detect accumulated memory read disturbances and correct such disturbances before they reach a level that causes errors. The memory device includes a memory array and a disturbance control circuit. The memory array includes a plurality of memory rows. Each memory row is associated with a disturbance warning circuit having a state that corresponds to an accumulated disturbance in the memory row. The disturbance control circuit determines, responsive to an activation of a memory row of the plurality of memory rows specified by a row access command, whether the disturbance condition is present in the memory row based on the state of the disturbance warning circuit associated with the memory row. If a disturbance condition is present, the disturbance control circuit causes a recovery operation to be performed on the memory row to reduce the accumulated disturbances.

Abstract: This disclosure includes a method for preventing errors in a DRAM (dynamic random access memory) due to weak cells that includes determining the location of a weak cell in a DRAM row, receiving data to write to the DRAM, and encoding the data into a bit vector to be written to memory. For each weak cell location, the corresponding bit from the bit vector is equal to the reliable logic state of the weak cell and the bit vector is longer than the data.

Abstract: A data storage system includes a memory circuit having memory cells and a control circuit. The control circuit is operable to receive data bits provided for storage in the memory cells. A subset of the memory cells have predetermined stuck-at faults. The control circuit is operable to compute a binomial coefficient for each of the predetermined stuck-at faults based on a bit position of a corresponding one of the predetermined stuck-at faults within the memory cells. The control circuit is operable to add together the binomial coefficients to generate an encoded number using a combinatorial number system. The control circuit is operable to generate a first set of redundant bits that indicate the encoded number. The first set of redundant bits are used to decode bits read from the memory cells to regenerate the data bits.

Abstract: In a method for managing serial attached small computer system interface (SAS) expanders using a host computer, the host computer connects to an SAS expander storage system through a redundant array of independent disks (RAID) card. The SAS expander storage system includes a first switch device, a first SAS expander, a second SAS expander, a second switch, a flash memory, and hard disk drives. The method controls the first switch device to switch the RAID card from the first SAS expander to the second SAS expander when the first SAS expander fails to function, controls the second switch device to switch the flash memory from the first SAS expander to the second SAS expander, and controls the first switch device to connect each of the hard disk drives to the second SAS expander.

Abstract: In one embodiment, a system includes logic adapted for receiving information relating to disk drive media (DDM) failures in an installed base of DDM across multiple virtual tape servers, a storage device adapted for storing the information relating to the DDM failures in a data repository, and a processor adapted for analyzing the information stored in the data repository to identify problems in an installed base of DDM, the analysis comprising analyzing comparative DDM failure data comprising vectors. In another embodiment, a method for managing DDM failures includes receiving DDM failure information in virtual tape servers, storing the DDM failure information in a data repository, and analyzing the information to identify problems in an installed base of DDM. Other systems, methods, and computer program products are also described according to more embodiments.

Abstract: A method, system and computer program product are provided for implementing dynamic random access memory (DRAM) failure scenarios mitigation using buffer techniques delaying usage of RAS features in computer systems. A buffer is provided with a memory controller. Physical address data read/write failures are analyzed. Responsive to identifying predefined failure types for physical address data read/write failures, the buffer is used to selectively store and retrieve data.

Abstract: Various embodiments of the present invention provide systems and methods for deriving data from a defective media region. As an example, a method for deriving data from a defective media region is disclosed that includes providing a storage medium and performing a media defect detection that indicates a defective region on the storage medium. A first data decode is performed on data corresponding to the defective region. The first data decode yields a first output. It is determined that the first output failed to converge and based at least in part on the failure of the first output to converge, a second data decode is performed on the data corresponding to the defective region. The second data decode includes zeroing out any soft data corresponding to the defective region and providing a second output.

Abstract: Disclosed is a method and system for saving the copybacked data in a drive and continuing to rebuild on the same drive where the copy back was in progress when the online drive, where the copy back is not initiated, fails.

Abstract: Described embodiments track a read disturb limit of a solid-state media coupled to a media controller. The media controller receives a read operation from a host device. In response to the received read operation, the media controller determines one or more associated regions of the solid-state media accessed by the read operation and reads the associated regions to provide read data to the host device. Based on a probability value corresponding to each of the associated regions, the media controller selectively increments a read count of each of the associated regions. Based upon each read count, the media controller determines whether each region has reached a read disturb limit. If a given region has reached the read disturb limit, the media controller relocates data of the given region to a free region of the solid-state media. Otherwise, the media controller maintains the data in the given region.

Abstract: An apparatus comprising a non-volatile memory and a controller. The controller is coupled to the non-volatile memory and configured to (i) accumulate a read disturb count for a first region of the non-volatile memory, (ii) accumulate error statistics for a second region of the non-volatile memory, (iii) determine, based upon both the read disturb count and the error statistics, whether the first region has reached a read disturb limit, and (iv) in response to determining that the first region has reached the read disturb limit, relocate at least some data of the first region.

Abstract: The present disclosure includes systems and techniques relating to implementing fault tolerant data storage in solid state memory. In some implementations, a method includes receiving a request for data stored in a solid state memory, and identifying a logical block grouping for logical data blocks of the requested data, the logical data blocks corresponding to the solid state memory, and the logical block grouping comprising at least one physical data storage block from two or more solid state physical memory devices. The method also includes reading the stored data and a code stored in the identified logical block grouping, and comparing the code to the stored data to assess the requested data.

Abstract: A method begins by a processing module receiving data to store and determining error coding dispersal storage function parameters. The method continues with the processing module encoding at least a portion of the data in accordance with the error coding dispersal storage function parameters to produce a set of data slices. The method continues with the processing module defining addressable storage sectors within the single hard drive based on a number of data slices within the set of data slices to produce a set of addressable storage sectors. The method continues with the processing module storing data slices of the set of data slices in corresponding addressable storage sectors of the set of addressable storage sectors.

Abstract: A method includes, in a non-volatile memory that includes multiple memory blocks, defining a redundancy zone that includes at least an old parity block, a new parity block and multiple active blocks of which one block is defined as an open block. Data is stored in the redundancy zone and the stored data is protected, such that new input data is stored in the open block, redundancy information for the active blocks including the open block is stored in the new parity block, and the redundancy information for the active blocks excluding the open block is stored in the old parity block. Upon filling the open block and the new parity block, an alternative block is assigned to serve as the open block and the new parity block is assigned to serve as the old parity block.

Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.

Abstract: Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device.

Abstract: Embodiments of the invention are directed to providing detailed error reporting of data operations performed on a NVM storage device. In one embodiment, a controller interfaces with a NVM storage device including NVM storage coupled with a bridge. In one embodiment, the controller is provided physical, page-level access to the NVM via the bridge, and the bridge provides detailed error reporting of the data operations that the bridge performs on the NVM on behalf of the controller. For example, the bridge may provide page level reporting indicating which page(s) failed during a read operation. Detailed error reporting allows the controller to better understand the failures that occurred in a data access operation in the NVM. It also enables the controller to manage the flash media at the physical page/block level. In one embodiment, detailed error reporting also enables the return of discontinuous ranges of data with the error portions removed.

Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.

Abstract: Scheduling workloads based on detected hardware errors is provided. In response to determining that a hardware error is detected, it is determined whether the hardware error is a cache error. In response to determining that the hardware error is a cache error, it is determined whether execution of a workload on a processor is changing contents of a cache associated with the cache error more than a threshold value. In response to determining that the execution of the workload on the processor is changing the contents of the cache associated with the cache error more than the threshold value, it is determined whether the cache associated with the cache error is private to a core in the processor. In response to determining that the cache associated with the cache error is private to a core, the execution of the workload is scheduled on a different core of the processor.

Abstract: A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response to the detection of the occurrence of the event. A system may include a storage resource and a power management module communicatively coupled to the storage resource. The storage resource may be disposed in an array of storage resources. The power management module may be operable to detect an occurrence of an event associated with the storage resource, and may be operable to transition the storage resource into a specified power state in response to the detection of the occurrence of the event.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: Memory devices and methods are described that include serially chained memory devices. In one or more of the configurations shown, a serial chain of memory devices includes a number of memory devices, and an error recovery device at an end of the chain. In one configuration shown, the serial chain of memory devices includes a chain of devices where each device is a stacked die memory device. Methods are described that show using the error recovery device in write operations and data recovery operations.

Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

Abstract: Data is buffered for concurrent writing to tape. For a magnetic tape drive having a magnetic head with multiple sets of transducers; a drive mechanism configured to pass a magnetic tape past the magnetic head; interfaces from two different hosts; and at least one buffer configured to buffer data; and a control; the buffering comprises receiving data from two different hosts at the interfaces; buffering the received data in separate buffer space of the buffer(s) associated with each host, and adjustably size the separate buffer space for each host in accordance with a data transfer rate of the host associated with the separate buffer space; and concurrently writing data from the separate buffer spaces with the magnetic head to separate partitions of the magnetic tape.

Abstract: In one embodiment of the invention, a flash-based/solid-state storage system with an implemented data redundancy scheme such as RAID is configured to hold parity data in a volatile memory such as RAM and write such parity data to the non-volatile flash media when a full stripe of data has been written to the media. Other embodiments in certain situations force an early write of the parity for a partial stripe that has not been fully written to the non-volatile media. Those situations may include a data access error on data in a partial stripe and a detected power loss event with a partial stripe present. Embodiments are directed to writing additional data with the parity data for the partial stripe and then later using the additional data in data recovery. This approach allows the controller to easily detect the presence of a partial stripe and handle such a stripe accordingly.

Abstract: A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.

Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.

Abstract: A method, system and computer program product are provided for implementing command timing adjustments to alleviate Dynamic Random Access Memory (DRAM) failures in a computer system. A predefined DRAM failure is detected. Responsive to the detected failure, a set of timers is adjusted for controlling predetermined timings used to access the DRAM. Responsive to the failure being resolved by the adjusted set of timers, checking for a predetermined level of performance is performed.

Abstract: Processing for file system volume error detection and processing for resultant error correction are separated to support system availability and user satisfaction. File system volumes for storing data structures are proactively scanned while the volumes remain online to search for errors or corruptions thereon. Found errors are scheduled to be corrected, i.e., spot corrected, dependent on the severity of the identified errors, error correction scheduling and/or at the determination of a file system administrator and/or user, to assist in maintaining minimal user and file system impact. When spot correction is initialized, one file system volume at a time is taken offline for correction. Spot correction verifies prior logged corruptions for the offline volume, and if independently verified, attempts to correct the prior noted corruptions. Volumes are retained offline only for the time necessary to verify and attempt to correct prior noted volume corruptions.

Abstract: Provided are a computer program product, system, and method for recovering a volume table and data sets from a corrupted volume. Data corruption is detected in a volume having data sets. A volume table having information on the data sets allocated in the volume is diagnosed. A backup volume table comprising a most recent valid backup of the volume table is accessed from a backup of the volume in response to determining that the diagnosed volume table is not valid. Content from the backup volume table is processed to bring to a current state in a recovery volume table for a recovery volume. The data sets in the volume are processed to determine whether they are valid. The valid data sets are moved to the recovery volume. A data recovery operation is initiated for the data sets determined not to be valid.

Abstract: A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme without negatively impacting latency and design complexity. Embodiments of the present disclosure utilize an ECC scheme which leaves up to extra 2B for metadata storage by changing the error detection and correction process flow. The scheme adopts an early error detection mechanism, and tailors the need for subsequent error correction based on the results of the early detection.

Abstract: The present disclosure includes systems and techniques relating to solid state drive controllers. In some implementations, a device includes a buffer that holds a block of data corresponding to a command from a host. The command identifies the block of data and a logical sequence in which the identified block of data is to be transmitted. In response to the command, a data retriever included in the device retrieves the portions of the block of data from non-volatile memory units in a retrieval sequence that is different from the logical sequence. When the device receives multiple commands identifying multiple blocks of data, the device services the commands in parallel by retrieving portions of blocks of data identified by both commands.

Abstract: Systems and methods for reading and writing a set of data using a journaling service are provided. The journaling service may be used to identify and record data storage operations associated with one or more shares of data stored in one or more share locations. The journaling service may use logs to record each of the read and write requests to the share locations. In some embodiments, the log may be a queue data structure that stores information associated with failed data storage operations. In some embodiments, the journaling service may leverage both memory and disk storage in order to maintain the journaling queue. In some embodiments, the journaling queue may maintain information associated with the state of each share location. In some embodiments, this information may be used by the journaling service to determine when to monitor and record information regarding data storage operations associated with the share locations.

Abstract: A method is disclosed for recovering data associated with a damaged file stored in a NAND gate array memory. The method includes the steps of: identifying all meta data associated with the damaged file; identifying each logical block address of all identified meta data; collecting all physical block addresses associated with one of the identified logical block addresses or the identified meta data; counting in a replace table (ReplTable) a number of matches to a physical block address of the damaged file for each physical block address of the damaged file; choosing a block in a linked list that corresponds to the physical block address of the block in the linked list; and linking all chosen blocks to form a replicated file.

Abstract: Embodiments provide systems and methods for archive verification of media in a library. A method of archive verification may comprise loading a specified media into a drive at intervals, sending one or more commands to the drive, wherein the drive attempts to read the specified media or data on the specified media in accordance with the one or more commands, collecting data associated with the specified media from the drive and determining the readability of the specified media or data on the specified media.

Abstract: Systems and methods are disclosed for storing the firmware and other data of a flash memory controller, such as using a RAID configuration across multiple flash memory devices or portions of a single memory device. In various embodiments, the firmware and other data used by a controller, and error correction information, such as parity information for RAID configuration, may be stored across multiple flash memory devices, multiple planes of a multi-plane flash memory device, or across multiple blocks or pages of a single flash memory device. The controller may detect the failure of a memory device or a portion thereof, and reconstruct the firmware and/or other data from the other memory devices or portions thereof.

Abstract: The disclosure is related to monitoring a portable electronic device to detect an occurrence of a power event. A command can be sent to a data storage device to initiate a maintenance procedure on the data storage device. In a particular embodiment, a method includes monitoring a portable electronic device to detect an occurrence of a power event. The method also includes selectively sending a command to a data storage device to initiate a maintenance procedure on the data storage device when the occurrence of the power event is detected.

Abstract: A method begins with a processing module determining a retrieval threshold for retrieving a set of encoded data slices from a dispersed storage network (DSN). The set of encoded data slices represents data encoded using a dispersed storage error encoding function having a number of encoded data slices in the set of encoded data slices equal to or greater than a decode threshold and the retrieval threshold is equal to or greater than the decode threshold. The method continues with the processing module issuing data retrieval requests to the DSN for the set of encoded data slices and receiving encoded data slices of the set of encoded data slices to produce received encoded data slices. The method continues with the processing module decoding the received encoded data slices to recapture the data when a number of received encoded data slices compares favorably to the retrieval threshold.

Abstract: A memory device electrically connectable to a host circuit receives, from the host circuit, data including a first actual data to be written into the first memory area; acquires first parity data associated with the first actual data; generates second actual data that is a copy of the first actual data, and second parity that is a copy of the first parity data; writes the first actual data and the first parity data into the first memory area, and writes the second actual data and the second parity data into the second memory area; and reads the first actual data, the first parity data, the second actual data, and the second parity data from the data memory section for transmission to the host circuit.

Abstract: Perceived corruptions encountered on file system volumes, and which cannot be initially remedied online, are processed to verify whether they are true, existing volume data structure corruptions or, alternatively, false positives. Upon the verification of one or more of a volume's corruptions, error scanning is performed to check for, and attempt to remedy online, all the existing corruptions on the volume. Subsequent to error scanning processing, if one or more verified corruptions continue to exist on a file system volume, at file system boot up time spot corruption correction is performed to attempt to remedy the existing, verified corruptions on the volume. Spot corruption correction is performed to attempt to correct verified data structure corruptions on a volume of the file system while the volume is maintained offline for the time necessary to attempt to correct its prior identified corruptions.

Abstract: A system for booting a processor from NAND flash, comprising a NAND agnostic boot controller and a NAND flash device, wherein the NAND flash device further comprises a boot wrapper storing boot code in a predetermined format.

Abstract: The embodiments described herein generally relate to methods and systems for using an extended patching procedure for correction or repair of logical data portions, pages, or sectors of a computer data storage device. The extended patching procedure targets for repair not only the page(s) appearing to be defective or unusable based on a failed read operation for a data transfer request, but also additional pages. Determining the additional pages to include for automatic patching is based on: statistical distribution analyzes to include pages within the physical or logical vicinity of the original page, information about the underlying storage device technology or Input/Output (I/O) subsystem, and/or historical data about error conditions for areas related to the original page. Preemptively patching pages based on extended page lists improves system performance by reducing the total number of costly repair processes and by avoiding situations involving correction actions that fail to resolve.

Abstract: A memory system comprises a flash memory and a memory controller. The flash memory comprises a plurality of memory blocks. The memory controller performs a read retry operation on a memory block containing an uncorrectable read error until an accurate data value is read from the memory block. The memory controller then controls the flash memory to perform an erase refresh operation on the memory block.

Abstract: Embodiments relate to providing error recovery in a storage system that utilizes data redundancy. An aspect of the invention includes monitoring plurality of storage devices of the storage system and determining that one of the plurality of storage devices has failed based on the monitoring. Another aspect of includes suspending data reads and writes to the failed storage device and determining that the failed storage device is recoverable. Based on determining that the failed storage device is recoverable, initiating a rebuilding recovery process of the failed storage device based on determining that the failed storage device is recoverable and restoring data reads and writes to the failed storage device upon completion of the rebuilding recovery process.

Abstract: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.

Abstract: Data structure errors, or corruptions, identified during, e.g., normal computing device system processing, file system processing or user access processing, are verified prior to the file system identifying the error for offline correction or notifying the user or system administrator a data structure error exists. Identified data structure corruptions are verified while the file system volumes are maintained online and otherwise accessible to other processing tasks and user access. Verified data structure corruptions are logged for further corrective processing. Data structure corruptions that cannot be verified, i.e., false positives, are not further processed and are not identified to file system administrators or users as corruptions, freeing the file system to concentrate on normal processing and true, verifiable errors.

Abstract: A flash memory control circuit including a microprocessor unit, a first interface unit for connecting a flash memory, a second interface unit for connecting a computer host, an error correcting unit, a memory management unit, and a marking unit is provided. The memory management unit divides each page in the flash memory into a plurality of data bit areas, and a plurality of redundancy bit areas and a plurality of error correcting bit areas corresponding to the data bit areas, wherein each of the data bit areas has a plurality of sectors for respectively storing a sector data. The marking unit stores a data accuracy mark corresponding to each sector data in the corresponding redundancy bit area to record the status of the sector data. Thereby, the flash memory controller can effectively identify error data in the flash memory by using the error correcting codes and the data accuracy marks.

Abstract: In one embodiment, an apparatus includes memory comprising a first portion in which data contained therein is mirrored and a second portion wherein data contained therein is not mirrored, a memory allocator for allocating the first portion of the memory to critical data and allocating the second portion of the memory to non-critical data, and a processor for mirroring the critical data and receiving an indication of a memory error. If the memory error occurs in the first portion of the memory, a mirrored copy of the critical data is used. If the memory error occurs in the second portion of the memory, the memory error is contained so that the apparatus can continue to operate programs using the memory not affected by the memory error.

Abstract: An information processing apparatus includes a memory, and a processor that executes a process in the memory. The process includes detecting a sign of a fault of a storage device that prohibits write access to a storage area of the storage device and permits read access to the storage area during a fault, and storing a copy of data to be written to the storage device as first copy data in the memory when the sign of a fault is detected.