Of Memory Patents (Class 714/6.1)
  • Patent number: 8001425
    Abstract: A storage subsystem has a plurality of storage devices. An indication of failure of at least one of the plurality of storage devices is detected. In response to detecting the indication of failure, monitoring is performed for a further condition. According to the monitored further condition, it is determined whether the at least one storage device has failed or whether communication has been lost to the storage subsystem. In response to determining that communication has been lost, state information of the storage subsystem is preserved to enable restoration of the storage subsystem after communication to the storage subsystem is recovered.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: August 16, 2011
    Assignee: Hewlett-Packard Development Company, L.P,
    Inventor: Daniel J. Mazina
  • Patent number: 7996710
    Abstract: A method is provided for managing defects in a semiconductor memory system having a plurality of addressable locations. In the method, a first plurality of the addressable locations is allocated as in-use locations, and a second plurality of the addressable locations is allocated as spare locations. A plurality of sets of the in-use locations, wherein each of the sets is associated with a memory defect, is determined. At least one of the sets includes a different number of in-use locations than another of the sets. Each of the sets of the in-use locations is associated with at least one corresponding set of the spare locations. Each of a plurality of data requests that is associated with one of the sets of the in-use locations is directed to the at least one corresponding set of the spare locations.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: August 9, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dheemanth Nagaraj, Larry J. Thayer
  • Patent number: 7996725
    Abstract: A method for monitoring the status of a memory device is disclosed. The method includes, during operation of the memory device, exercising a first portion of the memory device more than at least one other portion of the memory device in order to induce an accelerated rate of aging of the first portion. The first portion is monitored to detect at least a potential for a failure in the first portion. According to the method, in response to monitoring the first portion, at least one corrective action is performed. Apparatus and computer readable media are also disclosed.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: August 9, 2011
    Assignee: Nokia Corporation
    Inventors: Janne T. Nurminen, Kimmo J. Mylly, Matti K. Floman
  • Patent number: 7996712
    Abstract: A data transfer controller of the present invention can determine whether or not data has been correctly stored in a cache memory even when the data is not transferred to the cache memory in sequential order. Data inputted from a host is transferred to and stored in a prescribed area of the cache memory. First check data is created and stored for each block. A data consistency determination module reads out the data from the cache memory subsequent to the end of a data write, and creates second check data anew. By comparing the second check data against the first check data, it can be determined whether or not the data has been stored normally in the cache memory. The data consistency determination module can also determine the consistency of the data on the basis of the data address written to the cache memory.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventor: Susumu Tsuruta
  • Patent number: 7996611
    Abstract: Provided are a backup data management system and a backup data management method capable of facilitating the management of backup data that is multiplexed between different storage apparatuses. The backup data management system includes a storage apparatus having a volume to be used by a host computer, at least one storage apparatus having volumes, and a management computer. The management computer creates a copy pair so that a snapshot of the volume included in a backup group is stored in all the volumes included in the backup group, and sets all copy pairs included in the designated backup group to a PAIR status when there is a creation request of the snapshot of the volume.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Nakagawa, Masayasu Asano, Masayuki Yamamoto, Yuichi Taguchi
  • Patent number: 7992061
    Abstract: A method for testing a reliability of a solid-state storage medium is provided, wherein the solid-state storage medium has a plurality of blocks. First, a lifetime of each of the blocks of the solid-state storage medium is obtained. Then, an erase count of each of the blocks is obtained, and whether the erase count is greater than a predetermined erase count is determined. After that, those blocks having their erase counts greater than the predetermined erase count are accumulated to generate a problematic block number, and a test report is output.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: August 2, 2011
    Assignee: Industrial Technology Research Institute
    Inventor: Wen-Jun Zeng
  • Patent number: 7991988
    Abstract: A method for updating firmware in a communication device storing an original firmware in a first data area of a non-volatile memory includes receiving and storing a new firmware in a second data area of the non-volatile memory. The method comprises assigning a firmware other than the new firmware as a boot firmware for the communication device before verification of the new firmware. The new firmware is loaded and executed in response to a boot procedure of the communication device. If the new firmware is executable and causes the communication device to satisfy a predetermined boot up condition, the new firmware passes the bootability check, and the new firmware is assigned as the boot firmware. The new firmware is not assigned as the boot firmware if the new firmware does not pass the bootability check.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 2, 2011
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chien-Hua Chen
  • Patent number: 7992035
    Abstract: A response of a disk device during rebuild can be sped up. A disk array control device determines whether or not there is a normal read request during rebuild. If there is a read request during rebuild, data is read by sequentially switching a plurality of disk devices in a certain block size unit lower than a block size in which each disk device reads data during normal read.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Fujitsu Limited
    Inventors: Hidejiro Daikokuya, Mikio Ito, Kazuhiko Ikeuchi
  • Patent number: 7987383
    Abstract: A multiple node storage system cluster that allows for a takeover by a takeover node simultaneously with a failing node resetting its storage adapters is provided. A takeover monitor on the failing node initiates a “coredump” procedure by selecting a coredump disk. After selecting the coredump disk, the failing node determines the world wide name (WWN) of that disk and sends this information in a message across the cluster interconnect to the takeover node. In response to receipt of this message, the takeover node begins takeover procedures with respect to all disks except for the coredump disk. The failing node simultaneously resets its storage adapters and writes is memory to the coredump disk. The failing node later updates a completion header on that disk. The takeover node completes the takeover without waiting for the storage adapter reset, and subsequently reads the completion header and copies coredump information into its memory.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: July 26, 2011
    Assignee: NetApp, Inc.
    Inventors: Susan M. Coatney, Loellyn J. Cassell, Angel B. Aviles
  • Patent number: 7979736
    Abstract: A memory block having a plurality of parameter data including parameter data to be updated is read to a working area from a nonvolatile memory and, whether the plurality of parameter data is correct or not is checked on a basis of error detection data. When an error is detected, temporary updating data are generated in a working area by updating the parameter data to be updated to a specified parameter data and by updating data except the parameter data to be updated to an unspecified data that have no meaning, and then the temporary updating data are written into the nonvolatile memory.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: July 12, 2011
    Assignee: Nidec Sankyo Corporation
    Inventor: Tsutomu Baba
  • Publication number: 20110154102
    Abstract: Availability of an information system including a storage system that performs remote copy between two or more storage apparatuses and a host computer using such storage system is improved. A third storage apparatus including a third volume is coupled to a first storage apparatus, a fourth storage apparatus including a fourth volume is coupled to a second storage apparatus, the first and third storage apparatuses perform remote copy of copying data stored in a first volume to the third volume, the first and second storage apparatuses perform remote copy of copying data stored in the first volume to a second volume, and the third and fourth storage apparatuses perform remote copy of copying data stored in the third volume to the fourth volume.
    Type: Application
    Filed: March 3, 2011
    Publication date: June 23, 2011
    Inventors: Hiroaki AKUTSU, Takashige Iwamura, Kenta Ninose, Yasuo Watanabe, Yasutomo Yamamoto, Yoshiaki Eguchi, Hisao Homma
  • Patent number: 7966518
    Abstract: A method for repairing a neighborhood of rows in a memory array using a patch table is disclosed. First data to be stored in row N in a memory array of the memory device, second data, if any, stored in row N?1 in the memory array, and third data, if any, stored in row N+1 in the memory array are stored in a temporary storage area of a memory device. The first data is written in row N, and, in response to an error, the first data, the second data, if any, and the third data, if any, are written in respective rows in a repair area in the memory device. The addresses of rows N?1, N, and N+1 are added to a table stored in the memory device to indicate which rows in the repair area should be used instead of rows N?1, N, and N+1.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: June 21, 2011
    Assignee: SanDisk Corporation
    Inventors: Derek J. Bosch, Christopher S. Moore
  • Publication number: 20110145632
    Abstract: A method is provided for recovering from an uncorrected memory error located at a memory address as identified by a memory device. A stored hash value for a memory page corresponding to the identified memory address is used to determine the correct data. Because the memory device specifies the location of the corrupted data, and the size of the window where the corruption occurred, the stored hash can be used to verify memory page reconstruction. With the known good part of the data in hand, the hashes of the pages using possible values in place of the corrupted data are calculated. It is expected that there will be a match between the previously stored hash and one of the computed hashes. As long as there is one and only one match, then that value, used in the place of the corrupted data, is the correct value. The corrupt data, once replaced, allows operation of the memory device to continue without needing to interrupt or otherwise affect a system's operation.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Applicant: VMWARE, INC.
    Inventors: Carl A. WALDSPURGER, Dilpreet BINDRA, Gregory HARM, Patrick TULLMANN
  • Publication number: 20110145633
    Abstract: Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louie Arthur Dickens, Timothy A. Johnson, Craig Anthony Klein, Gregg Steven Lucas, Daniel James Winarski
  • Publication number: 20110138221
    Abstract: In a controller of a disk array device, when recovery from a power failure is detected, the controller instructs a reading section to transfer data in a burst mode using a large prefetch amount. When an error is detected, the controller causes the data to be transferred again for an area where the error is detected. Further, the controller designates different access ports for the reading section and an erasing section, and causes these sections to operate in parallel. The reading section reads cache data from a flash memory and stores the cache data in a cache memory. The erasing section uses the access port different from the access port of the reading section, to erase data that is stored in the flash memory and has been transferred by the reading section.
    Type: Application
    Filed: February 3, 2011
    Publication date: June 9, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Hanaoka, Nina Tsukamoto
  • Patent number: 7958390
    Abstract: A memory device for repairing a neighborhood of rows in a memory array using a patch table is disclosed. In one embodiment, circuitry in the memory device is operative to store, in a temporary storage area of the memory device, (i) first data to be stored in row N in the memory array, (ii) second data, if any, stored in row N?1 in the memory array, and (iii) third data, if any, stored in row N+1 in the memory array. The circuitry is operative to write the first data in row N in the memory array, and, in response to an error in writing the first data, to write the first data, the second data, if any, and the third data, if any, in respective rows in a repair area in the memory device. The circuitry is further operative to add the addresses of rows N?1, N, and N+1 to a table stored in the memory device.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: June 7, 2011
    Assignee: SanDisk Corporation
    Inventors: Derek J. Bosch, Christopher S. Moore
  • Publication number: 20110131444
    Abstract: This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.
    Type: Application
    Filed: December 2, 2009
    Publication date: June 2, 2011
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Bruce D. Buch, Ara Patapoutian, Bengt A. Ulriksson, Bernardo Rub
  • Publication number: 20110126043
    Abstract: Operating system (‘OS’)-firmware interface update recovery including determining, for each of a plurality of available OS-firmware interface images for booting a computer, whether each available OS-firmware interface image is corrupted or uncorrupted; setting, for each corrupted OS-firmware interface image, a predictive failure analysis (‘PFA’) bit in nonvolatile memory available to the OS-firmware interface update recovery module; selecting an uncorrupted OS-firmware interface image; initiating a boot for the computer with the selected OS-firmware interface image; determining whether a previous update to one of the available OS-firmware interface images was interrupted; and notifying a user that the previous update was interrupted if the previous update to one of the available OS-firmware interface images interrupted.
    Type: Application
    Filed: November 20, 2009
    Publication date: May 26, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul L. Anderson, William E. Atherton, Tu T. Dang, Michael C. Elles
  • Publication number: 20110093742
    Abstract: A storage apparatus connected to a storage device includes a storage module, a memory for storing data to be copied to the storage device, buffers for temporarily saving the data, redundantly, the saved data stored in one of the buffers being recoverable by the data stored in the rest of the buffers, and a control module for executing, storing the data of write request to the storage module and the memory, copying the data to the storage device, saving the data to the buffer when an using rate of the memory is greater than a predetermined rate, writing the saved data stored in the buffer to the memory when an using rate of the memory is not greater than the predetermined rate, detecting a failure of the buffers, and rebuilding the saved data stored in the one of the buffers based on an using state of the buffers.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 21, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Yoshinari SHINOZAKI
  • Publication number: 20110093741
    Abstract: A method for recovering basic input/output system (BIOS) in a computer system is disclosed. The computer system includes a host unit, a control unit, and a first storage device. The control unit is utilized for controlling system power provided for the host unit. The host unit is utilized for accessing a BIOS code stored in the first storage device to perform a boot process. The method includes turning the system power off when the computer system has a recovery requirement, restoring a backup BIOS code into the first storage device, and turning the system power on to make the host unit access the restored BIOS code in the first storage device for performing the boot process.
    Type: Application
    Filed: April 20, 2010
    Publication date: April 21, 2011
    Inventors: Te-Yu Liang, Cheng-Te Chen, Wen-Chun Tsao, Szu-Wei Pan
  • Publication number: 20110072301
    Abstract: A system includes a group of devices and a shared memory that is partitioned into blocks that are capable of being allocated to the group of devices using linked lists. The system also includes check logic configured to store a group of bits, where each bit corresponds to one of the blocks, and counter logic configured to count for a predetermined period of time. The system further includes logic configured to clear the group of bits stored in the check logic, cause the counter logic to count for the predetermined period of time, monitor a de-allocation of the blocks in the shared memory, set, for each of the blocks that is de-allocated during the predetermined period of time, the corresponding bit in the check logic, identify, after the predetermined period of time, one or more bits that have not been set, and mark the blocks corresponding to the one or more bits as available for allocation.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 24, 2011
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Debashis BASU, David OFELT
  • Publication number: 20110072300
    Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 24, 2011
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Hubert Rousseau
  • Publication number: 20110072299
    Abstract: A system to check for memory leaks in storage may include a data processing application executing via a computer processor, and storage to store data generated by the data processing application. The system may also include a monitor executing via the computer processor that checks the storage over different time intervals in order to identify a particular sized memory leak in the storage based upon each time interval's length.
    Type: Application
    Filed: September 21, 2009
    Publication date: March 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Patrick J. Callaghan, Thomas B. Mathias
  • Publication number: 20110066878
    Abstract: A semiconductor storage device includes a memory cell array including memory cells arranged at respective intersections between first wirings and second wirings. Each of the memory cells includes a rectifier element and a variable resistance element connected in series. A control circuit is configured to apply a first voltage to a selected first wiring and a second voltage lower than the first voltage to a selected second wiring so that a certain potential difference is applied to a selected memory cell positioned at an intersection between the selected first wiring and the selected second wiring. The control circuit performs a concurrent read operation to perform a read operation from plural memory cells concurrently by applying the first voltage to a plurality of the first wirings concurrently. It is possible to switch the number of the first wirings to be applied with the first voltage concurrently in the concurrent read operation.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 17, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Hosono, Yuri Terada, Takahiko Sasaki
  • Publication number: 20110066877
    Abstract: A method for accessing a flash memory includes: writing a data stream into at least a page of at least one data block of the flash memory, where each page of the data block includes an identity code; reading at least one identity code of the page; and determining a specific page according to at least the identity code, where the specific page is a last page that the data stream is written to before the flash memory is disconnected from a power source.
    Type: Application
    Filed: May 3, 2010
    Publication date: March 17, 2011
    Inventors: Po-Syuan Chen, Chi-Hsiang Hung
  • Publication number: 20110035621
    Abstract: A system and method for communicating, browsing, verifying and routing data in storage operation systems using network attached storage devices is provided. In some embodiments, the system may include a management module and a media management component connected to the management server, which interoperate with network attached storage devices to provide the communicating, browsing, verifying and routing functions.
    Type: Application
    Filed: September 9, 2010
    Publication date: February 10, 2011
    Inventors: Duncan LITTLEFIELD, Ho-Chi CHEN, Rajiv KOTTOMTHARAYIL