Of Memory Patents (Class 714/6.1)
  • Patent number: 8386835
    Abstract: A computer readable storage medium, embodying instructions executable by a computer to perform a method, the method including: validating a memory write of data segments using a first number of leaf hashes of a first hash tree, where each of the first number of leaf hashes is associated with one of the data segments of a first block size, generating interior node hashes based on the first number of leaf hashes, where each of the interior node hashes is associated with a second block size, generating a first root hash using the interior node hashes, where the first root hash is associated with a remote procedure call size, transmitting the first root rash and the data segments to a network file system, where the transmission is performed using the remote procedure call size, and validating the transmission of the data segments using the first root hash.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: February 26, 2013
    Assignee: Oracle International Corporation
    Inventors: Andreas E. Dilger, Eric Barton, Rahul S. Deshmukh
  • Patent number: 8386834
    Abstract: A storage server receives a notification indicating a failure of a mass storage device in a storage array. The storage server determines whether a number of failures exceeds a fault tolerance level of the array and if the number of failures exceeds the fault tolerance level, recovers an address space corresponding to the failed storage device. When recovering the address space, the storage server replaces the failed storage device with a spare storage device having an identifiable pattern stored thereon and determines whether a file system on the storage system can automatically invalidate cached data blocks on the failed storage device.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: February 26, 2013
    Assignee: Network Appliance, Inc.
    Inventors: Atul Goel, Stephen H. Strange
  • Patent number: 8381020
    Abstract: A method and apparatus for facilitating control interface failover in a media storage device is described. In one embodiment, the method couples a media changer device to a plurality of removable media storage drives, where each removable media storage drive comprises a first port having a first port name and assigns a second port name to either the first port or to a second port of a first removable media storage drive in the plurality of removable media storage drives, where the second port name comprises at least a portion of portable identity data. The method preserves the portable identity data to be utilized during a control interface failover process to transfer the second port name from the first removable media storage drive to a second removable media storage drive in the plurality of removable media storage drives.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: February 19, 2013
    Assignee: Quantum Corporation
    Inventor: Roderick B. Wideman
  • Patent number: 8381025
    Abstract: A method begins when a dispersed storage (DS) processing unit of a DS unit has at least one of DS unit operational data and DS unit operating system algorithm to store. The method continues with the DS processing unit encoding at least a portion of the at least one of DS unit operational data and DS unit operating system algorithm in accordance with an error coding dispersal storage function to produce a plurality of data slices. The method continues with the DS processing unit storing at least some of the plurality of data slices in memory devices of the DS unit in accordance with the error coding dispersal storage function.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: February 19, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Steven Mark Hoffman, Jason K. Resch, Gary W. Grube, Timothy W. Markison
  • Patent number: 8381023
    Abstract: A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 19, 2013
    Assignee: MegaChips Corporation
    Inventor: Shinji Tanaka
  • Patent number: 8381027
    Abstract: A method is used in determining alternate paths in faulted systems. It is detected that a first processor has a problem accessing a target. The first processor has a first path to the target. An alternate path to the target is determined by identifying that a second processor has better access to the target than the first processor. The second processor has a second path to the target. Responsibility for I/O communication with the target is transferred from the first processor to the second processor. Responsibility for I/O communication with the target is transferred back to the first processor upon resolution of the problem.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: February 19, 2013
    Assignee: EMC Corporation
    Inventors: Qing Liu, Qi Zhang, Peter Tolvanen, T. David Evans, Hongliang Tang
  • Patent number: 8381019
    Abstract: Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Blake, Timothy C. Bronson, Hieu T. Huynh, Pak-kin Mak
  • Patent number: 8381018
    Abstract: The invention provides a method for data recovery. In one embodiment, a memory comprises a plurality of pages for data storage. First, first data is obtained from a host. A first page for storing the first data is then selected from the pages of the memory. A start page link indicating the first page is then stored in the memory. The first data, a first page link indicating a next page, and first FTL fragment data corresponding to the first page are then written into the first page. Next data is then obtained from the host. The next data, a next page link indicating a subsequent page, and FTL fragment data corresponding to the next page are written into the next page.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: February 19, 2013
    Assignee: Mediatek Inc.
    Inventors: Chia-Wen Lee, Shih-Hsin Chen, Shih-Ta Hung, Ping-Sheng Chen, Po-Ching Lu
  • Patent number: 8375257
    Abstract: An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: February 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Hyung Hong, Kwang-Seok Im
  • Patent number: 8370683
    Abstract: Systems and methods are provided for reducing write splice failures. In one embodiment, a system for writing data to a media includes a write buffer for storing a data sector and a backup power device for providing power to the write buffer in the event of a power failure to hold the data sector in the write buffer. The next time the system is powered up after the power failure, the system reads the data sector from the write buffer and uses the read data sector to correct a write splice on the media that may have occurred due to the power failure.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: February 5, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert P. Ryan, Robert M. Fallone
  • Publication number: 20130031406
    Abstract: Disclosed are an apparatus and method for writing data based on a drive state. In one embodiment, a method may comprise receiving a command to store data to a first area of a data storage device, detecting whether the data storage device is in a first state indicating a lowered write reliability, and writing the data to a second area when the first state is detected, the second area having a higher write reliability than the first area. In another embodiment, an apparatus may comprise a processor configured to receive a command to write data to a first area of a data storage device, detect whether the data storage device is in a first mode indicating a reduced writing reliability relative to a second mode, and write the data to a second area of the data storage device when the first mode is detected.
    Type: Application
    Filed: April 27, 2012
    Publication date: January 31, 2013
    Applicant: Seagate Technology LLC
    Inventor: Hyung Joon Cho
  • Patent number: 8364925
    Abstract: This storage system modifies the migration plan in accordance with the state of the migration destination when a plurality of volumes are migrated all at once. Migration-source volumes are migrated collectively to volumes inside the migration-destination storage apparatus. The user can make settings related to migration-source volumes and migration-destination volumes in a migration plan, and can establish a mid-process control plan for modifying the migration plan in the middle of processing. If a failure occurs in the migration-destination storage apparatus subsequent to the commencement of data migration processing, a processing method controller either cancels or temporarily halts the data migration processing, or changes the migration destination, on the basis of the mid-process control plan. When changing the migration destination, a previously selected alternate storage apparatus is selected as the new migration-destination storage apparatus.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: January 29, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Tsukasa Shibayama, Wataru Okada, Yukinori Sakashita, Yuri Hiraiwa, Masahide Sato
  • Patent number: 8365039
    Abstract: In a non-volatile memory that reads a binary value from a storage cell by comparing the voltage level of a stored charge in that cell against a reference voltage, the accumulated errors in a range of memory locations may be analyzed to determined if there are more errors in one direction than the other (for example, more 0-to-1 errors than 1-to-0 errors). If so, the reference voltage may be adjusted up or down so that subsequent reads from that range may produce approximately the same number of errors in each direction. For multiple-bits-per-cell memories, where there are multiple reference voltages for each cell, each reference voltage may be adjusted separately by keeping track of the errors related to that particular threshold.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Chun Fung Man, Jonathan E. Schmidt
  • Patent number: 8365031
    Abstract: A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: January 29, 2013
    Assignee: Fujitsu Limited
    Inventors: Kenji Suzuki, Yasufumi Honda, Takashi Koguchi
  • Publication number: 20130024722
    Abstract: Techniques involving replication of virtual machines at a target site are described. One representative technique includes an apparatus including a virtual machine configured to provide storage access requests targeting a virtual disk. A storage request processing module is coupled to the virtual machine to receive the storage access requests and update the virtual disk as directed by the storage access requests. A replication management module is coupled to the virtual machine to receive the storage access requests in parallel with the storage request processing module, and to store information associated with the storage access requests in a log file(s). The log file may be transferred to a destination as a recovery replica of at least a portion of the virtual disk.
    Type: Application
    Filed: July 22, 2011
    Publication date: January 24, 2013
    Applicant: Microsoft Corporation
    Inventors: Sriravi Kotagiri, Rahul Shrikant Newaskar, Palash Kar, Shreesh Rajendra Dubey
  • Patent number: 8359112
    Abstract: The present invention relates generally to process control systems and devices and, more particularly, to an apparatus for and a method of implementing redundant controller synchronization for bump-less failover during normal and mismatch conditions at the redundant controllers. The redundant controllers are configured to transmit state information of the process control areas of the primary controller to the backup controller that is necessary for synchronizing the redundant controllers but is not typically transmitted to other devices during the performance of process control functions. Synchronization messages are transmitted from the primary controller to the backup controller each time one of the control areas executes to perform process control functions.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: January 22, 2013
    Assignee: Emerson Process Management Power & Water Solutions, Inc.
    Inventors: Richard W. Kephart, Kimberly Costlow, Michael Durbin, Xu Cheng, Richard Brown
  • Patent number: 8352783
    Abstract: An information system including: a first and second storage apparatus including a first and second volume; a failure detection storage apparatus including a third volume; wherein, for backup purposes, the first and second volumes form a remote copy pair, and, for I/O request purposes, are recognized as a single volume labeled with a same volume identifier, but accessible by alternative access paths designated with differing priorities; wherein, if one apparatus detects a failure in the other or a connection failure, the apparatus detecting the failure stores, in the third volume, a failure information flag showing failure; wherein, upon receiving the I/O request through the second access path, the second storage apparatus determines whether the failure information flag is stored in the third volume, and sends an error reply of the I/O request to the host computer if the failure information flag is stored in the third volume.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: January 8, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Kenta Ninose
  • Patent number: 8352780
    Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: January 8, 2013
    Assignee: Thomson Licensing
    Inventors: Thomas Brune, Michael Drexler, Dieter Haupt
  • Patent number: 8352779
    Abstract: In one embodiment, the present invention includes a method for receiving an indication of a loss of redundancy with respect to a pair of mirrored memory regions of a partially redundant memory system, determining new mirrored memory regions, and dynamically migrating information stored in the original mirrored memory regions to the new mirrored memory regions. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventors: Mallik Bulusu, Robert C. Swanson
  • Patent number: 8352812
    Abstract: Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: January 8, 2013
    Assignee: Intel Corporation
    Inventors: Xavier Vera, Jaume Abella, Javier Carretero Casado, Antonio González
  • Patent number: 8352781
    Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: January 8, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Akhil Garg, Prashant Dubey
  • Publication number: 20130007508
    Abstract: Receiving a power off alert indicating a power off condition of a first processing system on which a first storage provider is installed, the first storage provider managing at least one storage controller. Responsive to the power off alert, issuing a first command to a second storage provider installed on a second processing system, the first command indicating to the second storage provider to assume management of the storage controller.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: SANDIP AMIN, AJAY K. BARGOTI, RISHIKA KEDIA, ANBAZHAGAN MANI
  • Publication number: 20130007509
    Abstract: A method of utilizing storage in a storage system comprises prioritizing a plurality of storage areas in the storage system for data recovery with different priorities; and performing data recovery of the storage system at an occurrence of a failure involving one or more of the storage areas in the storage system based on the priorities. Data recovery for one storage area having a higher priority is to occur before data recovery for another storage area having a lower priority in the storage system. In various embodiments, the prioritization is achieved by monitoring the access characteristics, or the priority is specified by the host or management computer based on the usage and/or importance of data stored in the storage system, or the priority is determined by the storage system based on the area assignment/release (i.e., usage) of thin provisioned volumes.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 3, 2013
    Applicant: HITACHI, LTD.
    Inventors: Hiroshi ARAKAWA, Akira YAMAMOTO
  • Publication number: 20130007511
    Abstract: A method and apparatus for rebuilding a data set. In accordance with some embodiments, a data storage device is coupled to a host. An error condition associated with a memory of the data storage device is detected. Data stored in a first portion of the memory unaffected by said error condition is transferred to the host. A communication signal is output to the host that indicates that data stored in a second portion of the memory affected by said error condition will not be transferred to the host. The host reconstructs the data stored in the second portion of the memory responsive to the communication signal.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Mark Allen Gaertner, Tyler Ki Soo Gordon
  • Patent number: 8347150
    Abstract: A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: January 1, 2013
    Assignee: Continental Teves AG & Co., oHG
    Inventors: Lukusa Didier Kabulepa, Houman Amjadi, Wolfgang Fey, Adrian Traskov
  • Patent number: 8347151
    Abstract: Data storage services are provided for clients for backup of data objects from the clients. A data object is sent to a first location in a first storage device. A determination is made if the data object was successfully stored at the first location, and if so, meta data corresponding with the data object is stored, wherein the meta data includes first path information on a first data path of the data object to the first location. The data object is migrated from the first location to a second location in a second storage device. A determination is made if the data object was successfully stored at the second location, and if so, second path information on a second data path of the data object is added to the second location to the meta data corresponding with the data object, to update the meta data.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Colin S. Dawson, Glen Hattrup, Howard N. Martin, David M. Morton
  • Publication number: 20120331337
    Abstract: A memory card controller includes a receiver, a flow controller, a continuity determination unit, and a command controller. When size of data transferred from the memory card reaches transfer size specified by first read command, the command controller controls the flow controller to transmit a response representing a transfer busy state, and pauses a transfer operation of the memory card. When the receiver receives a second read command in a state that the transfer operation of the memory card is paused, the command controller controls the flow controller to transmit a response representing transfer ready state to the transfer authorization request from the memory card so as to restart a transfer operation of the memory card.
    Type: Application
    Filed: November 22, 2011
    Publication date: December 27, 2012
    Inventor: Takeshi OTSUKA
  • Patent number: 8341456
    Abstract: An apparatus of recording data on a recording medium includes an optical recording device and a microcomputer. The recording medium has a lead-in area, a lead-out area, and a data zone, where the data zone has a user data area and a spare area. When the microcomputer receives a command for physically overwriting first data in a first area within the user data area and determines that the first area is included in a pre-recorded area, it controls the recording device to record the first data in a first replacement area instead and to record a first entry in a TDMA, where the first entry specifies the locations of the first area and the first replacement area.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: December 25, 2012
    Assignee: LG Electronics, Inc.
    Inventor: Yong Cheol Park
  • Patent number: 8341364
    Abstract: An apparatus, system, and method are disclosed for maintaining asynchronous mirroring. A detection module detects insufficient storage space to store a snapshot of a logical volume in at least one of a primary storage system and a secondary storage system. The primary storage system comprises the logical volume. A write from a host to the logical volume is acknowledged, maintaining asynchronous mode mirroring between the primary storage system and the host. The mirror module mirrors the write to the logical volume at the secondary storage system using a backup synchronous mode in response to detecting the insufficient storage space. Under the backup synchronous mode, the primary storage system acknowledges the write to the host while concurrently mirroring the write to the secondary storage system. The secondary storage system acknowledges the mirrored write to the primary storage system.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Juan A. Coronado, Christina A. Lara, Lisa R. Martinez, Robert J. McNamara
  • Publication number: 20120324274
    Abstract: It is provided a storage system for storing write data requested by a host computer, comprising: a data storage device, first and second cache memories, first and second non-volatile memories and at least one power storage device, wherein the storage system stores the requested write data in the data storage device, without storing the requested write data in neither the first cache memory nor the second cache memory in a case where the amount of charge of the at least one power storage device is smaller than the predetermined amount of power, and stores the requested write data in at least one of the first and second cache memories, and then store the requested write data in the data storage device in a case where the amount of charge of the at least one power storage device is equal to or larger than the predetermined amount of power.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 20, 2012
    Applicant: HITACHI, LTD.
    Inventor: Masanori Hori
  • Patent number: 8332724
    Abstract: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: December 11, 2012
    Assignee: The Invention Science Fund I, LLC
    Inventors: Bran Ferren, Edward K. Y. Jung
  • Patent number: 8332685
    Abstract: A method of determining whether a defect exists on an information storage medium is provided along with a recording/reproducing apparatus using the same. Such a method comprises: seeking a defect entry whose state information indicates that a defect block or a replacement block has been re-initialized without certification from a defect list for managing an information storage medium and including state information of the defect block and state information of the replacement block, wherein the medium includes a spare area for recording the replacement block to replace the defect block occurring in a user data area on the medium; and certifying the defect block or the replacement block registered in the sought defect entry. As a result, defect information can be effectively rearranged for quick re-initialization without certification in order to improve the performance of a drive system.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-hee Hwang, Jung-wan Ko, Hyo-lin Sung
  • Publication number: 20120311381
    Abstract: The present disclosure includes apparatus (e.g., computing systems, memory systems, controllers, etc.) and methods for providing data integrity. One or more methods can include, for example: receiving a number of sectors of data to be written to a number of memory devices; appending first metadata corresponding to the number of sectors and including first integrity data to the number of sectors, the first metadata has a particular format; generating second integrity data to be provided in second metadata, the second integrity data corresponding to at least one of the number of sectors (wherein the second metadata has a second format); and generating third integrity data to be provided in the second metadata, the third integrity data including error data corresponding to the second integrity data and the at least one of the number of sectors.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: Micron Technology, Inc.
    Inventor: Kent A. Porterfield
  • Publication number: 20120311378
    Abstract: Techniques are described for increasing a lifetime of blocks of memory. In operation, respective life expectancy scores for each of the blocks are calculated based at least in part on a respective number of times each of the blocks is respectively erased, and further based at least in part on at least one other factor that affects the lifetime of the blocks. An order to write and recycle the blocks is determined, based at least in part on at least some of the respective lifetime expectancy scores. A total amount of the blocks that are erased and written is minimized while lifetime expectancy score variation between the blocks is equalized.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 6, 2012
    Applicant: LSI CORPORATION
    Inventor: Radoslav Danilak
  • Patent number: 8327059
    Abstract: In a computer system supporting execution of virtualization software and at least one instance of virtual system hardware, an interface is provided into the virtualization software to allow a program to directly define the access characteristics of its program data stored in physical memory. The technique includes providing data identifying memory pages and their access characteristics to the virtualization software which then derives the memory access characteristics from the specified data. Optionally, the program may also specify a pre-defined function to be performed upon the occurrence of a fault associated with access to an identified memory page. In this manner, programs operating both internal and external to the virtualization software can protect his memory pages, without intermediation by the operating system software.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 4, 2012
    Assignee: VMware, Inc.
    Inventors: Xiaoxin Chen, Pratap Subrahmanyam
  • Patent number: 8327182
    Abstract: A method is disclosed for recovering data associated with a damaged file stored in a NAND gate array memory. The method includes the steps of: identifying all meta data associated with the damaged file; identifying each logical block address of all identified meta data; collecting all physical block addresses associated with one of the identified logical block addresses or the identified meta data; counting in a replace table (ReplTable) a number of matches to a physical block address of the damaged file for each physical block address of the damaged file; choosing a block in a linked list that corresponds to the physical block address of the block in the linked list; and linking all chosen blocks to form a replicated file.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: December 4, 2012
    Assignee: The Board of Governors for Higher Education, The State of Rhode Island and Providence Plantations
    Inventors: Qing Yang, Weijun Xiao
  • Patent number: 8321720
    Abstract: When a failure occurs in an LPAR on a physical computer under an SAN environment, a destination LPAR is set in another physical computer to enable migrating of the LPAR and setting change of a security function on the RAID apparatus side is not necessary. When a failure occurs in an LPAR generated on a physical computer under an SAN environment, configuration information including a unique ID (WWN) of the LPAR where the failure occurs is read, a destination LPAR is generated on another physical computer, and the read configuration information of the LPAR is set to the destination LPAR, thereby enabling migrating of the LPAR when the failure occurs, under the control of a management server.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: November 27, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yukari Hatta, Hitoshi Ueno
  • Patent number: 8321721
    Abstract: A disk drive system and method capable of dynamically allocating data is provided. The disk drive system may include a RAID subsystem having a pool of storage, for example a page pool of storage that maintains a free list of RAIDs, or a matrix of disk storage blocks that maintain a null list of RAIDs, and a disk manager having at least one disk storage system controller. The RAID subsystem and disk manager dynamically allocate data across the pool of storage and a plurality of disk drives based on RAID-to-disk mapping. The RAID subsystem and disk manager determine whether additional disk drives are required, and a notification is sent if the additional disk drives are required. Dynamic data allocation and data progression allow a user to acquire a disk drive later in time when it is needed. Dynamic data allocation also allows efficient data storage of snapshots/point-in-time copies of virtual volume pool of storage, instant data replay and data instant fusion for data backup, recovery etc.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: November 27, 2012
    Assignee: Compellent Technologies
    Inventors: Philip E. Soran, John P. Guider, Lawrence E. Aszmann, Michael J. Klemm
  • Patent number: 8321722
    Abstract: A storage device in which the MR-IOV is applied to an internal network of a storage controller. Data path failover can be executed in the storage device. The internal network of the storage controller is configured to enable the access of a virtual function (VF) “VF 0:0, 1” of each endpoint device (ED0-ED2) from a root port RP0. Likewise, “VF 1:0, 1” of each endpoint device can be accessed from a root port RP1. In a first data path from the RP0 to ED0 in a normal state, “VF 0:0, 1” and “MVF 0, 0” are connected by VF mapping. When a failure occurs on the first data path, the MR-PCIM executes the VF migration, whereby in the second data path from the RP1 to ED0, “VF 1:0, 1” and “MVF 0, 0” are connected by VF mapping. As a result, failover to the second data path is realized.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: November 27, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • Publication number: 20120297241
    Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 22, 2012
    Inventor: Joe M. Jeddeloh
  • Patent number: 8315991
    Abstract: Embodiments of the invention detect inadvertent or malicious data corruption and for recovering data including receiving a query specifying corrupted application data; analyzing transaction logs to find update operations related to the data; determining where the data are stored, by mapping the table data to locations within the file system and mapping the file system locations to volume logical blocks; and analyzing snapshot volume bitmaps to determine if the bitmaps show changes to the table data stored in the volume logical blocks. Changes which are reflected in the bitmaps for the data, but which do not have corresponding entries in the transaction logs are flagged as unauthorized changes. Snapshots of the data, from a time prior to the time at which a flagged snapshot was taken, are identified for use in restoring data to its status prior to the unauthorized change.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: November 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nagapramod S. Mandagere, Mark J. Seaman, Sandeep M. Uttamchandani
  • Patent number: 8316017
    Abstract: An inappropriate-access module is incorporated in a computer system along with other computer system modules. The inappropriate-access module is connected to a read address decoder and controlling logic located within various other modules. The inappropriate-access module detects inappropriate read accesses or the occurrence of the inappropriate access during operations performed on related sensitive system resources in accompanying computer system modules. The inappropriate-access module produces an inappropriate-access flag, made available to the rest of the system, which invokes responses in the accompanying modules such as a halt in processing and protective measures for system resources. Additionally, a related logic block is able to detect the inappropriate access and produce an inappropriate-access trigger which causes a halt to processing within the logic block as well as in related system modules.
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: November 20, 2012
    Assignee: Atmel Corporation
    Inventors: Alain Vergnes, Renaud Tiennot
  • Patent number: 8316257
    Abstract: Techniques to recover data from an indirected non-volatile memory system after unexpected power failure, as, e.g., NAND memory in electronic devices are disclosed.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Robert Royer, Sanjeev N. Trika, Rick Coulson, Robert W. Faber
  • Patent number: 8312315
    Abstract: The present invention provides a storage system having a controller that can extend an old RAID group to a new RAID group without decreasing a processing speed. A conversion part reads the data from an unconverted area A1, converts it into the data based on a new RAID organization, and write it into a storage area A3 of the new RAID group. An address management part updates an initial address Ps and a last address Pe saved in a flash memory if the initial address Ps saved in the flash memory and the newest last address Pe of a converted area A2 are matched. When a power failure occurs, it is checked to see whether or not the data within the converted area A2 is correct. The conversion part reads the initial address Ps and the last address Pe from the flash memory to resume a conversion process.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Yuko Matsui
  • Patent number: 8312312
    Abstract: A controller transmits a second protocol command to a target from among one or more switch devices. The second protocol command is a command which conforms to a second protocol type in which a connection established for transmitting a command to the target is broken during processing of the command by the target, and is defined as a command corresponding to a first protocol command, which is a command conforming to a first protocol type in which the connection remains established during processing of the command by the target.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: November 13, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihiro Oikawa, Ikuya Yagisawa, Bunitsu Ando
  • Patent number: 8312313
    Abstract: An information processing apparatus has a first storage unit and a second storage unit and operates in one of a normal power mode and a power saving mode. When the information processing apparatus is operating in the power saving mode, if an error occurs in a storage process, the power mode of the information processing apparatus is switched to the normal power mode and the storage process is executed again. The storage process is a process in which when the first storage unit is replaced with a new storage unit, information equivalent to that stored in the first storage unit is stored in the new storage unit.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: November 13, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masakazu Kitora
  • Patent number: 8307249
    Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: November 6, 2012
    Assignee: Globalfoundries, Inc.
    Inventors: Markus Seuring, Kay Hesse, Kai Eichhorn
  • Patent number: 8307240
    Abstract: The present invention is a method for communication between an initiator system and a block storage cluster. The method includes receiving a command at a first storage system of a block storage cluster. The command is transmitted by the initiator system to the first storage system via a network and includes a request for data. The method further includes transferring the stored data from the first storage system to the initiator system via the network when data requested in the data request is stored by the first storage system. The method further includes transmitting a referral response from the first storage system to the initiator system when a portion of the data requested in the data request is not stored by the first storage system, but is stored by a second storage system of the block storage cluster. The referral response indicates to the initiator system that: a) not all of the requested data was transferred; and b) that the second storage system stores the portion of the requested data.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: November 6, 2012
    Assignee: Netapp, Inc.
    Inventors: Gerald J. Fredin, Andrew J. Spry, Kenneth J. Gibson, Ross E. Zwisler
  • Publication number: 20120278650
    Abstract: Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Inventors: Naveen Muralimanohar, Parthasarathy Ranganathan, Jichuan Chang
  • Patent number: 8301854
    Abstract: The storage system of the present invention is able to generate one virtual logical device from different logical devices which exist in each of the different storage control units and remote-copy all or part of the virtual logical device to another logical device. The same virtual identifier is set for a volume of the first storage unit and for a volume of the second storage unit. The path control unit of the host identifies a plurality of volumes which have the same virtual identifier as one virtual volume. A remote copy pair can also be set by a virtual volume and a volume of the third storage unit. The setting of the virtual volume and the setting of the remote copy can be performed by means of an instruction from the management server.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: October 30, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshihito Nakagawa, Satoru Ozaki