Abstract: An information handling system includes a host processing system and a baseboard management controller (BMC). The host processing system includes a main processor that instantiates a management controller agent, and a general-purpose processing unit (GPU). The BMC is coupled to the host processing system and to the GPU. The BMC is configured to direct the management controller agent to retrieve first management information from the GPU, receive the first management information from the management controller agent, retrieve second management information from the GPU, and provide a health indication for the GPU based upon the first management information and the second management information.

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: An analyzer and a method for analyzing a signal, in particular a signal for transmitting data is provided. For analyzing the signal transmission and detecting a specific error, a data signal may be received and analyzed in order to detect one or more types of errors according to predetermined specifications. When such a predetermined error is detected, the signal for transmitting the data and one or more further signals, which may cause the error are acquired. Accordingly, a cause of failure may be easily analyzed based on the acquired signal sequences of the signal for transmitting the data and the additionally acquired signals.

Abstract: Systems and methods are described for reducing error rates on data storage devices by applying data shaping to data written to such devices in order to avoid error-prone states on cells within the devices. Different states of individual cells (such as those representing different bit patterns) may have different propensities for error, and these propensities may vary during operation of a device. Thus, a device as disclosed herein may determine error-prone states for a cell or group of cells, and apply data shaping to data written to such cells to reduce the likelihood that writing the data places the cell or cells into an error-prone state. Data shaping may be used, for example, to increase the occurrence of “0” bits within input data, thus avoiding error-prone low voltage states that may be used to represent a series of “1” bits.

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

Abstract: The present disclosure provides a downlink control information transmission method, including generating more than one downlink control information (DCI) according to scheduling information of a user equipment (UE); determining a detection order of the more than one DCI and positions of the more than one DCI in a searching space; adding a position indication field to a respective DCI according to the detection order of the more than one DCI and the positions of the more than one DCI in the searching space; wherein, the position indication field is used to indicate a position of a next DCI of the respective DCI in the detection order; in which, a position indication field in a last DCI in the detection order is used to indicate a position of a first DCI in the detection order; and transmitting the more than one DCI in the searching space according to the positions of the more than one DCI in the searching space. The present disclosure also provides a UE-side method, a corresponding base station and a UE.

Abstract: In some embodiments, an apparatus is configured to wirelessly communicate with a base station using a first retransmission parameter in a first frame transmission scheme. In some embodiments, the apparatus is configured to determine a current performance metric and, based on the current performance metric, use a second, different retransmission parameter in a second frame transmission scheme for subsequent communications. In some embodiments, the retransmission parameter is a number of retransmissions or a number of hybrid automatic repeat request (HARQ) processes.

Abstract: The present disclosure a method of decoding a polar code based on a shared node, the method includes extracting an input node from target data that are data to be decoded, by an extractor, sorting the input node as one of a first node of which the pattern of the frozen bit satisfies a predetermined first reference, a second node of which the pattern of the information bit satisfies a predetermined second reference, and a third node that is not the first node and the second node, by a sorter, calculating at least one codeword candidate and at least one path metric that correspond to the input node in accordance with the sorting result by a calculator, finishing decoding the target data by iterating the extracting, the sorting as one, and the calculating of at least one path metric by a controller.

Abstract: One embodiment facilitates data placement. During operation, the system monitors a condition of a plurality of blocks of a non-volatile memory. The system determines that a condition of a first block falls below a first predetermined threshold, wherein the first block has a first capacity. The system formats the first block to obtain a second block which has a second capacity, wherein the second capacity is less than the first capacity.

Abstract: Techniques are disclosed for automated detection and notification of interconnect errors or failure. An interconnect is tested via passive or active means. Error data associated with data transferred via the interconnect is measured and analyzed to generate error statistics. Error statistics are then used to determine an error rate of the interconnect and an alert is generated if the error rate exceeds a threshold. Alerts are displayed to users for troubleshooting and/or for indication that the interconnect should be replaced.

Abstract: A first device receives, over a first communications link, a container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames of a second length. The first length is not a multiple of the second length. Each of the OTU frames includes an optical data unit (ODU) frame, a sequence of forward error correction (FEC) bits for the ODU frame, and a sequence of error-identifying bits for the ODU frame. The first device determines, based on the sequences of error-identifying bits, a performance of the first communications link.

Abstract: An apparatus, a system and a method use a class of dynamic switching mechanisms with multiple HARQ block sizes to reduce HARQ retransmission overhead while limiting the increase of HARQ ACK feedback overhead. The apparatus includes a first processing unit configured to estimate an intra-subframe fluctuation level of per-codeblock errors; a second processing unit configured to: map the intra-subframe fluctuation level to a hybrid automatic repeat request (HARQ) block size; determine a HARQ acknowledgement (ACK) format based at least in part on the HARQ block size; indicate the selected HARQ block size to a data transmitter; and generate a HARQ ACK. Per-code block link adaptation can be used to support multiple MCSs for a single user in each subframe with fine time-frequency granularity, with low-bandwidth signaling overhead and without a complete dependency on reference signal (RS) structure.

Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device may include memory cells configured to store data, a peripheral circuit configured to perform program and read operation on memory cells selected from among the memory cells, and a refresh controller configured to include a counter and a refresh manager, wherein the counter is configured to count a number of memory cells which are in an erased state or a programmed state by performing a read operation on the selected memory cells using a reference read voltage, and the refresh manager is configured to compare a read count indicating the counted number of memory cells, with a preset reference count, to determine whether to shift the reference read voltage and to control the peripheral circuit so that the program operation is performed using a voltage different than a program voltage by a step voltage.

Abstract: A controlled active resistance. The active resistance is implemented on an integrated circuit. In some embodiments, the active resistance includes a MOSFET. In alternate embodiments, the active resistance includes a MOSFET and a resistor. The control for the active resistance includes a reference resistor and an operational amplifier. The control for the active resistance further includes two current sources: i) a current source producing a current that is proportional to absolute temperature, and ii) another current source that is produced by a bandgap voltage reference. In one aspect, the active resistance generates an effective resistance that is proportional to thermal voltage. In another aspect, the active resistance generates an effective resistance that is proportional to inverse of the thermal voltage. In an alternate aspect, the current sources have various dependencies, and the active resistance generates an effective resistance that is proportional to those dependencies.

Abstract: A communication unit of the present disclosure includes a decoding section configured to decode transfer data transmitted from a communicated unit, by a first method using a first error detecting code, and a second method using at least an error correcting code, and a determination section that performs determination as to whether the transfer data are data in the first method including the first error detecting code or data in the second method including the error correcting code.

Abstract: A controller sets an error count margin for each of multiple units of a non-volatile memory and detects whether the error count margin of any of the multiple units has been exceeded. In response to detecting that the error count margin of a memory unit is exceeded, the controller determines whether calibration of the memory unit would improve a bit error rate of the memory unit sufficiently to warrant calibration. If so, the controller performs calibration of the memory unit. In some implementations, the controller refrains from performing the calibration in response to determining that calibration of the memory unit would not improve the bit error rate of the memory unit sufficiently to warrant calibration, but instead relocates a desired part or all valid data within the memory unit and, if all valid data has been relocated from it, erases the memory unit.

Abstract: According to one embodiment, a memory includes a non-volatile memory, a first buffer, a first circuit, a second circuit, and a third circuit. The first circuit transfers data from a host to the non-volatile memory through the first buffer. The second circuit executes garbage collection through the first buffer. The first buffer includes a second buffer and a third buffer. The second buffer can be allocated to the first and second circuit. The third buffer can be allocated only to the first circuit. The third circuit includes a timer. The third circuit allocates the first buffer to the first circuit or the second circuit upon writing of data in the non-volatile memory from the second buffer. The third circuit, after data is written into the non-volatile memory from the third buffer, allocates the third buffer to the first circuit at timing based on the timer.

Abstract: A method of driving a display by communicating with a controller through a first channel and a second channel includes; generating recovery data from a signal received through the first channel during a frame data period, detecting a vertical blank period between frame data periods, checking a training trigger event history during the vertical blank period, and during the vertical blank period, transmitting a training request direct to the first channel through the second channel when there is a training trigger event history.

Abstract: Embodiments for a routing module for a first node are disclosed. The routing module includes a computer readable medium having instructions thereon. The instructions cause one or more processing devices to track former links between the first node and a second node and determine a probability of a future link with the second node based on the former links. If the probability of a future link with a second node is above a threshold, an advertisement is sent to at least one other node indicating that the second node is reachable from the first node. If the probability of a future link with the second node is below the threshold and no other route exists from the first node to the second node, an advertisement is sent to at least one other node indicating that the second node is not reachable from the first node.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells in a first time period and manage the set of non-volatile memory cells according to a probability of occurrence of a target FBC in a second time period that is subsequent to the first time period. The probability of occurrence of the target FBC during the second time period is calculated from a model of FBC distribution change of the set of non-volatile memory cells.

Abstract: A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.

Abstract: A first device operates synchronously with a second device, and includes a hardware clock having an adjustable clock frequency and a software clock configured to derive time in dependence on the hardware clock. A controller determines a synchronisation error between the software clock and a clock of the second device, and adjusts the clock frequency of the hardware clock in dependence on the synchronisation error so as to synchronise the hardware clock to a hardware clock of the second device.

Abstract: The disclosure provides a memory device including: a connection interface; a memory array associated with a parameter; and a memory control circuit configured at least to: receive operations, each of the operations being a read operation or a write operation, through the connection interface to perform the operations on the memory array; detect, based on performing the operations on the memory array, a read error which is either a binary 0 read error or a binary 1 read error; update the error counter by incrementing an counter value of the error counter in response to the read error being the binary 1 read error and decreasing the counter value in response to the read error being the binary 0 read error; and adjust the parameter in response to the counter value having reached a positive predetermined threshold or a negative predetermined threshold.

Abstract: A technology for calibrating device-end operational information of a data storage system is shown. A controller operates a non-volatile memory with reference to operational information. A second type of logical address requested by the host that is different from the first type of logical address used in operating a file system of a host is introduced. As indicated by the second type of logical address, the controller receives calibration information from the host and calibrates the operational information based on the calibration information.

Abstract: Transcoders may be used to transcode multimedia inputs to generate output multimedia segments encoding segment quality scores that relate to the quality of transcoded segments and may be based at least in part on whether transcoding errors were detected. A system may be used to detect the generation of a multimedia segment and detect whether an event satisfies a condition for invocation of a mitigation routine. An event may include the generation of a multimedia segment having a quality segment score below a threshold value or the generation of a multimedia segment having a particular type of transcoding error. A second multimedia segment may be generated as part of the mitigation routine.

Abstract: An optical transceiver capable of optimizing the performance of the corresponding optical channel by dynamically adjusting the optical power of the output signal in response to the FEC-performance data received from the corresponding remote transceiver. In an example embodiment, the FEC-performance data can be exchanged by the two optical transceivers using a dedicated field in the overhead of the transmitted data frames. The power-adjustment process is configured to be relatively slow to prevent the occurrence of transients on other optical channels and ensure stable operation of the corresponding WDM system as a whole, while different transceivers thereof are allowed to adjust their respective output powers in an autonomous way and independent of each other.

Abstract: Systems and methods are described for a method of operating a wireless communication device includes receiving a physical downlink control channel (PDCCH) including a plurality of control channel elements (CCE), storing a plurality of LLRs generated by demodulating the PDCCH in a data buffer, storing at least one address of the LLRs, corresponding to a plurality of PDCCH candidates in accordance with an aggregation level for the CCEs, in a plurality of address buffers, and performing blind decoding on the PDCCH candidates by using the data buffer and the address buffers.

Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.

Abstract: One aspect of the present disclosure provides a method for configuring a disk array of an electronic device. The method includes: storing configuration information of the disk array; acquiring the stored configuration information if the electronic device is turned on; and configuring the disk array according to the configuration information.

Abstract: A memory module for reporting information about a fail in chip units, an operation of a memory module, and an operation of a memory controller are provided. The memory module includes: first to Mth memory chips (where M is an integer that is equal to or greater than 2) mounted on a module board and storing data, and an (M+1)th memory chip mounted on the module board and storing a parity code for recovering data of a memory chip in which a fail in chip units occurs among the first to Mth memory chips, wherein fail bits are generated from the first to (M+1)th memory chips through an intra-chip error detection operation, and fail information is output according to a result of calculating the fail bits from the first to (M+1)th memory chips.

Abstract: The present specification relates to a method for transmitting or receiving a signal by a station in a wireless LAN (WLAN) system and, more particularly, provides a method in which when a station transmits or receives a signal through a plurality of spatial streams in a wireless LAN system, the station operates a modulation and coding scheme (MCS) applied to each spatial stream, a method for transmitting or receiving a signal on the basis of the same, and a device therefor.

Abstract: Multi-channel accessing of non-volatile memory. A controller uses three kinds of tables to manage cross-channel accessing areas and, accordingly, to access the non-volatile memory through multiple channels. Each cross-channel accessing area includes M storage units, where M is an integer greater than 1. For each cross-channel accessing area, the first table marks whether there is a need for storage unit substitution and points to substitution information. The substitution information is stored in the second table and the third table. For each cross-channel accessing area marked in the first table, the second table stores M bits corresponding to M storage units of the marked cross-channel accessing area for substitution indication, and related substitute storage unit indication is stored in the third table.

Abstract: Embodiments can include a scan of data associated with programmed memory cells is performed. The scan of data results in a bit error count (BEC) histogram. A trigger margin is determined from the BEC histogram. The determined trigger margin and a target trigger margin are compared. In response to the determined trigger margin being different than the target trigger margin, one or more program step characteristics is adjusted to adjust the determined trigger margin toward the target trigger margin.

Abstract: Described are techniques for customizing a help system. A help system may be received providing help for a product. A proficiency level for a user may be determined in accordance with one or more proficiency criteria including one or more previous interactions of the user with any of the help system and performing an operation using a non-help feature of the product. A customized help system for the user may be determined for the user in accordance with the proficiency level for the user, wherein the customized help system is a modified version of the help system.

Abstract: A system includes a plurality of memory cells. Each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages. The memory cells are read to determine a programmed data state of each memory cell. Error correction decoding is performed to determine a corrected data state of each memory cell. The corresponding cell levels, or programmed voltages, are determined based on the programmed data state and the corrected data state. A first error count represents a total number of error cells that have a higher cell level for the corrected data state than the programmed data state. A second error count represents a total number of error cells that have a lower cell level for the corrected data state than the programmed data state. The system is configured to perform a memory operation based on the first error count and the second error count.

Abstract: A computerized system and method for managing a passive optical network (PON) are disclosed. The system includes a detection and analysis module adapted for receiving uploaded measurement data from an optical line terminal (OLT) and at least one optical network terminal (ONT), and at least one of technical tools data, service failure data, and outside plant data. The detection and analysis module is adapted for determining a source of failure or potential failure in the PON by correlating the uploaded measurement data and the at least one of technical tools data and service failure data with information stored in a memory medium for the OLT and each ONT.

Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.

Abstract: A resistive memory including a first storage circuit, a verification circuit, a second storage circuit and a control circuit is provided. The first storage circuit includes various cell groups. Each of the cell groups includes at least one memory cell. The verification circuit is coupled to the first storage circuit to verify whether a specific operation performed on at least one of the memory cells was successful. The second storage circuit includes various flag bits. Each of the flag bits corresponds to a cell group. In a reset period, the control circuit is configured to perform a first reset operation or a second reset operation on a first memory cell of a specific cell group among the cell groups according to a specific flag bit corresponding to the specific cell group.

Abstract: Methods and systems are provided for prioritizing a plurality of maintenance corrective actions in a troubleshooting chart for a device are provided. The method includes receiving, by a processor, an input from a user indicative of a successful corrective action from the plurality of corrective actions on the troubleshooting chart and incrementing a value of a counter associated with the successful corrective action. The processor then compares values for counters associated with each of the plurality of corrective actions and displays the plurality of corrective actions in hierarchal order based on the values of the counters.

Abstract: An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel. The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.

Abstract: A spectrum management system includes circuitry that obtains information of a primary communication system, where the information includes an interference tolerance of the primary communication system. The circuitry also obtains a desired communication quality for a secondary communication system, and determines available resources for the secondary communication system that result in an interference level below the interference tolerance of the primary communication system. The circuitry then allocates resources to the secondary communication system based on a comparison of an estimated communication quality of the secondary communication system if the available resources are used and the desired communication quality.

Abstract: Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information (FIGS. 7-9), and can be compatibly used in different wireless networks by means of message standardization.

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

Abstract: In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.

Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.

Abstract: A method for determining a transmit power in a coverage enhancement scenario and a device resolve a problem that the prior art lacks a solution to determining a transmit power of a preamble sequence in a random access process in the coverage enhancement scenario. The method includes: obtaining, by a terminal, configuration information that is used to determine a transmit power used for transmitting a signal at each coverage enhancement level; and determining, by the terminal according to the obtained configuration information, a transmit power used for transmitting the signal at a coverage enhancement level currently used by the terminal, so as to determine the transmit power used for transmitting the signal in the coverage enhancement scenario.

Abstract: A data storage system includes a controller that controls a non-volatile memory array including a plurality of garbage collection units of physical memory. For each of the plurality of garbage collections units storing valid data, the controller determines an invalidation metric and a health-based adjustment of the invalidation metric. The controller selects a garbage collection unit on which to perform garbage collection from among a plurality of garbage collections units predominately based on the invalidation metric for the garbage collection unit and also based on the health-based adjustment for the garbage collection unit. In response to selection of the garbage collection unit, the controller performing garbage collection for the garbage collection unit.

Abstract: A method includes detecting different data patterns in data read from a portion of a non-transitory data storage medium. Bit errors in the different data patterns are then determined. Further, bits in error for a total number of bits in each of the different data patterns are calculated from the determined bit errors in the different data patterns.

Abstract: A method of setting an upper limit value of the number of write times, which is applied to a magnetic disk device including a disk and a head configured to write data to the disk and read the data from the disk, includes measuring a plurality of bit error rates in a recording area of the disk upon repeatedly writing to an area of the disk adjacent to the recording area a number of write times, deriving a function that approximates a bit error rate in relation to a number of write times, using the measured bit rates corresponding to at least a first number of write times, a second number of write times, and a third number of write times, and applying the function to determine a number of write times that correspond to a first threshold bit error rate that makes the data on the disk unreadable, and setting the determined number of write times as the upper limit value of the number of write times.