Abstract: Embodiments of the present disclosure provide a method and apparatus for reducing cross talk among pins in a connector. The apparatus may detect a bit error rate (BER) for each of a plurality of pins in a connector and compare the BER for each pin to a threshold BER. Responsive to determining that a set of pins among the plurality of pins each have a BER that is above the threshold BER, the apparatus may decrease the BER for each pin in the set of pins by selecting a subset of pins among the plurality of pins and adjusting operational characteristics of one or more of the subset of pins. The operational characteristics include a transmit power of the pin.

Abstract: A variety of applications can include apparatus and/or methods to preemptively detect detect one memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.

Abstract: Embodiments of the present disclosure generally relate to storage devices, such as SSDs. A data storage device comprises an encrypted interface, one or more flash memory devices, and a controller configured to receive one or more workloads of data through the encrypted interface. Upon a threshold being met, the controller performs a diagnosis of one or more operating parameters of the one or more workloads of data. Based on the diagnosis, the data storage device is optimized by recalibrating one or more of: a partitioning of bits per cell of the one or more flash memory devices, one or more flash management parameters of the data storage device, and a programming rate of the storage device.

Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.

Abstract: A memory system suitable for counting the number of errors occurring in each memory location, and a host system suitable for detecting a defective memory location based on the number of the errors occurring in each memory location and controlling a repair operation for the defective memory location based on a current amount of data being processed between the host system and the memory system, wherein the memory system repairs the defective memory location using the redundant memory area.

Abstract: A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.

Abstract: A parallel processor includes one or a plurality of digital signal processing (DSP) arithmetic unit(s) and one or a plurality of DSP appropriateness checking unit(s) corresponding to the DSP arithmetic unit(s). The DSP appropriateness checking unit includes a register and a determining unit. The register repeatedly receives an arithmetic result from the DSP arithmetic unit. The determining unit determines, when an arithmetic result has the same calculation value, that an arithmetic operation performed by the DSP arithmetic unit is completed and outputs the calculation value as a determinate arithmetic result.

Abstract: A method of monitoring access requests to one or more access controls of an access control system is provided. The method comprising: receiving a first access request from a key card to a first access control, the key card being encoded with a credential and an access code; determining that the credential is not authorized to access the first access control; checking a first value of the access code; and rewriting the first value of the access code to a second value of the access code if the first value of the access code does not equal a desired value of failed access request attempts.

Abstract: Techniques involve: in response to a number of errors of an error type in a storage disk increasing, determining an adjustment rate for a health value of the storage disk based on a total usage time length of the storage disk, where a longer total usage time length corresponds to a higher adjustment rate, and the health value indicates a health condition of the storage disk with respect to the error type. The techniques further involve increasing the adjustment rate based on a total input/output (I/O) number of the storage disk, where a greater total number of I/Os corresponds to a greater increment. The techniques further involve adjusting the health value with the adjustment rate. Such techniques can improve the accuracy of evaluating the health condition of the storage disk.

Abstract: A memory system includes: a memory device that includes a plurality of ranks; and a memory controller suitable for deciding selection signals each of which selects one command set corresponding to each of combinations of the ranks and at least one program executed in the memory device among a plurality of command sets, and executing a program including the selected command set in the memory device.

Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Error thresholds for a memory device are configurable based on parameters such as a type of data or a location of stored data. When retrieving the data, the memory device tracks or counts errors in the data and determines whether the error threshold has been satisfied. The memory device transmits (e.g., to a host device) an indication of whether the error threshold has been satisfied, and the system is configured to perform functions to correct the errors and/or prevent further errors. The memory device is also configured to identify errors in received commands or to identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: The present technology includes a memory device and a method of operating the same. The memory device in which an interface circuit and a semiconductor memory are packaged together includes a centrally located region in a ball mapping region of a memory device in which data input/output pins for an operation of the interface circuit and the semiconductor memory are disposed, and a test pin region in which test pins for a test operation of the interface circuit are disposed.

Abstract: A method includes determining a portion of a block of a storage device to read after programming, and reading the portion of the block and determining a maximum error count for the portion of the block. The maximum error count is compared to a threshold. When the maximum error count exceeds the threshold, a code rate of an error correction coding used to program the block is adjusted, or a code rate test is performed on the entire block.

Abstract: A computer-implemented method for synchronizing wireless testing devices includes (a) in a protocol analyzer located in an RF-isolated test chamber, capturing first network packets transmitted to or from a wireless device-under-test (DUT) to generate protocol test data, (b) in the protocol analyzer, determining if any of the first network packets satisfy a trigger rule, (c) in the protocol analyzer, generating a trigger output signal when the trigger rule is satisfied, (d) sending the trigger output signal from the protocol analyzer to an RF analyzer in electrical communication with the DUT, (e) capturing second network packets with the RF analyzer based on the trigger output signal to generate RF test data, the second network packets transmitted to or from the DUT, and (f) in the protocol analyzer, time-aligning the first and second network packets in the protocol test data and the RF test data, respectively.

Abstract: A method includes: obtaining, by a terminal, configuration information, wherein the configuration information comprises a maximum quantity of signal transmitting attempts corresponding to each coverage enhancement level; determining, by the terminal according to the obtained configuration information, a transmit power used for transmitting the signal at a coverage enhancement level currently used by the terminal; and transmitting the signal using the determined transmit power.

Abstract: Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.

Abstract: An optical network device with abnormal light emission detection includes an optical transceiver circuit and a control circuit. The optical transceiver circuit receives a transmission signal. The control circuit enables the optical transceiver circuit according to the transmission signal, so that the optical transceiver circuit outputs an optical signal. The optical transceiver circuit outputs a status signal according to whether or not the optical transceiver circuit outputs the optical signal. The status signal triggers an interrupt system of the control circuit. The interrupt system is provided with a counter to count a light emission duration of the optical transceiver circuit. When the light emission duration is greater than a preset value, the control circuit stops the optical transceiver circuit from outputting the optical signal.

Abstract: In some embodiments, a method receives one or more segments for content from a first content delivery network during a playback session for the content. The content includes a number of segments. The method evaluates buffer occupancy of a buffer configured to store segments of the content for playback and evaluates a number of times of a failure to download a segment for the content. The buffer occupancy is compared to a first threshold and the number of times of the failure to a second threshold. The method determines a switch from the first content delivery network to a second content delivery network during the playback session based on the comparing.

Abstract: A data storage device may include a storage including a plurality of memory blocks each composed of a plurality of pages and divided into a first region including some of the plurality of memory blocks and a second region including remaining memory blocks of the plurality of memory blocks; and a controller configured to control data input and output of the storage in response to a request of a host, determine whether to move data stored in a memory block of the first region by performing a first scan operation on the memory block of the first region, and determine whether to move data stored in at least one memory block of the second region by performing a second scan operation on the at least one memory block of the second region after the first scan operation is completed.

Abstract: An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may construct, for adjusted fractally enhanced kernel (FRANK) polar coding, encoding code for encoding data of an ultra-reliable low latency (URLLC) communication, wherein an information bit assignment to an information bit set associated with the encoding code is performed based at least in part on an adjusted dimensionality factor, wherein the encoding code is all-stage FRANK polar code or partial-stage FRANK polar code, and wherein the encoding code is constructed for code block shortening or code block puncturing. In some aspects, the user equipment may transmit the URLLC communication encoded using the encoding code based at least in part on the information bit assignment to the information bit set. Numerous other aspects are provided.

Abstract: The invention introduces a method for proactive error-correcting code (ECC) failure handling, at least including the following steps: obtaining a completion element (CE) from a completion queue (CQ); determining whether an execution reply table of the CE comprises an unsecure value; if so, reallocating a physical address for a user data transaction corresponding to the unsecure value; and outputting a write command into a submission queue (SQ) for programming the user data transaction into the reallocated physical address.

Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.

Abstract: A method and a device for generating a data packet to be transmitted comprising data and at least one value for a cyclic redundancy check (CRC) value, are described, wherein the CRC value is generated using at least one previously determined polynomial on the basis of at least some of the data and the method comprises initializing a counter value, counting units of data, wherein the counter value changes for each unit of data, and adding a CRC value into the data packet, when the counter value reaches a reference value or all units of data in the data packet have already been counted, wherein the CRC value is generated over the units of data which have been counted since the counter value last reached the reference value or since the counter value was initialized. Furthermore, a method and a device for checking a corresponding received data packet are described.

Abstract: A process for generating regular expressions (regexes) as extraction patterns in a cluster computing system includes: receiving log events, a set of seed words, and a set of seed patterns; determining whether the set of seed words is full; if not, generating a new patterns by iteratively adding new patterns whose pattern scores S1 surpass a first preset score into the set of seed patterns; selecting a subset of seed patterns from the set of seed patterns; determining whether the subset of seed patterns is empty if not, generating a subset of seed words whose word scores S2 surpass a second preset score and iteratively adding the subset of seed words into the set of seed words; and repeating the above steps until the set of seed patterns is full and the set of seed words is empty; and finally pruning the set of seed patterns.

Abstract: Systems, methods, and apparatuses, for transform discrete voltage pulses to a continuous signal. One method may include receiving a pulsed-voltage signal. The method may also include alternately directing the pulsed-voltage signal between a pair of processing channels based on a modulation signal or another signal. The method may further include determining rate voltages corresponding to the pair of processing channels based on a pulse rate of the pulsed-voltage signal. Further, the method may include processing the rate voltages using low pass filters corresponding to the pair of processing channels to form filtered rate voltages. The method may also include determining a normalized differential output for the pair of processing channels based on the filtered rate voltages. The method may also include outputting the normalized differential output to an output connector.

Abstract: An information handling system includes a host processing system and a baseboard management controller (BMC). The host processing system includes a main processor that instantiates a management controller agent, and a general-purpose processing unit (GPU). The BMC is coupled to the host processing system and to the GPU. The BMC is configured to direct the management controller agent to retrieve first management information from the GPU, receive the first management information from the management controller agent, retrieve second management information from the GPU, and provide a health indication for the GPU based upon the first management information and the second management information.

Abstract: An apparatus includes a first function module providing a master signal, a second function module providing a comparison signal, and safety logic. The safety logic includes a toggle signal generator having a comparator providing a comparison result in response to the master signal and the comparison signal, a feedback path generating a first toggle signal in response to the comparison result and providing a feedback signal to the comparator, and a first multiple input gate generating a second toggle signal in response to the comparison result. The safety logic also includes a toggle signal monitor providing a final fault search signal in response to the first toggle signal and the second toggle signal.

Abstract: An analyzer and a method for analyzing a signal, in particular a signal for transmitting data is provided. For analyzing the signal transmission and detecting a specific error, a data signal may be received and analyzed in order to detect one or more types of errors according to predetermined specifications. When such a predetermined error is detected, the signal for transmitting the data and one or more further signals, which may cause the error are acquired. Accordingly, a cause of failure may be easily analyzed based on the acquired signal sequences of the signal for transmitting the data and the additionally acquired signals.

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

Abstract: Systems and methods are described for reducing error rates on data storage devices by applying data shaping to data written to such devices in order to avoid error-prone states on cells within the devices. Different states of individual cells (such as those representing different bit patterns) may have different propensities for error, and these propensities may vary during operation of a device. Thus, a device as disclosed herein may determine error-prone states for a cell or group of cells, and apply data shaping to data written to such cells to reduce the likelihood that writing the data places the cell or cells into an error-prone state. Data shaping may be used, for example, to increase the occurrence of “0” bits within input data, thus avoiding error-prone low voltage states that may be used to represent a series of “1” bits.

Abstract: The present disclosure provides a downlink control information transmission method, including generating more than one downlink control information (DCI) according to scheduling information of a user equipment (UE); determining a detection order of the more than one DCI and positions of the more than one DCI in a searching space; adding a position indication field to a respective DCI according to the detection order of the more than one DCI and the positions of the more than one DCI in the searching space; wherein, the position indication field is used to indicate a position of a next DCI of the respective DCI in the detection order; in which, a position indication field in a last DCI in the detection order is used to indicate a position of a first DCI in the detection order; and transmitting the more than one DCI in the searching space according to the positions of the more than one DCI in the searching space. The present disclosure also provides a UE-side method, a corresponding base station and a UE.

Abstract: In some embodiments, an apparatus is configured to wirelessly communicate with a base station using a first retransmission parameter in a first frame transmission scheme. In some embodiments, the apparatus is configured to determine a current performance metric and, based on the current performance metric, use a second, different retransmission parameter in a second frame transmission scheme for subsequent communications. In some embodiments, the retransmission parameter is a number of retransmissions or a number of hybrid automatic repeat request (HARQ) processes.

Abstract: The present disclosure a method of decoding a polar code based on a shared node, the method includes extracting an input node from target data that are data to be decoded, by an extractor, sorting the input node as one of a first node of which the pattern of the frozen bit satisfies a predetermined first reference, a second node of which the pattern of the information bit satisfies a predetermined second reference, and a third node that is not the first node and the second node, by a sorter, calculating at least one codeword candidate and at least one path metric that correspond to the input node in accordance with the sorting result by a calculator, finishing decoding the target data by iterating the extracting, the sorting as one, and the calculating of at least one path metric by a controller.

Abstract: One embodiment facilitates data placement. During operation, the system monitors a condition of a plurality of blocks of a non-volatile memory. The system determines that a condition of a first block falls below a first predetermined threshold, wherein the first block has a first capacity. The system formats the first block to obtain a second block which has a second capacity, wherein the second capacity is less than the first capacity.

Abstract: Techniques are disclosed for automated detection and notification of interconnect errors or failure. An interconnect is tested via passive or active means. Error data associated with data transferred via the interconnect is measured and analyzed to generate error statistics. Error statistics are then used to determine an error rate of the interconnect and an alert is generated if the error rate exceeds a threshold. Alerts are displayed to users for troubleshooting and/or for indication that the interconnect should be replaced.

Abstract: A first device receives, over a first communications link, a container frame having a payload of a first length. The payload of the container frame includes multiple optical transport unit (OTU) frames of a second length. The first length is not a multiple of the second length. Each of the OTU frames includes an optical data unit (ODU) frame, a sequence of forward error correction (FEC) bits for the ODU frame, and a sequence of error-identifying bits for the ODU frame. The first device determines, based on the sequences of error-identifying bits, a performance of the first communications link.

Abstract: An apparatus, a system and a method use a class of dynamic switching mechanisms with multiple HARQ block sizes to reduce HARQ retransmission overhead while limiting the increase of HARQ ACK feedback overhead. The apparatus includes a first processing unit configured to estimate an intra-subframe fluctuation level of per-codeblock errors; a second processing unit configured to: map the intra-subframe fluctuation level to a hybrid automatic repeat request (HARQ) block size; determine a HARQ acknowledgement (ACK) format based at least in part on the HARQ block size; indicate the selected HARQ block size to a data transmitter; and generate a HARQ ACK. Per-code block link adaptation can be used to support multiple MCSs for a single user in each subframe with fine time-frequency granularity, with low-bandwidth signaling overhead and without a complete dependency on reference signal (RS) structure.

Abstract: Provided herein may be a memory device and a method of operating the memory device. The memory device may include memory cells configured to store data, a peripheral circuit configured to perform program and read operation on memory cells selected from among the memory cells, and a refresh controller configured to include a counter and a refresh manager, wherein the counter is configured to count a number of memory cells which are in an erased state or a programmed state by performing a read operation on the selected memory cells using a reference read voltage, and the refresh manager is configured to compare a read count indicating the counted number of memory cells, with a preset reference count, to determine whether to shift the reference read voltage and to control the peripheral circuit so that the program operation is performed using a voltage different than a program voltage by a step voltage.

Abstract: A controlled active resistance. The active resistance is implemented on an integrated circuit. In some embodiments, the active resistance includes a MOSFET. In alternate embodiments, the active resistance includes a MOSFET and a resistor. The control for the active resistance includes a reference resistor and an operational amplifier. The control for the active resistance further includes two current sources: i) a current source producing a current that is proportional to absolute temperature, and ii) another current source that is produced by a bandgap voltage reference. In one aspect, the active resistance generates an effective resistance that is proportional to thermal voltage. In another aspect, the active resistance generates an effective resistance that is proportional to inverse of the thermal voltage. In an alternate aspect, the current sources have various dependencies, and the active resistance generates an effective resistance that is proportional to those dependencies.

Abstract: A communication unit of the present disclosure includes a decoding section configured to decode transfer data transmitted from a communicated unit, by a first method using a first error detecting code, and a second method using at least an error correcting code, and a determination section that performs determination as to whether the transfer data are data in the first method including the first error detecting code or data in the second method including the error correcting code.

Abstract: A controller sets an error count margin for each of multiple units of a non-volatile memory and detects whether the error count margin of any of the multiple units has been exceeded. In response to detecting that the error count margin of a memory unit is exceeded, the controller determines whether calibration of the memory unit would improve a bit error rate of the memory unit sufficiently to warrant calibration. If so, the controller performs calibration of the memory unit. In some implementations, the controller refrains from performing the calibration in response to determining that calibration of the memory unit would not improve the bit error rate of the memory unit sufficiently to warrant calibration, but instead relocates a desired part or all valid data within the memory unit and, if all valid data has been relocated from it, erases the memory unit.

Abstract: According to one embodiment, a memory includes a non-volatile memory, a first buffer, a first circuit, a second circuit, and a third circuit. The first circuit transfers data from a host to the non-volatile memory through the first buffer. The second circuit executes garbage collection through the first buffer. The first buffer includes a second buffer and a third buffer. The second buffer can be allocated to the first and second circuit. The third buffer can be allocated only to the first circuit. The third circuit includes a timer. The third circuit allocates the first buffer to the first circuit or the second circuit upon writing of data in the non-volatile memory from the second buffer. The third circuit, after data is written into the non-volatile memory from the third buffer, allocates the third buffer to the first circuit at timing based on the timer.

Abstract: A method of driving a display by communicating with a controller through a first channel and a second channel includes; generating recovery data from a signal received through the first channel during a frame data period, detecting a vertical blank period between frame data periods, checking a training trigger event history during the vertical blank period, and during the vertical blank period, transmitting a training request direct to the first channel through the second channel when there is a training trigger event history.

Abstract: Embodiments for a routing module for a first node are disclosed. The routing module includes a computer readable medium having instructions thereon. The instructions cause one or more processing devices to track former links between the first node and a second node and determine a probability of a future link with the second node based on the former links. If the probability of a future link with a second node is above a threshold, an advertisement is sent to at least one other node indicating that the second node is reachable from the first node. If the probability of a future link with the second node is below the threshold and no other route exists from the first node to the second node, an advertisement is sent to at least one other node indicating that the second node is not reachable from the first node.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells in a first time period and manage the set of non-volatile memory cells according to a probability of occurrence of a target FBC in a second time period that is subsequent to the first time period. The probability of occurrence of the target FBC during the second time period is calculated from a model of FBC distribution change of the set of non-volatile memory cells.

Abstract: A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.

Abstract: A first device operates synchronously with a second device, and includes a hardware clock having an adjustable clock frequency and a software clock configured to derive time in dependence on the hardware clock. A controller determines a synchronisation error between the software clock and a clock of the second device, and adjusts the clock frequency of the hardware clock in dependence on the synchronisation error so as to synchronise the hardware clock to a hardware clock of the second device.

Abstract: The disclosure provides a memory device including: a connection interface; a memory array associated with a parameter; and a memory control circuit configured at least to: receive operations, each of the operations being a read operation or a write operation, through the connection interface to perform the operations on the memory array; detect, based on performing the operations on the memory array, a read error which is either a binary 0 read error or a binary 1 read error; update the error counter by incrementing an counter value of the error counter in response to the read error being the binary 1 read error and decreasing the counter value in response to the read error being the binary 0 read error; and adjust the parameter in response to the counter value having reached a positive predetermined threshold or a negative predetermined threshold.

Abstract: A technology for calibrating device-end operational information of a data storage system is shown. A controller operates a non-volatile memory with reference to operational information. A second type of logical address requested by the host that is different from the first type of logical address used in operating a file system of a host is introduced. As indicated by the second type of logical address, the controller receives calibration information from the host and calibrates the operational information based on the calibration information.