Abstract: The present specification relates to a method for transmitting or receiving a signal by a station in a wireless LAN (WLAN) system and, more particularly, provides a method in which when a station transmits or receives a signal through a plurality of spatial streams in a wireless LAN system, the station operates a modulation and coding scheme (MCS) applied to each spatial stream, a method for transmitting or receiving a signal on the basis of the same, and a device therefor.

Abstract: Multi-channel accessing of non-volatile memory. A controller uses three kinds of tables to manage cross-channel accessing areas and, accordingly, to access the non-volatile memory through multiple channels. Each cross-channel accessing area includes M storage units, where M is an integer greater than 1. For each cross-channel accessing area, the first table marks whether there is a need for storage unit substitution and points to substitution information. The substitution information is stored in the second table and the third table. For each cross-channel accessing area marked in the first table, the second table stores M bits corresponding to M storage units of the marked cross-channel accessing area for substitution indication, and related substitute storage unit indication is stored in the third table.

Abstract: Embodiments can include a scan of data associated with programmed memory cells is performed. The scan of data results in a bit error count (BEC) histogram. A trigger margin is determined from the BEC histogram. The determined trigger margin and a target trigger margin are compared. In response to the determined trigger margin being different than the target trigger margin, one or more program step characteristics is adjusted to adjust the determined trigger margin toward the target trigger margin.

Abstract: Described are techniques for customizing a help system. A help system may be received providing help for a product. A proficiency level for a user may be determined in accordance with one or more proficiency criteria including one or more previous interactions of the user with any of the help system and performing an operation using a non-help feature of the product. A customized help system for the user may be determined for the user in accordance with the proficiency level for the user, wherein the customized help system is a modified version of the help system.

Abstract: A system includes a plurality of memory cells. Each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages. The memory cells are read to determine a programmed data state of each memory cell. Error correction decoding is performed to determine a corrected data state of each memory cell. The corresponding cell levels, or programmed voltages, are determined based on the programmed data state and the corrected data state. A first error count represents a total number of error cells that have a higher cell level for the corrected data state than the programmed data state. A second error count represents a total number of error cells that have a lower cell level for the corrected data state than the programmed data state. The system is configured to perform a memory operation based on the first error count and the second error count.

Abstract: A computerized system and method for managing a passive optical network (PON) are disclosed. The system includes a detection and analysis module adapted for receiving uploaded measurement data from an optical line terminal (OLT) and at least one optical network terminal (ONT), and at least one of technical tools data, service failure data, and outside plant data. The detection and analysis module is adapted for determining a source of failure or potential failure in the PON by correlating the uploaded measurement data and the at least one of technical tools data and service failure data with information stored in a memory medium for the OLT and each ONT.

Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.

Abstract: Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Abstract: A resistive memory including a first storage circuit, a verification circuit, a second storage circuit and a control circuit is provided. The first storage circuit includes various cell groups. Each of the cell groups includes at least one memory cell. The verification circuit is coupled to the first storage circuit to verify whether a specific operation performed on at least one of the memory cells was successful. The second storage circuit includes various flag bits. Each of the flag bits corresponds to a cell group. In a reset period, the control circuit is configured to perform a first reset operation or a second reset operation on a first memory cell of a specific cell group among the cell groups according to a specific flag bit corresponding to the specific cell group.

Abstract: An electronic device includes; a timing controller that generates a command to-be-sent to a display driver integrated circuit (DDI) selected from among a plurality of display driver integrated circuits (DDIs) connected to the timing controller through data lines and a shared channel. The DDI is selected by a DDI control signal transferred from the timing controller to the DDI through a corresponding data line among the data lines, and the command is transferred from the timing controller to the DDI through the shared channel.

Abstract: A spectrum management system includes circuitry that obtains information of a primary communication system, where the information includes an interference tolerance of the primary communication system. The circuitry also obtains a desired communication quality for a secondary communication system, and determines available resources for the secondary communication system that result in an interference level below the interference tolerance of the primary communication system. The circuitry then allocates resources to the secondary communication system based on a comparison of an estimated communication quality of the secondary communication system if the available resources are used and the desired communication quality.

Abstract: Methods and systems are provided for prioritizing a plurality of maintenance corrective actions in a troubleshooting chart for a device are provided. The method includes receiving, by a processor, an input from a user indicative of a successful corrective action from the plurality of corrective actions on the troubleshooting chart and incrementing a value of a counter associated with the successful corrective action. The processor then compares values for counters associated with each of the plurality of corrective actions and displays the plurality of corrective actions in hierarchal order based on the values of the counters.

Abstract: Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information (FIGS. 7-9), and can be compatibly used in different wireless networks by means of message standardization.

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.

Abstract: In an illustrative example, a method includes sensing at least a portion of a representation of a convolutional low-density parity-check (CLDPC) codeword stored at a memory of a data storage device. The method further includes receiving the portion of the representation of the CLDPC codeword at a controller of the data storage device. The method further includes performing one or more management operations associated with the memory based on an estimated number of errors of the portion of the representation of the CLDPC codeword.

Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.

Abstract: A method for determining a transmit power in a coverage enhancement scenario and a device resolve a problem that the prior art lacks a solution to determining a transmit power of a preamble sequence in a random access process in the coverage enhancement scenario. The method includes: obtaining, by a terminal, configuration information that is used to determine a transmit power used for transmitting a signal at each coverage enhancement level; and determining, by the terminal according to the obtained configuration information, a transmit power used for transmitting the signal at a coverage enhancement level currently used by the terminal, so as to determine the transmit power used for transmitting the signal in the coverage enhancement scenario.

Abstract: A data storage system includes a controller that controls a non-volatile memory array including a plurality of garbage collection units of physical memory. For each of the plurality of garbage collections units storing valid data, the controller determines an invalidation metric and a health-based adjustment of the invalidation metric. The controller selects a garbage collection unit on which to perform garbage collection from among a plurality of garbage collections units predominately based on the invalidation metric for the garbage collection unit and also based on the health-based adjustment for the garbage collection unit. In response to selection of the garbage collection unit, the controller performing garbage collection for the garbage collection unit.

Abstract: A method includes detecting different data patterns in data read from a portion of a non-transitory data storage medium. Bit errors in the different data patterns are then determined. Further, bits in error for a total number of bits in each of the different data patterns are calculated from the determined bit errors in the different data patterns.

Abstract: A method of setting an upper limit value of the number of write times, which is applied to a magnetic disk device including a disk and a head configured to write data to the disk and read the data from the disk, includes measuring a plurality of bit error rates in a recording area of the disk upon repeatedly writing to an area of the disk adjacent to the recording area a number of write times, deriving a function that approximates a bit error rate in relation to a number of write times, using the measured bit rates corresponding to at least a first number of write times, a second number of write times, and a third number of write times, and applying the function to determine a number of write times that correspond to a first threshold bit error rate that makes the data on the disk unreadable, and setting the determined number of write times as the upper limit value of the number of write times.

Abstract: A network device receives an enrollment request from a first device to enroll in a brokered communication protocol for communicating with at least one second device. The network device transmits, to the first device, a test vector and a measurement request, and receives, from the first device responsive to the measurement request, a measurement of at least one of a bit-error-rate (BER) and/or a signal-to-noise ratio (SNR) based on receipt of the test vector at the first device. The network device determines if the first device is vulnerable to message interception or eavesdropping based on the measurement of the BER and/or the SNR, and denies the first device access, by the network device, to the brokered communication protocol based on whether the first device is determined to be vulnerable to message interception or eavesdropping.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system trigger threshold or an uncorrectable error correction condition threshold, which are set based on the error correction capabilities of a memory system. Formulating the comparison to these metrics can include determining a margin between the CDF-based data at a particular codeword frequency and one of the thresholds.

Abstract: When the reception level of a main tuner (3) is equal to or lower than a first threshold or the reception level of a sub tuner (4) is equal to or lower than a second threshold while the sub tuner (4) performs data service reception, a sub tuner processing control unit (90), a broadcast program search control unit (91), and a data service control unit (93) cause the sub tuner (4) to suspend the running data service reception and start a broadcast program search. Then, while the reception level of the main tuner (3) is equal to or lower than the first threshold or the reception level of the sub tuner (4) is equal to or lower than the second threshold, the sub tuner processing control unit (90) and the broadcast program search control unit (91) cause the sub tuner (4) to repeatedly and continuously perform a broadcast program search.

Abstract: The present disclosure relates to suppressing malicious transmissions by overriding frames on a Controller Area Network (CAN) bus. In an embodiment, a method operates by determining when a frame arrives at a CAN bus. A determination of whether to override the frame is made based on an arbitration ID of the frame received from the CAN bus. In response to determining to override the frame, a predetermined sequence of bits is transmitted on the CAN bus during transmission of a data length code (DLC) field in the frame. A message to complete the frame is generated based on the predetermined sequence of bits. Then, the message is transmitted on the CAN bus.

Abstract: A storage controller coupled to a storage array comprising one or more storage devices receive a request to write data to one of the storage devices. The storage controller determines a first data block on the storage device comprising a list of deallocated data blocks on the storage device, the list comprising a block number of each deallocated data block and an access operation count value at which each deallocated data block was deallocated. The storage controller identifies a second data block from the list of deallocated data blocks on the storage device based on a corresponding access operation count value from the list and writes the data to the second data block.

Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

Abstract: A processor includes: an error checking and correcting information generating unit; a storage unit configured to store data to which error checking and correcting information and error uncorrectable information are added when an error is detected and configured to store data to which error checking and correcting information is added when an error is not detected; and a processing unit configured to read out all data which the storage unit stores and configured to check an error of each piece of read-out data based on error checking/correcting information added to each piece of all the read-out data when an arithmetic unit detects an error, and configured to correct data in which an error is detected based on error checking and correcting information when a correctable error is detected.

Abstract: An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.

Abstract: Embodiments are generally directed to display controller testing through a high speed communications switch. An embodiment of an apparatus includes a display controller including a first test machine; a high speed switch coupled with the display controller; and one or more physical layer (PHY) logic elements including a first PHY with a second test machine, the first test machine and second test machine being replicas of each other at least in part. The first test machine and the second test machine are operable to synchronously lock with each other, the first test machine to generate a data sequence and transmit the data sequence to the second test machine, the second test machine to generate an expected data sequence and compare the expected data sequence to a received data sequence from the first test machine.

Abstract: A non-transitory computer readable medium storing a program causing a computer to execute a process, the process including: selecting in a case where an error occurs in communication between a communication device and a communication target device, a setting item to be changed in order to handle the occurred error by referring to information in which a type of an error is previously correlated with a setting item to be changed; acquiring a setting value of another communication device regarding the selected setting item; and determining a setting value of the communication device based on the acquired setting value of the other communication device.

Abstract: A cache memory system has a nonvolatile memory which includes a first region and a second region, the first region storing readable and writable data, the second region storing an ECC for correcting an error of the data in the first region, an error corrector which generates the ECC and carries out an error correction of the data in the first region with the ECC, error rate determination circuitry which determines an error rate of the data in the first region, and region size adjustment circuitry which adjusts a size of the second region inside the nonvolatile memory based on the error rate.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells, obtain one or more metrics of a cumulative distribution of the FBCs, calculate an indicator from the one or more metrics of the cumulative distribution of the FBCs and a target FBC, obtain a probability for the target FBC from the indicator, and manage at least one of: garbage collection, wear leveling, and read threshold voltage adjustment of the set of non-volatile memory cells according to the probability for the target FBC.

Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.

Abstract: A method for testing a cloud streaming server, and an apparatus and a system therefor are disclosed. Test result videos are created by receiving, from cloud streaming servers, test results corresponding to the key input of a preset test script; masked videos are created by masking the test result videos; and it is determined whether at least any one of the cloud streaming servers has a failure by mutually comparing test result images created by capturing the masked videos.

Abstract: A system may obtain a current bit error count that identifies a quantity of bit errors in a bit stream during a time interval. The system may determine that the current bit error count identifies one or more bit errors. The system may determine whether an estimated bit error rate (BER) for the bit stream is likely to satisfy a threshold. The system may select an approach for determining the estimated BER for the bit stream. The estimated BER may be determined based on combining the current bit error count with a quantity of bits received in the time interval when the estimated BER is likely to exceed the threshold, and the estimated BER may be determined based on the current bit error count and one or more past bit error counts when the estimated BER is unlikely to exceed the threshold. The system may determine the estimated BER.

Abstract: A non-transitory computer readable medium stores a program causing a computer to execute a process for communicating. The process includes: when a connection error with a communication target device occurs, querying by transmitting equipment information acquired from the communication target device to a communication management server that manages information related to connection availability with the communication target device and procedures for connection errors; and displaying a connection availability with the communication target device or a procedure for the connection error, according to a result of the querying.

Abstract: According to an example, motion-aware MCS adaptation may include determining whether a device is static relative to a wireless AP, moving towards the wireless AP, or moving away from the wireless AP. A device static rate probing interval, a device moving rate probing interval, first and second frame retransmission limits, a device static PER smoothing factor, and a device moving PER smoothing factor may be determined. In response to a determination that the device is static relative to the wireless AP, moving towards the wireless AP, or moving away from the wireless AP, an appropriate rate probing interval, an appropriate frame retransmission limit, and an appropriate PER smoothing factor may be used to determine a MCS value from a plurality of available MCS values to be used for transmitting data between the device and the wireless AP.

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

Abstract: An event clearinghouse engine is used with a data storage system to modify event disposition associated with components. A separate component disposition table is provided for each component. The component disposition table specifies different sets of disposition modifications for different types of events as indicated by event ID. A global disposition rule mapping table includes disposition modifications which are applied to all events. Per-vendor and per-tenant tables may be used to specify disposition modifications for particular vendors and tenants. Mode-specific tables such as a rescue/recovery mode table may be used to specify disposition modifications when the storage system is in a particular mode. The tables may be implemented in stages, including parallel and serial application.

Abstract: An electronic device is provided. The electronic device includes a memory in which contact information is stored, a communication circuit configured to receive at least one piece of contact information from the outside, and a processor configured to unify language scripts between a name of the stored contact information and a name of the received contact information and determine whether to integrate the stored contact information and the received contact information by comparing the name of the stored contact information with the name of the received contact information in a unified language script.

Abstract: Even when a main board is replaced, if no change is made to a connected storage unit, existent mirroring information is obtained to resume mirroring function processing. An information processing apparatus that performs mirroring to store same data in a plurality of storage units includes a first storage unit configured to store mirroring information indicating a state of the mirroring in a memory of a main board, a second storage unit configured to store the mirroring information in a memory of a sub board, a detection unit configured to detect replacement of the main board, and a restoration unit configured to restore the mirroring information stored in the memory of the sub board by the second storage unit in a memory of a replaced main board in accordance with detection of the replacement of the main board by the detection unit.

Abstract: A last written page in an open block in NAND flash is identified where the NAND flash includes a plurality of pages and the last written page has first content. Second content is written to an adjacent page in the open block, wherein the adjacent page is physically adjacent to the last written page in the open block and the second content enhances robustness of the first content.

Abstract: Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information (FIGS. 7-9), and can be compatibly used in different wireless networks by means of message standardization.

Abstract: An apparatus may include a circuit that performs one or more read and recovery operations for one or more data segments including updating an outer code syndrome for one or more recovered data segments recovered by the one or more read and recovery operations and preventing updates of the outer code syndrome for one or more failed data segments not recovered by the one or more read and recovery operations.

Abstract: Systems and methods are disclosed for performing segment-based outer code recovery at a data storage device. An apparatus may comprise a circuit configured to disable outer code error recovery, and perform a read operation spanning a plurality of segments of a data storage medium, a segment including a plurality of sectors. The circuit may identify one or more segments from the plurality of segments that have one or more sectors with an error. For an identified segment of the one or more segments, the circuit may perform a re-read operation with outer code error recovery enabled, and perform outer code recovery on sectors with an error within the identified segment.

Abstract: One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second result from reading the codeword with the second trim level, and a third result from reading the codeword with the third trim level can be accumulated. An erasure of a detected unit sequence can be computed. The detected unit sequence can be modified by changing a unit in a position of the detected unit sequence corresponding to a position of the erasure. The modified detected unit sequence can be ECC decoded.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating an Enhanced Directional Multi Gigabit (EDMG) support indication. For example, a wireless station may be configured to generate a frame having a structure compatible with a Directional Multi Gigabit (DMG) frame structure, the frame including an EDMG supported field to indicate that the wireless station supports one or more EDMG features; and to transmit the frame over a DMG channel.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.