Abstract: When the reception level of a main tuner (3) is equal to or lower than a first threshold or the reception level of a sub tuner (4) is equal to or lower than a second threshold while the sub tuner (4) performs data service reception, a sub tuner processing control unit (90), a broadcast program search control unit (91), and a data service control unit (93) cause the sub tuner (4) to suspend the running data service reception and start a broadcast program search. Then, while the reception level of the main tuner (3) is equal to or lower than the first threshold or the reception level of the sub tuner (4) is equal to or lower than the second threshold, the sub tuner processing control unit (90) and the broadcast program search control unit (91) cause the sub tuner (4) to repeatedly and continuously perform a broadcast program search.

Abstract: The present disclosure relates to suppressing malicious transmissions by overriding frames on a Controller Area Network (CAN) bus. In an embodiment, a method operates by determining when a frame arrives at a CAN bus. A determination of whether to override the frame is made based on an arbitration ID of the frame received from the CAN bus. In response to determining to override the frame, a predetermined sequence of bits is transmitted on the CAN bus during transmission of a data length code (DLC) field in the frame. A message to complete the frame is generated based on the predetermined sequence of bits. Then, the message is transmitted on the CAN bus.

Abstract: A storage controller coupled to a storage array comprising one or more storage devices receive a request to write data to one of the storage devices. The storage controller determines a first data block on the storage device comprising a list of deallocated data blocks on the storage device, the list comprising a block number of each deallocated data block and an access operation count value at which each deallocated data block was deallocated. The storage controller identifies a second data block from the list of deallocated data blocks on the storage device based on a corresponding access operation count value from the list and writes the data to the second data block.

Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

Abstract: A processor includes: an error checking and correcting information generating unit; a storage unit configured to store data to which error checking and correcting information and error uncorrectable information are added when an error is detected and configured to store data to which error checking and correcting information is added when an error is not detected; and a processing unit configured to read out all data which the storage unit stores and configured to check an error of each piece of read-out data based on error checking/correcting information added to each piece of all the read-out data when an arithmetic unit detects an error, and configured to correct data in which an error is detected based on error checking and correcting information when a correctable error is detected.

Abstract: An apparatus of a memory system and an operating method thereof includes: a plurality of memory devices; and a controller including a decoder and a BER predictor, coupled with the plurality of memory devices, configured to perform a decoding iteration includes to conduct NAND read and generate NAND data; decode in accordance with the NAND data and generate decoder information by the decoder; predict a BER in accordance with at least the decode information by the BER predictor; and evaluate the predicted BER and generate evaluation result by the BER predictor.

Abstract: Embodiments are generally directed to display controller testing through a high speed communications switch. An embodiment of an apparatus includes a display controller including a first test machine; a high speed switch coupled with the display controller; and one or more physical layer (PHY) logic elements including a first PHY with a second test machine, the first test machine and second test machine being replicas of each other at least in part. The first test machine and the second test machine are operable to synchronously lock with each other, the first test machine to generate a data sequence and transmit the data sequence to the second test machine, the second test machine to generate an expected data sequence and compare the expected data sequence to a received data sequence from the first test machine.

Abstract: A non-transitory computer readable medium storing a program causing a computer to execute a process, the process including: selecting in a case where an error occurs in communication between a communication device and a communication target device, a setting item to be changed in order to handle the occurred error by referring to information in which a type of an error is previously correlated with a setting item to be changed; acquiring a setting value of another communication device regarding the selected setting item; and determining a setting value of the communication device based on the acquired setting value of the other communication device.

Abstract: A cache memory system has a nonvolatile memory which includes a first region and a second region, the first region storing readable and writable data, the second region storing an ECC for correcting an error of the data in the first region, an error corrector which generates the ECC and carries out an error correction of the data in the first region with the ECC, error rate determination circuitry which determines an error rate of the data in the first region, and region size adjustment circuitry which adjusts a size of the second region inside the nonvolatile memory based on the error rate.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells, the one or more control circuits are configured to collect failure bit counts (FBCs) for data read from the set of non-volatile memory cells, obtain one or more metrics of a cumulative distribution of the FBCs, calculate an indicator from the one or more metrics of the cumulative distribution of the FBCs and a target FBC, obtain a probability for the target FBC from the indicator, and manage at least one of: garbage collection, wear leveling, and read threshold voltage adjustment of the set of non-volatile memory cells according to the probability for the target FBC.

Abstract: Detecting a defective cell in a memory in consideration of an error property difference depending on the storage state. A determination unit determines whether there is a possibility of defect for each of unit-of-storages on a memory cell formed with a non-volatile memory. The non-volatile memory undergoes either a reset operation that transitions a state from a low resistive state (LRS) to a high resistive state (HRS) or a set operation that transitions the state from the high resistive state to the low resistive state. The determination unit determines a unit-of-storage in which the number of errors in predetermined one of the reset operation and the set operation has exceeded a predetermined standard, as a unit-of-storage suspected of having a defect.

Abstract: A method for testing a cloud streaming server, and an apparatus and a system therefor are disclosed. Test result videos are created by receiving, from cloud streaming servers, test results corresponding to the key input of a preset test script; masked videos are created by masking the test result videos; and it is determined whether at least any one of the cloud streaming servers has a failure by mutually comparing test result images created by capturing the masked videos.

Abstract: A system may obtain a current bit error count that identifies a quantity of bit errors in a bit stream during a time interval. The system may determine that the current bit error count identifies one or more bit errors. The system may determine whether an estimated bit error rate (BER) for the bit stream is likely to satisfy a threshold. The system may select an approach for determining the estimated BER for the bit stream. The estimated BER may be determined based on combining the current bit error count with a quantity of bits received in the time interval when the estimated BER is likely to exceed the threshold, and the estimated BER may be determined based on the current bit error count and one or more past bit error counts when the estimated BER is unlikely to exceed the threshold. The system may determine the estimated BER.

Abstract: A non-transitory computer readable medium stores a program causing a computer to execute a process for communicating. The process includes: when a connection error with a communication target device occurs, querying by transmitting equipment information acquired from the communication target device to a communication management server that manages information related to connection availability with the communication target device and procedures for connection errors; and displaying a connection availability with the communication target device or a procedure for the connection error, according to a result of the querying.

Abstract: According to an example, motion-aware MCS adaptation may include determining whether a device is static relative to a wireless AP, moving towards the wireless AP, or moving away from the wireless AP. A device static rate probing interval, a device moving rate probing interval, first and second frame retransmission limits, a device static PER smoothing factor, and a device moving PER smoothing factor may be determined. In response to a determination that the device is static relative to the wireless AP, moving towards the wireless AP, or moving away from the wireless AP, an appropriate rate probing interval, an appropriate frame retransmission limit, and an appropriate PER smoothing factor may be used to determine a MCS value from a plurality of available MCS values to be used for transmitting data between the device and the wireless AP.

Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

Abstract: An event clearinghouse engine is used with a data storage system to modify event disposition associated with components. A separate component disposition table is provided for each component. The component disposition table specifies different sets of disposition modifications for different types of events as indicated by event ID. A global disposition rule mapping table includes disposition modifications which are applied to all events. Per-vendor and per-tenant tables may be used to specify disposition modifications for particular vendors and tenants. Mode-specific tables such as a rescue/recovery mode table may be used to specify disposition modifications when the storage system is in a particular mode. The tables may be implemented in stages, including parallel and serial application.

Abstract: An electronic device is provided. The electronic device includes a memory in which contact information is stored, a communication circuit configured to receive at least one piece of contact information from the outside, and a processor configured to unify language scripts between a name of the stored contact information and a name of the received contact information and determine whether to integrate the stored contact information and the received contact information by comparing the name of the stored contact information with the name of the received contact information in a unified language script.

Abstract: Even when a main board is replaced, if no change is made to a connected storage unit, existent mirroring information is obtained to resume mirroring function processing. An information processing apparatus that performs mirroring to store same data in a plurality of storage units includes a first storage unit configured to store mirroring information indicating a state of the mirroring in a memory of a main board, a second storage unit configured to store the mirroring information in a memory of a sub board, a detection unit configured to detect replacement of the main board, and a restoration unit configured to restore the mirroring information stored in the memory of the sub board by the second storage unit in a memory of a replaced main board in accordance with detection of the replacement of the main board by the detection unit.

Abstract: A last written page in an open block in NAND flash is identified where the NAND flash includes a plurality of pages and the last written page has first content. Second content is written to an adjacent page in the open block, wherein the adjacent page is physically adjacent to the last written page in the open block and the second content enhances robustness of the first content.

Abstract: Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information (FIGS. 7-9), and can be compatibly used in different wireless networks by means of message standardization.

Abstract: An apparatus may include a circuit that performs one or more read and recovery operations for one or more data segments including updating an outer code syndrome for one or more recovered data segments recovered by the one or more read and recovery operations and preventing updates of the outer code syndrome for one or more failed data segments not recovered by the one or more read and recovery operations.

Abstract: Systems and methods are disclosed for performing segment-based outer code recovery at a data storage device. An apparatus may comprise a circuit configured to disable outer code error recovery, and perform a read operation spanning a plurality of segments of a data storage medium, a segment including a plurality of sectors. The circuit may identify one or more segments from the plurality of segments that have one or more sectors with an error. For an identified segment of the one or more segments, the circuit may perform a re-read operation with outer code error recovery enabled, and perform outer code recovery on sectors with an error within the identified segment.

Abstract: One example of erasure-assisted error correction code (ECC) decoding can include reading a codeword with a first trim level, reading the codeword with a second trim level, and reading the codeword with a third trim level. A first result from reading the codeword with the first trim level, a second result from reading the codeword with the second trim level, and a third result from reading the codeword with the third trim level can be accumulated. An erasure of a detected unit sequence can be computed. The detected unit sequence can be modified by changing a unit in a position of the detected unit sequence corresponding to a position of the erasure. The modified detected unit sequence can be ECC decoded.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating an Enhanced Directional Multi Gigabit (EDMG) support indication. For example, a wireless station may be configured to generate a frame having a structure compatible with a Directional Multi Gigabit (DMG) frame structure, the frame including an EDMG supported field to indicate that the wireless station supports one or more EDMG features; and to transmit the frame over a DMG channel.

Abstract: A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

Abstract: A method and a memory controller for accessing a non-volatile memory are disclosed. The method includes reading a first memory region of the non-volatile memory, ascertaining whether the first memory region contains a predetermined data pattern wherein the predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region, wherein the data status indicates at least one of whether valid data is present within the second memory region and whether the second memory region is writable.

Abstract: According to one embodiment, a distribution of threshold voltages of a plurality of memory cells is acquired from a nonvolatile memory which includes the plurality of memory cells, a malfunction state occurring in the nonvolatile memory is identified based on a shape of the distribution, and a read voltage when data is read out of the nonvolatile memory is set to a voltage value corresponding to a type of the malfunction state.

Abstract: A method and an apparatus for performing a Superposition Coded Modulation (SCM) scheme in a broadcasting or communication system including a controller are provided. The method includes controlling an SCM coefficient by the controller. The SCM coefficient is controlled according to a channel capacity of each layer of one or more layers in which information included in a signal is encoded.

Abstract: A method for execution by one or more processing modules of one or more computing devices of a dispersed storage network (DSN) begins by identifying an unrecoverable encoded data slice of a data segment stored in a set of DSN storage units, where a region of a data object includes a plurality of data segments, and where the plurality of data segments includes the data segment. The method continues by determining whether the data segment is recoverable. The method continues, when recoverable, by salvaging the region by indicating that the region has corruption, updating a directory and replacing the data segment with filler data, and when not recoverable, by not salvaging the region by indicating that the region has been eliminated.

Abstract: Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage.

Abstract: A method for enhancing image quality of compressed video stream, mirrored thorough wireless network using a compression scheme, between a source device and a sink device. The method includes identifying idle time in the compression scheme of video, where the image change is below a predefined threshold for pre-defined period of time, calculating color code corrections between an original source last image and a decoded last image, sending corrections from the source device to the sink device in real-time during identified idle time and performing an image correction at the sink device based on the received correction.

Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.

Abstract: System, methods and apparatus are described that model analog behavior in a multi-wire, multi-phase communications link. A digital signal representative of a physical connection in a communications link and a virtual signal characterizing a three-phase signal transmitted over the physical connection are generated. The virtual signal may be configured to model one or more analog characteristics of the physical connection. The analog characteristics may include voltage states defining the three-phase signal. The analog characteristics of the physical connection include at least three voltage states corresponding to signaling states of the three-phase signal.

Abstract: A system including a wireless device configured to apply selective error correction coding to data content to produce first data and second data, wherein the first and the second data being error correction coded differently; maintain the first data and the second data in a non-volatile memory of the wireless device; receive an electromagnetic signal for powering the wireless device; and transmit the first data and the second data over a short-range wireless link. The system further includes an apparatus configured to transmit an electromagnetic signal for powering the wireless device; receive first and second data over a short-range wireless link, wherein the first data and the second data being error correction coded differently; and apply selective error correction decoding to the first data and the second data to produce data content.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are provided. The method includes: configuring a default encoding rule for a first physical erasing unit which includes encoding data to be stored to the first physical erasing unit based on a default code rate; configuring a first encoding rule, for the first physical erasing unit according to error estimating information of the first physical erasing unit, which includes encoding data to be stored to a first-type physical programming unit and a second-type physical programming unit belonging to the first physical erasing unit based on a first code rate and a second code rate respectively, where a value of the first code rate is greater than a value of the default code rate, and a value of the second code rate is less than the value of the default code rate.

Abstract: Embodiments of the present disclosure provide a method, computer program product, and system for monitoring a dynamic random-access memory (DRAM) device to detect and respond to a cryogenic attack. A processor receives a set of memory information about a DRAM device. The processor then determines a set of error indicators by processing the memory information using a set of decision parameters. The error indicators are then compared to an attack syndrome to determine if the DRAM is experiencing a cryogenic attack. If the DRAM is experiencing a cryogenic attack, access to the DRAM device is disabled.

Abstract: A method for extending period of data retention of a flash memory device and a device for the same are disclosed. In the present invention, the temperature of the flash memory device is detected by a temperature sensor. According to the temperature and P/E cycles of the flash memory device, a safe period is obtained for the data retention of the flash memory device. By refreshing each block of the flash memory device during the safe period, the data retention period is refreshed, and the data stored in the flash memory device can be prevented from bit error caused by exceeding data retention period or read disturb.

Abstract: A Solid State Drive (SSD) that includes a host connector receptacle for connecting to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The nonvolatile memory controller is configured to perform program operations and read operations on memory cells of each of the NAND devices. The nonvolatile memory controller includes a program step circuit configured to initially program memory cells of each of the NAND devices using an initial program step voltage and is configured to change the program step voltage used to program the memory cells of each of the NAND devices during the lifetime of each of the NAND devices.

Abstract: A data storage device may include a non-volatile memory and a controller. According to a first aspect, a bit error rate (BER) estimate may be determined at a memory interface of the controller based on hard bit data from the non-volatile memory. The BER estimate may be used to determine, prior to transfer of the hard bit data to an error correction coding (ECC) decoder of the controller, whether to request transfer of soft bit data from the non-volatile memory. According to a second aspect, the ECC decoder may be instructed to initiate decoding of a codeword or sub code using a particular operating mode based on the BER estimate for the codeword or sub code. According to a third aspect, sub codes of an ECC codeword may be reordered based on BER estimates for the sub codes, and the reordered sub codes may be provided to the ECC decoder.

Abstract: Apparatuses, systems, and methods are disclosed for managing configuration parameters for non-volatile data storage. A control module is configured to manage differences in one or more storage characteristics for blocks of a non-volatile memory medium within one or more established limits. A block classification module is configured to group blocks of a non-volatile memory medium based on one or more other storage characteristics. A configuration parameter module is configured to use a configuration parameter for at least one group of blocks based on a grouping. A configuration parameter update module is configured to update a configuration parameter for at least one group in response to a change in one or more managed storage characteristics.

Abstract: A method for link adaptation at a mobile station can include the steps of computing mutual information per coded bit (MIB) metrics on at least one sub-channel for one or more candidate modulation types. The method may average the MIB metrics over at least two sub-channels, generate feedback information including MIB metrics for the plurality of candidate modulation types, and transmit the feedback information to a base station.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.

Abstract: Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing the poisoned state if volatile data stored in the memory region does not correspond to a known data pattern. Additionally, the memory region may be maintained in the poisoned state if the volatile data stored in the memory region corresponds to the known data pattern. In one example, an error may be detected, wherein the error is associated with a write operation directed to the memory region. In such a case, the poisoned state may be set for the volatile data in response to the error and the known data pattern may be written to the memory region.

Abstract: A recording/reproducing device and a recording/reproducing method, which are capable of improving reliability of data while securing compatibility with a file format employed in a recording medium are provided. Provided is a reconstruction method of reproduction data acquired from a reproducing device that reproduces data from a recording medium in which the data is recorded, performs error correction using a second error correction code specified in a file format employed in the recording medium, and outputs reproduction data, and the reconstruction method of the reproduction data includes obtaining reproduction data from the reproducing device, reading a first error correction code different from the second error correction code from the reproduction data, and performing error correction on the reproduction data using the first error correction code and reconstructing user data.

Abstract: In a method for controlling data stored in an Solid State Disk (SSD) of a data de-duplication system, a storage controller obtains stability information of a data block. The stability information comprises a reference count of the data block and a length of a period of time when the data block is stored in the SSD. The storage controller identifies a stability level of the data block according to the stability information, and sends the stability level of the data block to the SSD. The SSD moves the data block to a target block which corresponds to the stability level. Thereby, the SSD can store data blocks having a same stability level together.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

Abstract: Efficient production testing of integrated circuits (ICs). A first production test is implemented on a group of ICs and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that ICs having a recoverable fail and ICs having a non-recoverable fail are differentiated. The ICs are integrated based on the analyzed results and a second production test is implemented. The second production test tests the ICs responsive to the segregation, such that the second production test is limited only to ICs with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having ICs not to be re-tested.