Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in memory locations that are within a range of memory locations. If the multiple memory locations are within the range of memory locations, the processing device may continue with a recovery process. If one of the multiple memory locations is outside of the range of memory locations, the processing device may halt the recovery process.

Abstract: Efficient production testing of integrated circuits (ICs). A first production test is implemented on a group of ICs and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that ICs having a recoverable fail and ICs having a non-recoverable fail are differentiated. The ICs are integrated based on the analyzed results and a second production test is implemented. The second production test tests the ICs responsive to the segregation, such that the second production test is limited only to ICs with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having ICs not to be re-tested.

Abstract: Techniques to train a personal area network component may include obtaining a packet error rate from a personal area network component. It may be determined that the packet error rate is greater than a packet error rate threshold after a time period. A reservation may be requested from a wide area network component based a first transmit pattern from the personal area network component. A second or adjusted transmit pattern from the wide area network component may be received. Personal area network signals may be transmitted based on the second transmit pattern. The time period may be adjusted based on a personal area network packet error rate of the second transmit pattern. Other embodiments are described and claimed.

Abstract: Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ECC coverage areas, and control circuitry configured to adjust a size of one or more of the ECC coverage areas.

Abstract: Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, a system includes a hardware processor and logic integrated with and/or executable by the processor or media access control (MAC) functionality of a network port. The logic is configured to negotiate a credit aging duration during initialization of a link between a receiving endpoint and a sending endpoint, the receiving and sending endpoints being connected in a network fabric. The link includes at least one virtual link. The logic is also configured to receive an amount of available flow credits from the receiving endpoint and transmit one or more packets to the receiving endpoint. The amount of available flow credits are used to determine a capacity to process packets at the receiving endpoint. The exchange of flow credits is performed on a per virtual link basis. Other systems, methods, and computer program products are presented according to more embodiments.

Abstract: Described are methods, systems, and apparatus, including computer program products for error correction coding and decoding procedures for data storage or transfer. A plurality of data blocks is received. A plurality of checksum blocks are generated by multiplying the plurality of data blocks by a coding matrix, where the coding matrix comprises values of at least one basic interpolation polynomial and the multiplying is according to a finite field arithmetic for a finite field comprising all possible values of the plurality of data blocks and the plurality of coding blocks. The plurality of data blocks and the plurality of checksum blocks are stored in a data storage medium.

Abstract: A radio access network node (e.g., base station system), a mobile station, and various methods are described herein that increase the size and/or efficiency of an ack/nack bitmap in one or more control messages (e.g., Packet Downlink Ack/Nack message(s)). The mobile station when operating in a Downlink Multi Carrier mode sends the one or more control messages to the radio access network node.

Abstract: Controller and method for requesting arbitration of a queue. The controller comprises a coalescing engine for determining a number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied. The method comprises determining the number of commands in a queue and requesting arbitration of the queue when a coalescing condition is satisfied.

Abstract: Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.

Abstract: A data storage device including a flash memory and a controller. The controller performs a first read operation on the pages of a first block of a first block group, and performs a maintenance process to determine whether the first group read count of the first block group is greater than a read threshold when the first read operation is finished. The controller scans the blocks of the first block group to obtain a plurality of first error bit numbers when the first group read count is greater than the read threshold, and updates the block corresponding to the first error bit number that is greater than an error-bit threshold.

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

Abstract: A method of programming target memory cells of a nonvolatile memory device includes; programming the target memory cells using an incrementally adjusted program time, reading a code word stored by the target memory cells and determining a bit error rate (BER) associated with the target memory cells in view of the read code word, and if the BER exceeds an upper BER limit, increasing the program time by a unit time.

Abstract: Embodiments of the present disclosure provide a signal processing method and device. The method includes: receiving soft information corresponding to encoded signals sent by at least two base stations and CRC check results of decoding results of first subflows in the encoded signals, where the soft information includes first soft information corresponding to the first subflows; obtaining a selective combining result of the first subflows by performing selective combining according to the at least two CRC check results of the decoding results of the first subflows; and if the selective combining result of the first subflows is that CRC check is incorrect, determining a soft combining result of the first subflows according to at least two pieces of the first soft information. The signal processing method and device provided in the embodiments can increase a signal gain.

Abstract: A packetized streaming media delivery network carries many “streams” of differing media content. They often are from multiple sources and of different media types. The invention consists of a scalable hardware and/or software computing element resolving the network traffic into its individual streams for focused, simultaneous, and continuous real-time monitoring and analysis. The monitoring and analysis consists of delay factor and media loss rate which measure the cumulative jitter of the streaming media within the delivery network and the condition of the media payload. These measurements form a powerful picture of network problem awareness and resolution. The delay factor objectively indicates the contribution of the network devices in the streams' path, allowing for both problem prediction and indication. In one example, tapping a packetized network at various locations allows for correlation of the same-stream performance at various network points to pinpoint the source(s) of the impairment(s).

Abstract: Systems, methods and/or devices are used to enable triggering a process to reduce declared capacity of a storage device in a multi-storage-device storage system. In one aspect, the method includes: (1) obtaining, for each storage device of a plurality of storage devices of the storage system, one or more metrics of the storage device, the storage device including non-volatile memory, (2) detecting a trigger condition for reducing declared capacity of the non-volatile memory of a respective storage device of the plurality of storage devices, the trigger condition detected in accordance with the one or more metrics of one or more storage devices, and (3) enabling an amelioration process associated with the detected trigger condition, the amelioration process to reduce declared capacity of the non-volatile memory of the respective storage device. In some embodiments, the respective storage device includes one or more flash memory devices.

Abstract: Integrated circuits such as application specific integrated circuits or programmable logic devices may include sequential elements such as configurable register circuitry. Such configurable register circuitry may operate as independent registers controlled by selectable clock signals or as a single register with error detection and error correction capabilities. For example, the configurable register circuitry when operated as single register with error detection and error correction circuitry may detect and correct runtime errors caused by manufacturing and environmental variations, thereby allowing an increase in the clock rate that controls the register. If desired, the configurable register circuitry may be configured to detect single event upsets, which may enable the implementation of safe finite state machines.

Abstract: A transmission device transmitting a polarization-multiplexed optical signal includes: a frame encoder configured to encode an electric signal in accordance with a predetermined frame format; an error correction encoder configured to provide encoded signal data as a result of the encoding by the frame encoder with a predetermined error correction code; and a transmission loss information acquiring part configured to acquire transmission loss information based on a loss that the encoded signal data provided with the error correction code incurs when the encoded signal data is transmitted, from a receiving device as a transmission destination. The error correction encoder adjusts a redundancy of the error correction code given to the encoded signal data, based on the transmission loss information acquired by the transmission loss information acquiring part.

Abstract: A management device includes a measurement data storage unit configured to store measurement data transmitted from a substrate processing apparatus; a setting unit configured to set an item of the measurement data as a determination target, reference data, and upper and lower limit values with respect to the reference data; a counting unit configured to count the number of times that the value of the measurement data corresponding to the item exceeds the upper and lower limit values; and a determining unit configured to determine that the measurement data as a determination target is abnormal, when the counted number exceeds a predetermined value.

Abstract: The invention uses a PRBS pattern generated by transmitter (serializer) as training. At the receiver side, following receiver outputs, a synchronous capturing module is used to capture multiple lanes simultaneously. The captured data is used to calculate the PRBS distance for different lanes. After the distances are obtained, the one with largest latency is used as a reference, to calculate the relative latency with each other lane. This relative latency is further used to calculate the number of shifts for Barrel Shifter and word shifter.

Abstract: A data storage device may include: a nonvolatile memory device including a memory block; and a controller suitable for controlling the nonvolatile memory device to perform a string read operation on the memory block, and estimating a data storage rate of the memory block based on string read data acquired through the string read operation. When performing the string read operation, the nonvolatile memory device may apply the same read voltage to a plurality of word lines included in the memory block at the same time, acquire the string read data from the memory block according to the read voltage, and transmit the string read data to the controller.

Abstract: A method of operating a nonvolatile memory block includes reading data from physical units in the block and determining individual error rates for data from the physical units. The error rate data is stored. This is repeated over multiple iterations and aggregated stored error rates are used to identify bad physical units in the block.

Abstract: An apparatus detects an error from data transmitted on a transmission path, and measures a first value indicating the number of times the number of errors detected within a first time interval becomes equal to or greater than a first threshold. The apparatus reports that a failure has been detected on the transmission path of the data, when the first value measured within a second time interval longer than the first time interval becomes equal to or greater than a second threshold.

Abstract: Apparatus and method for performing a post-write read in a memory device are disclosed. A memory device may include 3-dimensional memory, with the wordlines in a memory block each having multiple strings. Periodically, the memory device may analyze the wordlines for defects by performing a post-write read on a respective wordline and analyzing the read data to determine whether the respective wordline is defective. Rather than reading all of the strings for the respective wordline, less than all of the strings (such as only one of the strings) for the respective wordline are read. In this way, determining whether the respective wordline in 3-dimensional memory may be performed more quickly.

Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

Abstract: Examples may include techniques to manage multiple sequential write streams to a solid state drive (SSD). Wrap around times for each sequential write stream may be determined. Respective wrap around times for each sequential write stream may be changed for at least some of the sequential write streams to cause the multiple sequential write streams to have matching wrap around times.

Abstract: Rate adaptation is carried out using bit error rate (BER) to enable effective multimedia transmission. The BER can be estimated using signal strength in a MAC layer and modulation information (FIGS. 7-9), and can be compatibly used in different wireless networks by means of message standardization.

Abstract: Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested.

Abstract: A D2D direct communication method is provided. The device sets at least one frame among a plurality of frames included in a superframe to a frame type 0 which is sectionized into a synchronization region for performing a synchronization procedure, a discovery region for discovering devices, a peering region for a connection, and a data region for scheduling of resources and data transmission. The device sets remaining frames among the plurality of frames to a frame type 1 which is sectionized into the synchronization region and the data region.

Abstract: Methods for determining a variable data frequency for recording data on a zone of a magnetic storage disc, each zone including a plurality of tracks and each track including a plurality of sectors, the method includes measuring a signal to noise ratio (S/N) around at least a first track in a first zone; and modulating a data frequency based on the measured S/N around the first track.

Abstract: A data network comprises a master, a network distributor and a plurality of network users. The network distributor is connected to a master data path, a first and a second user data path. A method for transferring data telegrams in this data network includes the reception of a first master data telegram sent by the master through the network distributor, the compilation transfer of a first and a second transmission data telegram through the network distributor, and the reception of a first and a second reception data telegram through the network distributor. Further, the network distributor compiles a second master data telegram and transfers it to the master. In this connection, an access indicator of the second master data telegram represents accesses of the network user to the first master data telegram, the first and second transmission data telegrams as well as the first and second reception data telegrams.

Abstract: A storage controller is configured to find a last-written page in a block in a memory by sending a command to the memory to read a page of data, receiving at least some of the data from that page, and analyzing the at least some of the data from that page to determine if that page is a written page. In one embodiment, the storage controller instructs the memory to read the page of data using a sense time that is shorter than a sense time used to read a page of data in response to a read request from a host controller. Additionally or alternatively, the amount of the data received by the storage controller can be less than the amount of data received when reading a page of data in response to a read request from a host controller.

Abstract: A method of processing a digital broadcasting signal in a transmitter is provided. The method includes performing RS (Reed-Solomon) encoding on signaling data containing cross layer information between a physical layer and a upper layer, interleaving the RS encoded signaling data by writing the RS encoded signaling data row-by-row from left-to-right and top-to-bottom in a signaling data block and outputting the signaling data in the signaling data block by reading data column-by-column from top-to-bottom and left-to-right, and transmitting the digital broadcasting signal including the mobile service data and the interleaved signaling data during slots.

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.

Abstract: The patent application discloses mechanisms that, for a given channel step or edge response, bit interval, and data dependent jitter table can directly determine the minimal eye or bit error rate opening by building a worst case pattern considering the effect of data dependent jitter. These mechanisms can be based on building an indexed table of jitter samples, preparing a structure in the form of connected elements corresponding to the jitter samples, and then applying dynamic programming to determine paths through the connected elements.

Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.

Abstract: In one embodiment, a system includes a hardware processor and logic integrated with and/or executable by the processor or media access control (MAC) functionality of a network port. The logic is configured to negotiate a credit aging duration during initialization of a link between a receiving endpoint and a sending endpoint, the receiving and sending endpoints being connected in a network fabric. The link includes at least one virtual link. The logic is also configured to receive an a Count of available flow credits from the receiving endpoint. The amount of available flow credits are used to determine a capacity to process packets at the receiving endpoint. The exchange of flow credits is performed on a per virtual link basis. Other systems, methods, and computer program products are presented according to more embodiments.

Abstract: Techniques, apparatus and systems are described for an optical line terminal (OLT) operable in a passive optical network (PON) system to isolate and mitigate the behavior of a rogue optical network unit (ONU) that transmits optical power up the optical distribution network (ODN). In one aspect, a method of mitigating the behavior of rogue ONUs can include detecting the presence of a rogue ONU on the PON system, and transmitting, based on the detection, a message addressed exclusively to the ONUs that have not yet been discovered or identified by the OLT.

Abstract: A wireless access point (WAP) including: a station grouping module, a transmit selector, a spatial mapper, an output injector, and an input injector. The station grouping module selects a group of station nodes for concurrent MIMO communications. The transmit selector determines whether all station nodes in the group support a multi-user (MU) protocol. The spatial mapper precodes concurrent transmissions to the group using a precode matrix “Q” which spatially separates the concurrent MIMO transmissions to each station node in the group. The output injector injects preambles for synchronizing timing of the MIMO transmissions at the output of the spatial mapper, responsive to an affirmative determination by the transmit selector. The input injector injects preambles before precoding in the spatial mapper, responsive to a negative determination by the transmit selector; whereby transmission preambles are precoded when at least one station node in the group doesn't support the MU protocol.

Abstract: Systems, methods and/or devices are used to adapt a target charge to equalize bit errors across page types for a storage medium, such as flash memory, in a storage system. In one aspect, the method includes performing a sequence of operations, including: (1) determining a first target charge, a second target charge, and a third target charge, the first, second, and third target charges used for controlling first, second, and third charge distributions, respectively, in cells of the storage medium when data is written to the cells, wherein the second charge distribution is between the first charge distribution and the third charge distribution, (2) determining a first error indicator for lower/fast pages of the storage medium, (3) determining a second error indicator for upper/slow pages of the storage medium, and (4) adjusting the second target charge in accordance with the first error indicator and the second error indicator.

Abstract: The present invention relates to a system and method for providing channel access synchronization in a time division multiple access (TDMA) multi-hop network employing a plurality of time slots defined within a frame structure which repeats. The system and method includes nodes which have local clock variables. The local clock variables generate an expected arrival time of signals from other nodes in the network. Each node then determines whether the local clock variable needs adjusting after receiving a transmission and comparing the expected arrival time with the actual arrival time. Thus, time synchronization across the network is distributed and updated locally at each node. Networks may be merged by casting out nodes in one network and joining those cast out nodes with the other network. Newly joined nodes are thereafter time synchronized into their new network by comparing actual and expected arrival times and updating their clock accordingly.

Abstract: Methods and systems for transferring alarm information by sending an alarm message containing information about an alarm. The alarm message includes an alarm counter indicator that indicates whether an alarm status has changed from a previous alarm message. The alarm message also includes one or more indications of alarm conditions indicating an alarm state or an alarm source. Furthermore, the alarm message includes an alarm length that indicates a number of alarm conditions included in the alarm message.

Abstract: Embodiments include systems and methods for determining link margins of data communications channels in a communications system. For example, an integrated circuit includes a large number of input/output (I/O) channels, each with a respective receiver system. The receiver system can include equalizer subsystems, that attempt to adapt to their respective channels (e.g., to eliminate inter-symbol interference). Embodiments manipulate filter tap weights in the equalizer subsystems to controllably close its respective data eye until a failure region is detected, indicating that a threshold I/O error rate has been exceeded. Thus, for each channel, the filter tap weights can be allowed to fully adjust to identify fully adapted values, and they can be forced into a failure region to identify failure region values. A link margin for each channel can be derived for each channel according to the difference between the fully adapted and failure region values of the filter tap weights.

Abstract: Systems and methods for characterizing networks are disclosed. In several embodiments, a network analyzer applies a network analysis to a network that replaces components of the network in a model of the network with equivalent or bounding models. The network analyzer can then characterize the simplified model of the network and an assessment can be made concerning the accuracy of the characterization of the network.

Abstract: A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Abstract: A method for recording and profiling information of a plurality of aborted transactions from a plurality of transactions is executed by processor core with a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.

Abstract: Data transmission over a wireless connection is improved by determining whether packets include a packet containing an end of a data frame, and if the packets are determined to include such a packet, transmitting the packets together over the wireless connection.

Abstract: A method for controlling a loss of reliability of a non-volatile memory (NVM) included in an integrated circuit card (ICC) may include determining whether the NVM is reliable at the operating system (OS) side of the ICC, and generating an event associated with the reliability of the NVM at the OS side for an application of the ICC, if the NVM is determined to be unreliable.

Abstract: A modular external infusion device that controls the rate a fluid is infused into an individual's body, which includes a first module and a second module. More particularly, the first module may be a pumping module that delivers a fluid, such as a medication, to a patient while the second module may be a programming module that allows a user to select pump flow commands. The second module is removably attachable to the first module.