Abstract: According to one general aspect, an apparatus may include an interconnect bus, an interconnect-to-debug bus interface, and a debug bus. The interconnect bus may be configured to connect and manage combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock. The interconnect-to-debug bus interface may be configured to translate communications between the interconnect bus and the debug bus. The debug bus may include a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock. Each of the plurality of debug wrapper circuits may be configured to: identify if the respective debug wrapper circuit is activated by the debug bus, receive a non-invasive input from a respective combinatorial logic block, and place the non-invasive input from the respective combinatorial logic block on the debug bus.

Abstract: Techniques described and suggested herein include systems and methods for optimizing retrieval, based on localities associated with a requestor and that of various components of a data storage system, of data archives stored on data storage systems using redundancy coding techniques. For example, redundancy coded shards, which may include identity shards that contain unencoded original data of archives, may be configured such that a variable number of the shards can be leveraged to meet performance requirements or time-to-retrieval limitations for retrieval requests associated with the archives stored and/or encoded therein. Under some circumstances, implementing systems may monitor relative geographic locations, among other performance-related metrics, so as to retrieve data such that fewer hosting data storage facilities are used for a given retrieval.

Abstract: Embodiments of the present invention provide systems and methods for dynamically modifying data scrub rates based on RAID analysis. The method includes determining a grouping for an array based on a temperature for the array, a configurable threshold temperature range for the array, and an I/O distribution of the array. The method further includes modifying the data scrub rate for the array based on the grouping.

Abstract: An example system that includes a processor, a memory controller, a memory, and a memory device. The memory controller coupled to the processor. The memory coupled to the memory controller, the memory to store a first copy of data stored according to a first test data pattern for use by a memory scrubbing operation. The memory device coupled to the memory controller. The memory controller may mirror a first set of data stored in a first block of memory of the memory device to a second block of memory of the memory device. The memory controller may also write the first copy of data to the first block of memory as a second copy of data. The memory controller send a first message to the processor indicating a memory fault error for the first block of memory.

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

Abstract: A memory subsystem is operable with a system memory controller. The memory subsystem comprises memory devices mounted on a circuit board, a data module mounted on the circuit board; and a control module mounted on the circuit board to provide address and control signals to the memory devices. The memory subsystem is operable in any of a plurality of modes including a normal mode and a test mode. During the normal mode, the control module provides the address and control signals based on address and control signals from the system memory controller, and the data module enables data paths between the memory devices and the system memory controller. During the test mode, the control module generates the address and control signals, and the data module isolates the memory devices from the system memory controller.

Abstract: The method for validating the status of a memory of a simulator of a cryptographic component able to save data generated by a cryptographic function, includes a step carried out in the simulator including a first execution of a first cryptographic function generating: a first status of the first memory, and a first result of the first command; a step carried out in a test bench including a second execution of a second simplified cryptographic function, with the first and the second functions carrying out the same operations generating: a second status of the memory, and a second result of the second command; a step of validating including comparisons: of the first status and of the second status and of the first result and of the second result.

Abstract: A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.

Abstract: A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

Abstract: A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.

Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

Abstract: Power usage is estimated in a computing environment by automatically detecting hardware configuration information by use of a software agent that is translated into power consumption information for implementing a plurality of power estimation models for efficient power consumption and utilization.

Abstract: A memory system or flash card may include a mechanism for memory cell measurement and analysis that independently measures/predicts memory wear/endurance, data retention (DR), read disturb, and/or remaining margin. These effects may be independently quantified by analyzing the state distributions of the individual voltage levels of the cells. In particular, a histogram of cell voltage distributions of the memory cells can be analyzed to identify signatures for certain effects (e.g. wear, DR, read disturb, margin, etc.). Those measurements may be used for block cycling, data loss prediction, or adjustments to memory parameters. Pre-emptive action at the appropriate time based on the measurements may lead to improved memory management and data management. That action may include calculating the remaining useful life of data stored in memory, cycling blocks, predicting data loss, trade-off or dynamic adjustments of memory parameters.

Abstract: A magnetic memory device includes a memory cell array comprising memory cells including magnetic tunnel junction elements. Each memory cell is electrically connected between a source line and a bit line. A control circuit is configured to perform a screening test on the memory cell array before writing data to the memory cell array. The screening test determines whether an abnormal cell is present in the memory cell array. The controller applies a first writing voltage to the write data to the memory cell array if the abnormal cell is not present, or applies a second writing voltage to write data to the memory cell array if the abnormal cell is present. The second writing voltage is different from the first writing voltage.

Abstract: A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Abstract: A system, a non-transitory computer readable medium and a method for wear estimation of a flash memory device, the method may include: programming information to a first portion of the flash memory device during a test programming process; measuring a duration of the test programming process; and estimating a wear characteristic of the first portion of the flash memory device thereby providing an estimated wear characteristic, wherein the estimating is responsive to the duration of the test programming process.

Abstract: Systems and methods disclosed herein provide for automatically diagnosing mis-compares detected during simulation of Automatic Test Pattern Generation (“ATPG”) generated test patterns. Embodiments of the systems and methods provide for determining the origin of a mis-compare based on an analysis of the generated test patterns with a structural simulator and a behavioral simulator.

Abstract: A memory system is disclosed. The memory system includes: a memory; a first ECC circuit used to encode information bits of a first length into a codeword of a first ECC scheme, and to decode a codeword of the first ECC scheme read from the memory into decoded information bits of the first length; a second ECC circuit used to encode information bits of a second length into a codeword of a second ECC scheme, and to decode a codeword of the second ECC scheme read from the memory into decoded information bits of the second length; and a control circuit used to combine a plurality sets of the decoded information bits of the first length into the information bits of the second length, and to separate the decoded information bits of the second length into a plurality sets of the information bits of the first length.

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

Abstract: A method for operating a data storage device includes obtaining test data from a target region of a memory block by applying a test bias simultaneously to all word lines of the memory block; and estimating a state of the memory block based on the test data.

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

Abstract: Techniques are disclosed relating to capturing information related to instructions executing on in a processor. In one embodiment, an integrated circuit is disclosed that includes an execution pipeline configured to execute a sequence of instructions. The integrated circuit includes monitoring circuitry configured to monitor the execution pipeline for occurrences of an event associated with the sequence of instructions, and in response to detecting a particular number of occurrences of the event, capture a value of a program counter corresponding to an instruction of the sequence of instructions that is associated with an occurrence of the event. The monitoring circuitry stores the captured value of the program counter in a distinct capture register and signals an interrupt indicating that the captured value of the program counter is retrievable from the capture register. In some embodiments, a debugging application may retrieve the value and present it to a developer attempting perform code profiling.

Abstract: A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.

Abstract: An apparatus for performing a scan test of IC chip includes a shift-frequency searching unit that executes first scan test for first scan pattern whole or part of which constituting first scan section and second scan test for second scan pattern whole or part of which constituting second scan section, and searches usable shift frequency for the second scan section. The first scan pattern is scan pattern inputted to scan path right before the second scan pattern. The shift-frequency searching unit shifts the first scan section to the scan path with first shift frequency in the first scan test, shifts the second scan section to the scan path with second shift frequency in the second scan test, and determines, when both results of the first scan test and the second scan test indicate pass, the second shift frequency as the usable shift frequency for the second scan section.

Abstract: A sequence number is assigned to a data storage operation targeted for a persistent data storage device. The sequence number is used to seed a random number generator. A random sequence is obtained from the random number generator, each element of the random sequence being used to generate characteristics of the operation. The data storage operation is fulfilled in accordance with the characteristics, the characteristics being subsequently determinable using the sequence number.

Abstract: Systems and methods for reducing sensing time for sensing data states stored within a plurality of memory cells are described. In some cases, the ramping of a word line connected to the plurality of memory cells may be delayed until a threshold current corresponding with a particular number of erased memory cells of the plurality of memory cells has been met or exceeded. The threshold current may be compared with a summation of a first set of detection currents corresponding with a first set of memory cells of the plurality of memory cells that have been sensed to be in a conducting state while the word line is set to a voltage level for sensing erased memory cells. The threshold current may be set based on a chip temperature and/or a particular number of bit errors that occurred during a prior sensing operation.

Abstract: A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: A memory test system may include a tester and N memory devices, where N is a positive integer greater than 1. The tester may generate test signals. A K-th memory device of the N memory devices includes a plurality of K-th memory banks and a K-th decoder, where K is each positive integer equal to or smaller than N. The K-th memory banks may be configured to operate based on first internal signals and each of the K-th memory banks includes a plurality of unit blocks. The K-th decoder may be configured to convert the test signals corresponding to the first test to the first internal signals based on a K-th conversion relation and update the K-th conversion relation based on a result of the first test with respect to the K-th memory device.

Abstract: Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.

Abstract: A semiconductor memory device and a verification method which can verify data taken inside external terminals are provided. The semiconductor memory device of the invention includes external input/output terminals for inputting or outputting data, a memory array 110 and a page buffer/sensing circuit 170. The page buffer/sensing circuit 170 holds input data inputted from the external input/output terminals and the held input data can be programmed to the memory array 110. Further, the semiconductor memory device includes comparing circuit 132. The comparing circuit 132 compares input data held in the page buffer/sensing circuit 170 and the input data read from the page buffer/sensing circuit 170.

Abstract: A storage system is provided which includes: a storage device including a first memory, which may be nonvolatile memory, and a second memory, which may be a device memory, and configured to request a test on at least one of the first and second memories; and a host configured to test the at least one memory in response to the request for the memory test from the storage device and store the test result in the first memory or a third memory.

Abstract: The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a test mode enable signal and a switch control signal and receives test data. The second semiconductor device generates first internal data and second internal data in response to the test mode enable signal, drives a first pad in response to the first internal data, drives a second pad in response to the second internal data, and drives a third pad in response to the first and second internal data according to the switch control signal.

Abstract: A method for data storage includes storing data in a group of memory cells, by encoding the data using at least an outer code and an inner code, and optionally inverting the encoded data prior to storing the encoded data in the memory cells. The encoded data is read from the memory cells, and inner code decoding is applied to the read encoded data to produce a decoding result. At least part of the read data is conditionally inverted, depending on the decoding result of the inner code.

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

Abstract: Partially-bad blocks are identified in a 3-D block-erasable nonvolatile memory, each partially-bad block having one or more inoperable separately-selectable sets of NAND strings and one or more operable separately-selectable sets of NAND strings. Operable sets of NAND strings within two or more partially-bad blocks are identified and are mapped to form one or more virtual blocks that are individually assigned virtual block addresses. The virtual block address are maintained in a list and used to access the virtual blocks.

Abstract: A first data input circuit receives test data from a first pad to generate first input control data for generating cell input data stored in a memory cell array during a first operation period. A first data output circuit receives first output control data generated from cell output data outputted from the memory cell array to output the first output control data to an internal node coupled to a second pad during a second operation period.

Abstract: Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.

Abstract: Memory optimization of integrated circuit (IC) design using generic memory models is presented. One method includes accessing a register transfer level (RTL) description for the IC design that includes generic memory interface calls to generic memory models for each memory instance. The generic memory call interface includes a set of memory parameters. The method also includes processing the RTL description of the IC design as a step in a design flow for the IC design by processing specific memory models for the memory instances, wherein the specific memory model for each memory instance is generated from the generic memory model using the memory parameters corresponding to the memory instance. The method can also include generating specific memory models (e.g., simulation model, timing model, and layout model) for each memory instance based on a given set of values of memory parameters for the memory instance.

Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract: Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

Abstract: Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.

Abstract: Apparatus, systems, and methods for AES integrity check in memory are described. In one embodiment, a controller comprises logic to receive a write request from a host device to write a line of data to the memory device, determine a first plaintext cyclic redundancy check from the line of data, encrypt the line of data, encrypt the first plaintext CRC with a unique value to generate a first encrypted CRC, and store the encrypted line of data and the first encrypted CRC in memory. Other embodiments are also disclosed and claimed.

Abstract: A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for VT testing for reading at least some memory cells. A second test stage including at least one second stage read uses an adjusted step size less in magnitude than the first step size for reading at least some memory cells. Provided no bit pattern match by the second test stage and/or the adjusted step size does not meet a predetermined minimum resolution (PMR), one or more additional test stages including additional array searching are added using a fixed step size less in magnitude than the adjusted step size including at least one read until a final read determines the predetermined repeating bit pattern is matched and a fixed step size for the final read meets the PMR.

Abstract: A fast and low-power sense amplifier and writing circuit for high-speed Magnetic RAM (MRAM) which provides the long retention times and endurance of magnetic tunnel junction (MTJ) cells, while providing faster access speeds, verified writes, and an increased sensing margin. A high-speed and low-power pre-read and write sense amplifier (PWSA) provide VCMA effect precessional switching of MTJ cells which include pre-read and comparison steps which reduce power consumption. An embodiment of the PWSA circuit is described with write and pre-charge circuit, S and D latches, comparison circuit, and a differential amplifier and control circuit.