Abstract: A semiconductor system includes a slave including a plurality of unit memory regions. The semiconductor system further includes a master configured to perform a training operation by writing test data to the plurality of unit memory regions, reading the written test data, and determining a pass/fail result for the read test data.

Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.

Abstract: An operation method of a memory system including a memory controller and a memory device may include transferring, by the memory controller, a first read command to the memory device; transferring, by the memory device, read data and a part of an error correction code corresponding to the read data to the memory controller in response to the first read command; detecting, by the memory controller, an error of the read data based on the part of the error correction code; transferring, by the memory controller, a second read command to the memory device when the error is detected; transferring, by the memory device, a remainder of the error correction code corresponding to the read data to the memory controller in response to the second read command; and correcting, by the memory controller, the error of the read data based on the remainder of the error correction code.

Abstract: Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.

Abstract: A processing device of a memory device test resource detects that a memory sub-system has engaged with a first memory sub-system interface port and a second memory sub-system interface port of the memory device test resource. The processing device causes a power supply signal to be transmitted from the memory device test resource to the memory sub-system via the first memory sub-system interface port. The processing device identifies a test to be performed for a memory device of the memory sub-system, where the test includes one or more test instructions to be executed in performance of the test. The processing device causes the one or more test instructions to be transmitted from the memory device test resource to the memory sub-system via the second memory sub-system interface port, where the test is performed by the one or more test instructions executing at the memory sub-system.

Abstract: A storage device includes a non-volatile memory including a plurality of memory groups; and a memory controller configured to determine a monitoring group from among the plurality of memory groups, determine a monitoring block from among a plurality of blocks included in the monitoring group, and determine whether the monitoring group is a fail group by monitoring the monitoring block using dummy data prior to failure of the monitoring group.

Abstract: A method may include, during a boot of an information handling system, detecting a soft failure associated with a read request to storage media of the information handling system wherein the soft failure is not visible to an operating system of the information handling system and in response to detecting the soft failure, rewriting a sector of the storage media affected by the soft failure to correct the soft failure.

Abstract: A semiconductor memory apparatus includes a write control circuit suitable for generating a write cancel signal and a rewrite signal in response to a voltage level of a write voltage in a write operation, and a driving circuit suitable for transferring data to a data storage region in response to the write cancel signal and the rewrite signal in the write operation.

Abstract: A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array, performs an ECC operation on read-out data from first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder, adjusts the first address boundary according to a first ECC failure bit number.

Abstract: Devices and techniques for fatal error logging in a memory device are described herein. For example a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a portion of the diagnostic information as payload instead of the user data that would have occupied the payload had the read succeeded. Metadata in the response can be used to communicate an error code.

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: sending a first read command sequence which indicates a reading of a first physical unit by using a first read voltage level to obtain first data; decoding the first data; sending a second read command sequence which indicates a reading of the first physical unit by using a second read voltage level to obtain second data; decoding the second data with assistance information to improve a decoding success rate of the second data if the second read voltage level meets a first condition or the second data meets a second condition; and decoding the second data without the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Abstract: Yield criteria of a material are estimated by obtaining test data representing anisotropic material properties of the material and performing an iterative evolutionary search to identify parameters of a function descriptive of the yield criteria of the material. The evolutionary search includes determining an error value based on a first data point of a first population, where the first data point representing potential values of the parameters. The evolutionary search also includes performing an evolutionary process to generate a second data point as a candidate for replacing the first data point in a second population and determining a second error value based on the second data point. Either the first data point or the second data point is selected for inclusion in the second population. Output data is generated based on estimated values of the parameters that are identified by the evolutionary search.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and an operating method. A command from a host is received and multiple streams corresponding to the command are generated, and the size of super memory blocks is dynamically configured according to the number of multiple streams. Accordingly, the number of currently accessed memory dies can be adjusted according to the number of streams, and the cost for preventing data loss when SPO occurs can be minimized.

Abstract: A parallel test device is provided. The parallel test device of the disclosure includes an I/O pad, a plurality of input buffers, and a plurality of output drivers. The I/O pad is configured to perform input/output operations in the parallel test device. The input buffers are configured to enable write data. The output drivers are configured to enable read data and output the read data to the I/O pad. A test signal corresponds to the data from an external device is transferred to the output drivers through the I/O pad in the parallel test device during a test mode.

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

Abstract: A method of managing a non-volatile memory includes during a data writing process, selecting, by a program triggering the data writing process, an error detection and correction code from among two codes depending on a type of information being written. The information is written into the non-volatile memory, where the information is associated with the selected error detection and correction code.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

Abstract: Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.

Abstract: A failure detection apparatus (10) includes a RAM (125) and a controller (122) configured to execute processing related to detection of a physical quantity in a predetermined sampling period (T1). The RAM (125) includes partitioned areas generated by partitioning the entire area of the RAM (125). The controller (122) is configured to execute sequential failure detection on a portion of the partitioned areas during a time when the controller (122) is not executing the processing in each of the sampling periods (T1).

Abstract: Embodiments relate to a system, program product, and method for expanding the retention capacity of a write cache on a host bus adaptor (HBA) device through the use of non-volatile dual in-line memory modules (NVDIMMs). At least a portion of the existing NVDIMM capacity is leveraged to temporarily retain data that is to be written to persistent storage to reduce the potential for data loss during external electric power disruptions. A NVDIMM HBA Write Cache Module (NHWCM) facilitates the data file traffic transmission and I/O command generation and transmission between a processing device, the HBA device, the NVDIMMs, and the persistent storage.

Abstract: Various embodiments of the invention relate to continuously verifying semiconductor device state integrity. A counter is combined to form part of the Cyclic Redundancy Check (CRC) calculation for control register within the semiconductor device. The counter is initialized to zero and resets after a predetermined number of cycles. The counter value is added to the currently calculated CRC value to get a combined CRC value. Every time a CRC value is calculated for the register bank, the counter value is updated, e.g. incremented. If the CRC calculation is repeated enough times, the counter value will reach its maximum value, and then roll over to its initial value of zero. If no errors occur in the register bank, the combined CRC value at the rolling over point will match an initial combined CRC value. Such a repetitive pattern of the combined CRC value may be used to continuously monitor control register integrity.

Abstract: A method and system for improving data and memory reorganization and storage technology is provided. The method includes configuring data capture and analysis settings of a database system resulting in configured data capture settings. A data and associated memory analysis request is received and specified test code is selected. A specified portion of data and associated memory is selected and the specified analysis code is executed resulting in execution of said specified type of analysis with respect to the specified portion of said data and associated memory. The specified portion of said data and associated memory is modified and stored.

Abstract: A memory correcting method includes steps: providing a memory with a plurality of memory bytes; respectively adding a plurality of correcting bytes to the plurality of memory bytes; providing a plurality of non-volatile compared memory bytes; detecting whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory bytes of the memory to complete the correction. Alternatively, the method respectively provides a plurality of compared memory address bytes for the plurality of memory bytes and for the plurality of correcting bytes for labeling underperforming-bit addresses. Then, the method detects whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory address bytes of the memory to complete the correction.

Abstract: Apparatuses and techniques are described for reliably storing bad column data in a memory device. Units of bad column data and related units of error detection data are stored in non-adjacent groups of memory cells connected to a word line in a ROM block. A unit of bad column data and a related unit of error detection data can be stored in respective groups of memory cells which are relatively far apart from one another along the word line. This helps ensure that a defect in some NAND strings will not affect both the unit of bad column data and a related unit of error detection data. In another aspect, a unit of bad column data and a related unit of error detection data can be stored using different input/output circuits to further increase robustness.

Abstract: A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.

Abstract: A semiconductor device includes a flag generation circuit and a write operation circuit. The flag generation circuit generates an error scrub flag if an error scrub operation is performed. The write operation circuit controls a write operation in response to the error scrub flag. The error scrub operation includes an internal read operation for outputting read data from a cell array, a data correction operation for correcting an error included in the read data to generate corrected data, and an internal write operation for storing the corrected data into the cell array.

Abstract: A data storage system is described that uses wafer-level packaging. In one embodiment an apparatus includes a silicon wafer, a plurality of memory cells formed directly on the wafer, an encapsulant formed over the memory cells, a plurality of wiring connections to connect the memory cells to an external interface, a memory controller, and an external interface.

Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

Abstract: Methods, systems, and devices for a memory error indicator related to high-reliability applications are described. A memory device may perform error detection procedures to monitor trends in the quantity of bit errors as an indication of the health of the memory device. A memory device may perform error detection procedures concurrently with refresh procedures to detect a quantity of errors (e.g., in a memory array) without degrading the performance of the device or the memory array. The memory device may compare a quantity of errors detected (e.g., in the memory array) with one or more previously detected quantities of errors to determine one or more differences in the quantities of errors. The memory device may generate an error metric based on the differences, and may determine whether the error metric satisfies a threshold. The memory device may output a status indicator (e.g., to a host device) based on whether the error metric satisfies the threshold.

Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples.

Abstract: In embodiments, a memory controller (MC) includes an output interface, and an execution engine (EE) to identify, based on field test results of a die coupled to the MC, initial test results of the die using an artificial neural network (ANN) trained to identify the die from a set of NVM dies based on initial test results of the set of NVM dies obtained at a time of manufacture of the set of dies. The initial test results include a first useful life prediction and the field test results include a second useful life prediction, and the initial test results are regenerated by the ANN to protect their confidentiality. In embodiments, the MC is further to compare the second useful life prediction with the first useful life prediction, to determine a deviation between the two, and output, via the output interface, the deviation to a user.

Abstract: Embodiments of the present invention include a memory module that includes a plurality of memory devices and a memory buffer device. The memory devices are characterized as one of a high or low random bit error rate (RBER) memory device. The memory buffer device includes a read data interface to receive data read from a memory address on one of the memory devices, and common error correction logic to detect and correct error conditions in data read from both high RBER and low RBER memory devices. The memory buffer device also includes refresh rate logic configured to adjust a refresh rate based on the detected error conditions.

Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.

Abstract: Systems and methods are disclosed, including determining whether to write dummy data to a first physical page of memory cells of a storage system, such as in response to a detected asynchronous power loss (APL) at the storage system, using a determined number of zeros in the first physical page.

Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

Abstract: A memory system includes a memory device including a plurality of blocks, and a controller suitable for managing the plurality of blocks by grouping the plurality of blocks into a plurality of super blocks in accordance with a predetermined condition, managing normal blocks which are not grouped into the super blocks in a replacement block pool, setting each of the plurality of super blocks that includes at least one bad block to a bad super block, and then changing each bad super block in which the at least one bad block is replaced with a normal block of the replacement block pool using replacement information to a recovery super block, wherein the replacement information includes in a bitmap indicative of whether or not an interleaving operation of each of the recovery super blocks is possible.

Abstract: A display device includes a display panel, a frame memory, a display control circuit that performs a predetermined process on a first video signal using the frame memory and outputs an obtained second video signal, and a panel drive circuit that drives the display panel based on the second video signal. The display control circuit checks whether the frame memory is normal or abnormal, by storing partial video data included in the first video signal, writing to the frame memory, video data obtained by replacing the partial video data with first test data, and comparing with the first test data, second test data included in the video data read from the frame memory.

Abstract: A semiconductor device including a signal generator and decoding and timing skew adjusting circuit is provided. The signal generator is configured to receive n multi-level signals having m signal levels and convert the n multi-level signals into n*(m?1) single level signals having two signal levels. The decoding and timing skew adjusting circuit is configured to receive the single level signals, perform a predefined operation on the single level signals to generate an output signal, and compensate for timing skew between the n multi-level signals, using the single level signals. The n and m are natural numbers, where n>=2 and m>=3.

Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

Abstract: A method includes (a) switching a receiver path network of a front end module to a first matching mode in a receive mode. The method further includes (b) switching a transmitter path network of the front end module to a first resonance mode in the receive mode. The method further includes (c) switching the transmitter path network to a second matching mode in a transmit mode. The method further includes (d) switching the receiver path network to a second resonance mode in the transmit mode.

Abstract: In the present invention, computational efficiency degradation is suppressed when diagnosing a shared storage area in a vehicle control device in which a plurality of computing units are employed. This vehicle control device suppresses computational efficiency degradation by changing an access destination in a storage device while diagnosing a shared storage area that the storage device has.

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.

Abstract: A test interface board includes a first input terminal, a second input terminal, an output terminal, and a transmission line. The first input terminal receives a first test signal for testing a semiconductor device. The second input terminal receives a second test signal for testing the semiconductor device. The output terminal outputs the first test signal and the second test signal to the semiconductor device. The transmission line electrically connects the first input terminal, the second input terminal, and the output terminal such that the first test signal and the second test signal are merged.

Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.

Abstract: Disclosed are a memory management system and a method thereof. Restricted spare cells are optimally distributed (or allocated) into a physical region and a virtual region in a system for repairing a fault of a memory, thereby increasing a yield of a memory chip.

Abstract: In a method for operating a semiconductor memory device including a plurality of memory blocks, the method includes: receiving a read command for a first memory block among the plurality of memory blocks; referring to a block read count value corresponding to the first memory block; determining whether the block read count value has reached a first threshold value; and performing a read operation on the first memory block, based on the determined result.

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a nonvolatile memory including multiple memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The processor is configured to store first data in one or more WLs of a memory block, the first data occupies less than a maximal number of WLs available in the memory block, to calculate redundancy data over the first data and store the redundancy data in a dedicated memory, to program second data to a selected WL of the memory block that was not programmed with the first data, to check a programming status resulting from the programming of the selected WL, and in response to identifying that programming the second data to the selected WL has corrupted at least part of the first data, to recover the first data using the redundancy data.

Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.