Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A device and method for outputting BIOS POST code, applied to a computer system. The device includes a basic input output system (BIOS), a transfer module and a video graphics array (VGA) connector. The BIOS generates a power-on self-test (POST) code using a low pin count (LPC) interface format. The transfer module receives the POST code and transfers the format of the POST code to a system management bus (SMBus) format. The VGA connector receives and outputs the POST code transmitted from the transfer module.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract: A system receives serial messages from a device under test. The system includes a deserializer configured to i) receive the serial messages and, ii) based on the serial messages, form data frames. A frame sync module is configured to form Joint Task Action Group (JTAG) data bits based on the data frames. A plurality of virtual JTAG test access ports are configured to i) receive the JTAG data bits and ii) shift the JTAG data bits between the plurality of virtual JTAG test access ports.

Abstract: An information processing system includes a dynamic random access memory, a processor for information processing in cooperation with the dynamic access memory, and a built-in diagnosis module including a longevity evaluation device, the longevity evaluation device comprising, a timer for measuring an elapsed time after data is entered into a memory device, a read controller for reading the data from the memory device when the elapsed time reaches a predetermined time, and an evaluator for evaluating a longevity of the memory device based on an existence of an error in the data read by the read controller and the elapsed time.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A method implemented to test a plurality of components coupled in a star configuration, each component having a test access port (TAP) controller. The method comprises performing a capture phase of a scan operation on all of the TAP controllers in the star configuration and sequentially selecting one of the TAP controllers at a time to perform a shift state. When all of the TAP controllers have been sequentially selected to perform the shift phase, the method further comprises selecting all of the TAP controllers to perform an update phase.

Abstract: A latch circuit includes a first latch that stores data provided from a data input terminal when a clock is provided from a clock input terminal, and stores scan data provided from a scan data input terminal when a first scan clock is provided from a first scan clock input terminal, a logical circuit that performs a logical operation for a second scan clock provided from the second scan clock input terminal and for an operational mode signal provided from the operation mode input terminal, and generates an update clock and a second latch including an update input terminal connected to an output terminal of the first latch, and an update clock input terminal connected to an output terminal of the logical circuit, the second latch holds the data or the scan data provided from the update input terminal when the update clock is provided.

Abstract: A circuit (12) comprises a first circuit point (13) and a second circuit point (14), which first circuit point (13) and second circuit point (14) are designed to be connected with RF transmission means (11) being designed for receiving in a contact-less manner a carrier signal (CS) from a read/write station and for feeding the circuit (12) with the received carrier signal (CS). The circuit (12) further comprises circuit testing means (4) being designed to carry out functional tests of the circuit (12) and to output a modulated response signal (TS-MOD) via the first and second circuit points (13, 14) only if the functional tests have been successful.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.

Abstract: Some embodiments include apparatus, systems, and methods comprising semiconductor dice arranged in a stack, a number of connections configured to provide communication among the dice, at least a portion of the connections going through at least one of the dice, and a module configured to check for defects in the connections and to repair defects the connections.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: In a non-volatile memory system, test data may be retrieved by means of a circuit without the help of firmware. The circuit is triggered into action when it detects an abnormality in the processor or host interface. In such event, it formats the self test or status signals from the various blocks in the non-volatile memory system controller and sends a test message to the outside world without the assistance of the system processor or interface controller. When implemented in memory systems with multiple data lines, only one of the data lines may be utilized for such purpose, thereby allowing the testing to be performed while the system is still performing data transfer. Preferably, the system includes the test mode communication controller, which can select between a test channel and a host interface channel for the test message transfer so that the same testing may be performed when the memory system is in the test package as well as in an encapsulated package.

Abstract: A resizable cache memory and a system including a Built-In Self Test (BIST) circuit configured to test a cache memory are disclosed. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator identifies a corresponding memory address of a failed location of the cache memory that has been detected by the BIST circuit.

Abstract: A semiconductor integrated circuit includes a self-test circuit, wherein, when a operation mode of the self-test circuit has been switched from a low-speed operation mode to a high-speed operation mode, processing is performed in the high-speed operation mode during a given time period, and the processing result is invalidated based on a control signal.

Abstract: A mechanism is provided for internally controlling and enhancing logic built-in self test in a multiple core microprocessor. The control core may use architectural support for scan and external scan communication (XSCOM) to independently test the other cores while adjusting their frequency and/or voltage. A program loaded onto the control core may adjust the frequency and configure the LBIST to run on each of the cores under test. Once LBIST has completed on a core under test, the control core's program may evaluate the results and decide a next test to run for that core. For isolating failing latch positions, the control core may iteratively configure the LBIST mask and sequence registers on the core under test to determine the location of the failing latch. The control core may control the LBIST stump masks to isolate the failure to a particular latch scan ring and then position within that ring.

Abstract: One Time Programmable (OTP) memory structures and methods for pretesting the support circuitry are provided. A group of dedicated test cells associated with one or more groups of regular OTP cells are used to test the support circuitry for the regular OTP cells. The dedicated cells are programmed and read. The read values are compared to the programmed values or expected values. As a result of the comparison, failing memories may be designated “Not Usable”, while regular OTP cells of passing memories can be programmed for their purpose resulting in elimination of wasted memories during test.

Abstract: The present invention is directed to methods of monitoring logic circuits for failures. In particular, the methods are directed toward establishing parallel logic cores where failures are detected by comparing the parallel paths for equivalence at key locations by a redundancy checker. Any mismatch will result in a predetermined failsafe operational mode. In addition, important techniques are applied to periodically exercise individual parallel paths to ensure that logic cores are verified in a way that does not disturb any process being monitored or controlled. This feature is important in some industries, such as the nuclear power industry, where safety critical operations require a high state of reliability on logic circuit blocks which may be infrequently utilized.

Abstract: Techniques for storing and using compressed restrict values for selected scan chains and flip-flops, such that the states that need to be applied to those flip flops need not be solved by a linear equation system solver, such as a linear equation system solver provided by an automatic test pattern generation (ATPG) tool. Selected restrict values can then be injected into test patterns for those flip-flop combinations that need to be set in a certain shift cycle or those flip-flops that need to be initialized one after another (e.g., for serial settings in one scan chain).

Abstract: Apparatus and methods for effecting bad-block testing operations are disclosed herein. In some embodiments, instead of effecting bad-block testing for the majority of the flash memory blocks of a flash memory device during manufacture, most or all bad-block testing is postponed until the end user is in possession of the flash memory device. In some embodiments, after user data is received by the flash memory device from a host device, one or more blocks of the flash memory device are subjected to bad-block testing.

Abstract: A method and circuit are provided for implementing switching factor reduction in Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides. Switching factor reduction logic is coupled to a Pseudo-Random Pattern Generator (PRPG) providing channel input patterns to a plurality of LBIST channels used for the LBIST diagnostics. The switching factor reduction logic selectively provides controlled channel input patterns for each of the plurality of channels.

Abstract: A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Abstract: A method of functionally verifying a device under test having at least one processor and at least one memory is disclosed. The method includes creating verification data for the device under test using a constrained random verification data creation process executed on the at least one processor. The verification data includes input data and expected output data. The method further includes storing the verification data in the at least one memory. The method further includes processing the input data with the at least one processor to produce actual output data. The method further includes comparing the actual output data to the expected output data. When the actual output data does not equal the expected output data, the method further includes storing at least one inconsistency between the actual output data and the expected output data.

Abstract: A method for allowing high-speed testability of a memory device having a core with memory cells for storing data, comprising: enabling a data signal having a first logical state or a second logical state from the core to reach an output port of the memory device within an evaluate cycle during a functional operating mode and pass an array built in self test during LBIST mode; enabling the data signal to change from the first logical state to the second logical state during LBIST mode at a time that coincides with the latest possible time the data signal from the core can reach the read output port within the evaluate cycle during the functional operating mode and pass the array built in self test; and executing a logic built-in self test configured to test a logic block located downstream of a transmission path of the memory device.

Abstract: A processor having a pipelined test access mechanism (TAM). The processor includes a plurality of processor cores. Each of the processor cores includes a scan chain including plurality of serially-coupled scan elements. The processor further includes the pipelined TAM, which includes a plurality of pipeline stages each corresponding to one of the plurality of processor cores. The pipelined TAM includes a command channel, a scan data input (SDI) channel, a scan data output (SDO) channel, and a compare channel. Each pipeline stage is operable to convey commands to its corresponding processor core via the command channel, to convey scan input data to its corresponding processor core via the SDI channel, to receive scan output data conveyed from the corresponding processor core to the SDO channel and the compare channel, and convey compare data downstream via the compare channel, wherein the compare data is based on the scan output data.

Abstract: A device for monitoring events. The device may have a programmable event engine for detecting events and a memory array coupled to the event engine. The array may store data for programming the event engine to monitor for the events. The device may have an external pin coupled to the event engine. The event engine may monitor a signal on the external pin to detect events external to the device. Alternatively, the device may output a signal on an external pin in response to detecting one of the events.

Abstract: A built-in self test (BiST) system is described. The BiST system includes a circuit-under-test. The BiST system also includes one or more embedded sensors. Each of the embedded sensors includes one or more switches connected to one or more nodes within the circuit-under-test. The BiST system further includes a signal generator. The BiST system also includes a bus interface. The bus interface provides for external access of the BiST system.

Abstract: Disclosed are a method, system and computer program product for determining hardware diagnostics during initial program loading (IPL). A space is allocated for a diagnostics hardware table storing hardware identifications corresponding to hardware to be tested. A hardware monitor function detects new and/or defective hardware. Hardware can be manually selected. A runtime diagnostics detects defective hardware. The hardware identifications corresponding to the new, failing, and/or selected hardware are added to the diagnostics hardware table. The hardware identification to be tested is acquired during the building of a system Hardware Objects Model (HOM). A diagnostics flag is set within HOM according to the diagnostics hardware table. Diagnostics are performed per HOM diagnostics flag indication. The diagnostics table is cleared, and the operating system is run. At system runtime, diagnostics code monitors for runtime error.

Abstract: Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: Testing of combinatorial logic in a programmable device is provided by routing input and/or output test values as signals from and back to dedicated logic through programming circuitry in programmable logic. Some embodiments of the present invention provide for a method for testing functional logic block of an application-specific standard product (ASSP) in a programmable logic device, the method comprising: storing an input value into a register; passing the input value from the register to combinatorial logic; producing an output value from the combinatorial logic; passing the output value from the combinatorial logic to the register; saving the output value in the register; and reading the output value out of the register.

Abstract: An integrated circuit chip includes a mainline function logic path communicatively connected to a first input/output (I/O) pin, a test logic path communicatively connected to the first I/O pin, a latch disposed between the communicative connection between the test logic function path and the first I/O pin, a second I/O pin communicatively connected to the latch, the second I/O pin operative to send a signal operative to change a state of the latch.

Abstract: A method, apparatus and computer program product are provided for implementing diagnostics of transitional scan chain defects using structural Logic Built In Self Test (LBIST) test patterns. A LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a passing operating region and scan data is unloaded. The LBIST test pattern is applied to the device under test and multiple system clock sequences with variable loop control are applied in a failing operating region for the device under test and scan data is unloaded. Then the unload data from the passing operating region and the failing operating region are compared. The identified latches having different results are identified as potential AC defective latches. The identified potential AC defective latches are sent to a Physical Failure Analysis system.

Abstract: The present invention discloses a memory build-in self-test comprising steps of: (a) determining whether there is redundant address in the ROM; (b) when there is redundant address for storing standard check code, transferring the coefficient file in the ROM to a predetermined format; (c) producing a self-test logic and a standard check code corresponding to the ROM via design tool; (d) writing the standard check code into the redundant address and generating a new ROM. The present invention can assure that the standard check code and coefficient can be simply revised via corresponding way of Mask Change, so as to detect the damages of ROM by using memory build-in self-test (MBIST) which does not need to remake a whole set of Mask to revise the standard check code outside the ROM, so as to save cost and time, and lower the difficulty to update the product.

Abstract: A semiconductor circuit for testing a logic circuit, the semiconductor circuit including: an exclusive OR circuit receiving an input testing signal to a circuit under testing and a output testing signal from the circuit under testing; a multiplexer receiving a result signal output from the exclusive OR circuit and a clock signal; and a flip-flop storing a logical value represented by a captured signal in synchronization with a multiplexed signal output from the multiplexer, the captured signal being selected from a entered signal(I) and a data signal that is output from another semiconductor circuit for testing.

Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.

Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Abstract: Various example embodiments are disclosed. According to one example embodiment, an integrated circuit may include a mode block, a plurality of data blocks, and a reset node. The mode block may be configured to output a test mode signal, a scan mode signal, and a trigger signal based on a received data input. The plurality of data blocks may each include registers configured to store data, each of the plurality of data blocks being configured to write over at least some of the data stored in their respective registers in response to receiving a write-over instruction. The reset node may be configured to reset the registers based on receiving either a first reset input or a second reset input. The integrated circuit may be configured to enter a test mode, enter a scan mode, and exit the test mode.

Abstract: An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator performs a test on the integrated circuit. The embedded in-circuit emulator generates a testing result based on the test on the integrated circuit. Trace logic to generate trace data based on the testing result, the trace data being in a parallel format. A serializer is located on the integrated circuit. The serializer converts the parallel format of the trace data into a serial format. The serializer serially outputs the trace data in the serial format from the integrated circuit.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A PBIST architecture is described. A data path circuit is configured for bit-to-associated bit comparisons of expected result data read from a tile with the expected result data read from result memory. The data path circuit is configured to write a first type of failure indication to first failure memory responsive to a data 0 being read from the result memory and a data 1 being read from the tile for a bit-to-associated bit comparison failure. The data path circuit is further configured to write a second type of failure indication to second failure memory responsive to a data 1 being read from the result memory and a data 0 being read from the tile for the bit-to-associated bit comparison.

Abstract: A semiconductor device includes a CPU, a memory, a memory BIST circuit, a first selector that selects and outputs an address and control signal from the memory BIST circuit, when performing a test using the memory BIST circuit, and selects and outputs an address and control signal of the CPU when not performing a test using the memory BIST circuit, a second selector that selects and outputs write data from the memory BIST circuit when performing a test using the memory BIST circuit, and selects and outputs write data of the CPU when not performing a test using the memory BIST circuit, a first flip-flop that samples an output of the first selector (11) and a second flip-flop that samples an output of the second selector. An address and control signal and write data output from the first and second flip-flops are supplied to an address and control terminal and a write data terminal of the memory.

Abstract: A system and method for designing a field programmable gate array (FPGA) with built-in test mechanism includes several enhancements to traditional circular self-test path (CSTP) BIST architecture. The FPGA BIST scheme isolates primary inputs and primary outputs to improve test coverage. Multiple signature output taps are inserted at CSTP registers throughout the test path to help improve signature aliasing probability. Enhanced CSTP register selection algorithms help prevent register adjacency problems and optimize overall resource utilization for implementation. Multiple clock domains are also handled by the FPGA BIST to allow full chip implementation of the FPGA BIST.