Abstract: The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: An array built-in self test (ABIST) system includes a first latch having a first data input, a first scan input and first output and a second latch having a second data input, a second scan input and a second output. The system also includes a first ABIST logic block coupled to the first output that compares a first expected value with a first data value received at the first data input and provided to the first ABIST logic block after a first clock is applied to the first latch. The system also includes a second ABIST logic block coupled to the second output that compares a second expected value with a second data value received at the second data input and provided to the second ABIST logic block after a second clock is applied to the second latch.

Abstract: A test system, comprising: a BIST circuit for generating a first signal; a storage apparatus, for storing the first signal to generate a second signal; a first logic circuit, for generating a third signal; a second logic circuit; a register; and a passby circuit. In a first mode, the BIST circuit transmits the first signal to the storage device, the storage device outputs the second signal to the register for registering, and then the register outputs the registered second signal to the BIST circuit to test the storage apparatus. In a second mode, the first logic circuit transmits a third signal to the register for registering, and then the register outputs the registered third signal to the second logic circuit.

Abstract: A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Abstract: A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.

Abstract: A semiconductor chip having a functional block that performs a communication function includes an input circuit that supplies an oscillating test signal to the functional block, and a test circuit that detects the strength of an oscillating signal which the functional block outputs in response. A strength signal indicating the detected strength is output from the test circuit through an external terminal of the semiconductor chip to a test device. The test device evaluates the strength signal to decide whether an operating characteristic of the functional block is within a specified range. The strength information indicated by the strength signal is not affected by impedance on the signal transmission line between the semiconductor chip and the test device, so the test is not affected by impedance loss.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing.

Abstract: In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

Abstract: A testing system includes a tester probe and a plurality of integrated circuits. Tests are broadcast to the plurality of integrated circuits using carrierless ultra wideband (UWB) radio frequency (RF). All of the plurality of integrated circuits receive, at the same time, test input signals by way of carrierless UWB RF and all of the plurality of integrated circuits run tests and provide results based on the test input signals. Thus, the plurality of integrated circuits are tested simultaneously which significantly reduces test time. Also the tests are not inhibited by physical contact with the integrated circuits.

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract: A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.

Abstract: A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behavior, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine.

Abstract: This invention generates the random seed patterns using simple, low-area overhead digital circuitry on-chip. This circuit is implemented as a finite state machine whose states are the seeds as contrasted to storing the seeds in the prior art. These seeds are used to control pseudo-random pattern generation for built-in self-tests. This invention provides a large reduction in chip area in comparison with storing seeds on-chip or off-chip.

Abstract: A method for self-contained testing within a DRAM comprises the DRAM receiving an instruction from an external processor to test a memory core on the DRAM, and the DRAM self-testing the memory core with one or more BIST pattern stored in a multipurpose register on the DRAM. Optionally, the step of self-testing may include writing the BIST pattern into all locations of the memory core, reading each location of the memory core, and comparing the content read from each location of the memory core with the BIST pattern, wherein a negative comparison indicates a failure has occurred. In a further option, the method may further comprise, after testing the DRAM, initializing the DRAM with an INIT pattern stored in the multipurpose register on the DRAM.

Abstract: A hybrid self-test circuit structure comprises a plurality of input terminals and a plurality of output terminals for testing a plurality of memory units. The circuit structure comprises a first level functional unit for driving a plurality of first output terminals electrically coupled to the first level functional unit to output an output signal according to an external control signal transmitted from the outside; a plurality of second level functional units for receiving the output signal and generating a test signal according to the output signal and outputting the test signal to the memory units; a parallel interface parallelly installed between the first level functional unit and at least one of the second level functional units; and a serial interface serially installed between the first level functional unit and at least one of the second level functional units.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: Provided is a test apparatus for testing a device under test, including: a plurality of test modules that exchange signals with the device under test; a bus to which the plurality of test modules are connected; and a test control section that controls the plurality of test modules via the bus, where each of the plurality of test modules includes: a test section that exchanges signals with the device under test, and a module control section that controls the test section, and the module control section of each test module exchanges signals with the module control section of another test module, via the bus.

Abstract: Provided is a test apparatus and a test method related to the test apparatus for testing a device under test, including: a plurality of test modules that exchange a signal with the device under test; a test control section that outputs a group read instruction for collectively reading data stored in two or more of the test modules; and a control interface section that reads the data from the two or more test modules according to the group read instruction, and collectively sends the read data to the test control section.

Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

Abstract: In one embodiment, a method includes powering on a testing system, whereby a unit present signal is included in the system, the unit present signal communicating to a management complex unit (MCU) that a unit under test (UUT) has been inserted into a corresponding architecture, the signal being sent through a relay such that it can be sent or connected at a later time. The UUT is installed in the system and a programming protocol is initiated. The system is then powered off, whereby the unit present signal is set to open and the system is subsequently powered on. When the UUT is plugged in, the MCU does not see it. The system can include a second relay that allows power being fed to the UUT to be broken such that when the UUT is subsequently powered up, the board is reset and not removed from the architecture.

Abstract: Various embodiments of a test mode signal generating device are disclosed. The device includes first and second test mode signal generating units. The first test mode signal generating unit is configured to receive test address signals to generate a first test mode signal when a first mode conversion signal is enabled. The first test mode signal generating unit is also configured to enable a second mode conversion signal when the test address signals correspond to a first predetermined combination. The second test mode signal generating unit is configured to receive the test address signals to generate a second test mode signal when the second mode conversion signal is enabled. The second test mode signal generating unit is also configured to enable the first mode conversion signal when the test address signals correspond to a second predetermined combination.

Abstract: A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power.

Abstract: A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

Abstract: An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: A stored-pattern logic self-test system includes a memory, a device under test and a test controller. The memory stores test pattern data including test stimuli. The device under test includes a scan chain and a test access port configurable to control operation of the scan chain. The test controller is configured to test the device under test by controlling the memory to output the test stimuli to the device under test. The test controller controls the test access port to load the test stimuli into the scan chain, and receives and evaluates response data from the device under test.

Abstract: A test controller switches the operation of output stages in an integrated circuit between a normal operation mode and a test mode. The output stages are respectively connected to switch elements. A level shifter generates a switch signal for controlling activation and deactivation of the switch elements in accordance with the normal operation mode and the test mode.

Abstract: Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: A System-on-Chip (SoC) may include logic blocks connected to each other and to external connections, and a hardware debug infrastructure logic connected to the logic blocks and for performing functional changes to a design layout of the SoC. The hardware debug infrastructure logic may include software re-configurable modules based upon the logic blocks obtained from substituting a mask programmable ECO base cell configured as a functional logic cell for a logic cell in the design layout.

Abstract: A valid-transmission verifying circuit and a semiconductor device including the same are provided. The valid-transmission verifying circuit provides data to an output circuit in correspondence with reference data, the valid-transmission verifying circuit comprising: a data receiving terminal receiving the reference data; a valid-transmission verifier including a reference load unit configured to sample the reference data, the data sampling operation is interrupted in response to a sampling control signal to determine whether the data sampling operation has been performed within a sampling time; and a selection switch providing the reference data to one of the normal output circuit and the valid-transmission verifier in response to a mode selection signal.

Abstract: In a first embodiment a TAP of IEEE standard 1149.1 is allowed to commandeer control from a WSP of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface. One approach provides for the TAP to maintain access and control of the TAP instruction register, but provides for a selected data register to be accessed and controlled by either the TAP+ATC or by the discrete CaptureDR, UpdateDR, TransferDR, ShiftDR, and ClockDR WSP data register control signals.

Abstract: Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock.

Abstract: A semiconductor integrated circuit includes memories, a BIST circuit, and an analyzer. The BIST circuit includes a test controller performing the test and generating a memory selection signal selecting a memory to be tested, an address generator generating write and read addresses, a data generator generating write data and an expected output value, and a control signal generator generating a control signal. The analyzer includes a memory output selector selecting output data, a bit comparator comparing the output data with the expected output value, an error detection unit determining whether there is an error in the memory, a plurality of pass/fail flag registers capable of storing a pass/fail flag, a repair analyzer analyzing a memory error and generating a repair analysis result, a plurality of repair analysis result registers capable of storing the repair analysis result, and an output unit outputting the pass/fail flag and the repair analysis result.

Abstract: A method executes computerized instructions within an integrated and packaged semiconductor device using a centralized programming interface within the packaged semiconductor device to perform in-system preventive and recovery actions, configure and issue stimulus to chips, components and sensors within the semiconductor device. The method monitors chip, components and sensors within the packaged semiconductor device, using the centralized programming interface, to measure characteristics of the packaged semiconductor device in response to the stimulus. The structure including chips, components and sensors produce outputs representing the characteristics.

Abstract: A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.

Abstract: A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.

Abstract: The disclosed quadrature decoder filtering circuitry for motor control uses one quadrature signal to correct an error in the other quadrature signal, thus allowing a noisy signal due to large dust particles or scratches to be recovered. In some implementations, a system processing for quadrature signals comprises a first circuitry triggered by edges of a first quadrature signal to detect inactivity of a second quadrature signal during consecutive edges of the first quadrature signal. A second circuitry is operable to count the number of consecutive edges of the first quadrature signal during inactivity of the second quadrature signal. A third circuitry is operable to combine transitions of the first quadrature signal with the second quadrature signal during a period of time determined by the count value of the second circuitry.

Abstract: In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.

Abstract: A method and apparatus to improve the efficiency of debugging a processor is provided. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes executing a first test pattern from a plurality of test patterns of a logic built-in self test (LBIST). The method further includes generating a first value based on the first test pattern. The method also further includes comparing the first value to a second value, and terminating the LBIST in response to determining that the first value does not equal the second value.

Abstract: A SRAM (Static Random Access Memory) macro test flop circuit includes a flip-flop circuit, a scan control circuit, and an output buffer circuit. The flip-flop circuit includes a master latch circuit and a slave latch circuit. The master latch circuit includes a master feed-back circuit including a master storage node and a master feed-forward circuit. The slave latch circuit includes a slave feed-back circuit including a slave storage node and a slave feed-forward circuit driven from the master latch. The scan control circuit includes a scan slave feed-forward circuit, a scan latch circuit, and a scan driver circuit driven by the scan feed-back circuit. The scan latch circuit includes a scan feed-back circuit comprising a scan storage node and a scan feed-forward circuit driven from the slave latch. The output buffer circuit includes a master driver driven from master latch circuit and a slave driver driven from slave latch circuit.