Dynamic Data Storage Patents (Class 714/769)
  • Patent number: 10915398
    Abstract: A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code and a second system error correction code based on write data; and a memory including: a memory error correction code generation circuit configured to generate a first memory error correction code based on the write data transferred from the memory controller, and generate a second memory error correction code based on the second system error correction code transferred from the memory controller, and a memory core configured to store the write data, the first system error correction code, the second system error correction code, the first memory error correction code and the second memory error correction code.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Hoiju Chung, Young-Do Hur, Hyuk Lee, Jang-Ryul Kim
  • Patent number: 10901635
    Abstract: The described technology is generally directed towards mapping mapped storage clusters to resources of a real storage cluster in a way that provides high performance. In one aspect, the mapped storage clusters are divided into logical columns, with each logical column corresponding to a mapped node, and having a column height corresponding to a number of storage resources (e.g., disks) managed by that mapped node. The columns are logically positioned within a logical rectangle having dimensions of the real storage cluster. For example, the logical columns can be selected based on column height, and placed in the logical rectangle in a top-down, back and forth pattern. Once logically positioned, the logical columns in the logical rectangle establish the mapping (e.g., embodied in a mapping table) that results in high performance.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: January 26, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Yohannes Altaye
  • Patent number: 10903859
    Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kern, Michael Goessel, Thomas Rabenalt
  • Patent number: 10715182
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, recording a number of flip(s) for each bit of the codeword, generating reliability information for each bit based on the number of flip(s) for each bit respectively, determining to switch to soft decision decoding according to a switching rule and performing a soft decision decoding on the codeword using the reliability information for each bit.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 14, 2020
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Jie Chen, Chung-Li Wang, Zining Wu
  • Patent number: 10644836
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 5, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 10644835
    Abstract: An apparatus includes: a cyclic redundancy check (CRC) encoder configured to receive k information bits and generate p parity bits corresponding to the k information bits, k and p being positive integers; and an interleaver configured to output an interleaved bit sequence, in which the k information bits are interleaved with the p parity bits. The interleaved bit sequence includes a first subset of the k information bits appended with a first parity bit of the p parity bits and a second subset of the k information bits appended with a second parity bit of the p parity bits. The first subset of the k information bits is located earlier than the second subset of the k information bits in the interleaved bit sequence. The second subset of the k information bits and all of preceding information bits in the interleaved bit sequence including the first subset of the k information bits deterministically correlate the second parity bit of the p parity bits.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ahmed A. Abotabl, Jung Hyun Bae
  • Patent number: 10635309
    Abstract: The invention relates to a method for protecting user data of a read/write storage device of an electronic computing system in a motor vehicle. Using test data relating to the run time of the electronic computing system, at least one protection region for protecting a storage region of the read/write storage device is established or removed or is specified in such a manner that the extent and/or position of the protection region with respect to a total storage region comprised by the read/write storage device is changed. The invention further relates to a corresponding electronic computing system.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 28, 2020
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Kai Schade, Andreas Heise
  • Patent number: 10476681
    Abstract: A semiconductor device includes a physical unclonable function (PUF) cell array that includes PUF cells outputting first bits; a non-volatile memory that stores marking bits indicating whether the first bits are valid, first mask bits generated by masking second bits depending on parity of the second bits, and second mask bits generated by masking helper bits of the second bits, the second bits are valid bits from the first bits; an extracting unit that extracts the second bits from the first bits using the marking bits; an unmasking unit that unmasks the second bits using the first mask bits while receiving the second bits to provide the third bits; a bit decoding unit that compresses the third bits to fourth bits while receiving the third bits; and a block decoding unit that generates a security key by decoding the fourth bits and the second mask bits.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: November 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongsoo Kim, Mijung Noh, Bohdan Karpinskyy, Kyoungmoon Ahn, Yong Ki Lee, Yunhyeok Choi
  • Patent number: 10446242
    Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a temperature-based value of a search parameter in response to detecting that an error rate of a codeword read from the memory exceeds a threshold error rate. The controller is further configured to iteratively modify one or more memory access parameters associated with reducing temperature-dependent threshold voltage variation and to re-read the codeword using the modified one or more memory access parameters.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: October 15, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Stella Achtenberg, Eran Sharon, David Rozman, Alon Eyal, Idan Alrod, Dana Lee
  • Patent number: 10348451
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Richardson
  • Patent number: 10241856
    Abstract: A method for memory quarantine comprises: in response to a memory error, determining an extent associated with the memory error, wherein the extent defines an amount of memory comprising a plurality of chunks; traversing, forward from a beginning chunk of the plurality chunks, the plurality of chunks until a first chunk is determined to be corrupt; traversing, in reverse from a last chunk of the plurality of chunks, the plurality of chunks until a second chunk is determine to be corrupt; flagging a subset of the plurality of chunks as quarantined, wherein the subset begins with the first chunk and ends with the second chunk, and wherein quarantine prevents the subset from being reallocated after being released.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: March 26, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Jonathan Giloni, William Habeck, Raunak Rungta, Ravi Thammaiah
  • Patent number: 10169369
    Abstract: A managing unit included in a distributed storage network (DSN) determines resource availability information. The resource availability information includes information indicating a number of memory devices available to be used for storage of encoded data slices. The management unit then chooses dispersal parameters based on the resource availability information. The dispersal parameters are chosen to satisfy a performance threshold associated with storage of the encoded data slices in the DSN, but subject to a constraint requiring a pillar width associated with the encoded data slices to be no larger than the number of memory devices available. The management unit creates a number of storage units, wherein the number of storage units is constrained to be greater than the pillar width, and wherein one or more of the number of memory devices is assigned to each of the number of storage units. The management unit then instantiates a DSN memory that includes the number of storage units.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Trent W. Johnson, Andrew D. Baptist, Ilya Volvovski, John Quigley
  • Patent number: 10134437
    Abstract: According to one embodiment, physical position information on errors on a recording medium is acquired, physical position relationship between the errors on the recording medium is calculated based on the position information, and a failure mode related to the errors is determined based on the position relationship.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: November 20, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takehiko Tsuboi, Kunihiro Shimada, Takashi Endo, Takashi Usui, Toshiaki Ohgushi, Takeichiro Nishikawa, Daiki Kiribuchi
  • Patent number: 9917675
    Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: March 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Shrinivas Kudekar, Thomas Joseph Richardson
  • Patent number: 9899104
    Abstract: A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and a RAID decoder. The RAID decoder includes: a storage, for storing a syndrome of the first codeword, a syndrome of the second codeword, parity data of the first RS codeword and parity data of the second RS codeword; and a first RS decoder and a second RS decoder for storing the first RS codeword and the second RS codeword, respectively, and for performing decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: February 20, 2018
    Assignee: Silicon Motion Inc.
    Inventor: Yu-Luen Wang
  • Patent number: 9876632
    Abstract: There is provided a data transmission/reception system for performing a data communication using interleaving, comprising: a transmission apparatus configured to transmit data in which a synchronization signal including identification data is included; and a reception apparatus configured to extract the synchronization signal from the data received from the transmission apparatus, wherein upon detecting that the extracted synchronization signal is not coincident with any one of a plurality of predetermined code strings, the reception apparatus replaces the extracted synchronization signal with one predetermined code string among the plurality of predetermined code strings, wherein an inter-code word distance between the one predetermined code string and the extracted synchronization signal is the smallest among the calculated inter-code word distances; and the reception apparatus identifies a storage unit for storing the data received from the transmission apparatus based on the identification data included i
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 23, 2018
    Assignee: Ricoh Company, Ltd.
    Inventor: Atsushi Kawata
  • Patent number: 9819365
    Abstract: A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.
    Type: Grant
    Filed: July 19, 2015
    Date of Patent: November 14, 2017
    Assignee: HGST, INC.
    Inventor: Daniel R. Shepard
  • Patent number: 9817712
    Abstract: A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: November 14, 2017
    Assignee: Sony Corporation
    Inventors: Kenichi Nakanishi, Keiichi Tsutsui
  • Patent number: 9710650
    Abstract: A method of detecting a cold-boot attack on an integrated circuit including the steps of: transferring, into a first volatile memory of the integrated circuit, a pattern stored in a non-volatile memory of the circuit; periodically causing a switching down and a switching up of the first volatile memory; and verifying that the number of bits having switched state is within a range of values.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: July 18, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Yannick Teglia
  • Patent number: 9678831
    Abstract: The present invention discloses an error correction method applied to a memory device, wherein the memory device has a plurality of pages. The error correction method includes: sequentially retrieving data of a plurality of first sectors of a first page of the pages in response to a first read command; performing a first error correction by an error correction module during retrieval the data of the first page; producing a second read command when the data of the first sectors of the first page are all retrieved; and starting to sequentially retrieve data of a plurality of second sectors of a second page of the pages in response to the second read command after the data of the first sectors of the first page are all retrieved.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: June 13, 2017
    Assignee: SILICON MOTION, INC.
    Inventors: Tuan-Chieh Wang, Chi-Chih Kuan, Chun-Yu Chen, Mong-Ling Chiao
  • Patent number: 9666225
    Abstract: In one embodiment, a system includes a data processing unit configured to read encoded data from a magnetic tape medium. The data processing unit is also configured to decode a plurality of codeword interleaves (CWIs) from the encoded data, each CWI being a row in a sub data set logically organized into a two-dimensional array. The array includes a predetermined number of rows and columns of predetermined lengths. The data processing unit is also configured to determine an address for a first-written CWI without successfully decoding a corresponding codeword interleave designation (CWID) from the encoded data, each CWID specifying an address for a corresponding CWI. Also, each CWID is calculated as a function of a logical track number and a CWI set number.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 30, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Roy D. Cideciyan, Simeon Furrer, Robert A. Hutchins, Mark A. Lantz, Keisuke Tanaka
  • Patent number: 9667381
    Abstract: A method and an apparatus for encoding and decoding packets using a polar code is provided. The method includes acquiring a plurality of blocks constituting the packet, extracting a plurality of codeword candidates corresponding to the blocks, selecting some of the codeword candidates in a descending order of posterior probability among the codeword candidates corresponding to the blocks, combining the selected codeword candidates into a plurality of codeword combinations, selecting a codeword combination having the highest posterior probability and passed Cyclic Redundancy Check (CRC) test without error among the plurality of codeword combinations, and decoding the selected codeword combination. The packet encoding and decoding apparatus and method of the present disclosure is capable of encoding and decoding packets in a unit of blocks efficiently.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: May 30, 2017
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Research & Business Foundation
    Inventors: Hongsil Jeong, Sang-Hyo Kim, Jong-Hwan Kim, Daehyeon Ryu, Seho Myung
  • Patent number: 9653185
    Abstract: In at least one embodiment, a read operation in a data storage system having lossy storage media includes fetching target data of the read operation from a lossy storage device into a buffer, transferring the target data from the buffer to an external controller external to the lossy storage device via a communication bus, performing error location processing on the target data during the transferring of the target data, communicating error location information regarding at least one error location to error repair logic via the communication bus, the error repair logic repairing the at least one error in the target data using the error location information, and the external controller causing the target data as repaired to be transmitted toward a destination. By deserializing the suboperations comprising the read operation, read latency can be reduced.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 16, 2017
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Evangelos S. Eleftheriou, Charalampos Pozidis, Gary A. Tressler, Andrew D. Walls
  • Patent number: 9582314
    Abstract: Embodiments of the present invention provide a method, system and computer program product for maintaining distributed state consistency in a distributed computing application. In an embodiment of the invention, a method for maintaining distributed state consistency in a distributed computing application can include registering a set of components of a distributed computing application, starting a transaction resulting in changes of state in different ones of the components in the registered set and determining in response to a conclusion of the transaction whether or not an inconsistency of state has arisen amongst the different components in the registered set in consequence of the changes of state in the different ones of the components in the registered set. If an inconsistency has arisen, each of the components in the registered set can be directed to rollback to a previously stored state. Otherwise a committal of state can be directed in each of the components in the registered set.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: February 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Michael Busch, Rajesh M. Desai, Tom William Jacopi, Michael McCandless
  • Patent number: 9557994
    Abstract: A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: January 31, 2017
    Assignee: ARM Limited
    Inventors: Dominic Hugo Symes, Simon Andrew Ford
  • Patent number: 9548762
    Abstract: An adaptation technique for decoding low-density parity-check (LDPC) codes for hard disk drive (HDDs) systems is disclosed. The method includes tuning the normalization factor for LDPC decoding for each data zone and read head during the test stage of manufacturing. The LDPC decoder can be either a sum-product algorithm (SPA) decoder or a Min-Sum decoder. The channel detector can be any soft-output detector, such as a soft-output Viterbit detector (SOVA), a BCJR detector, a pattern-dependent noise-predictive (PDNP) detector, or a bi-directional pattern-dependent noise-predictive (BiPDNP) detector. The adaptation technique can optimize the LDPC decoding performance for each data zone and read head, thereby relaxing the acceptance criteria for hard disk drive read/write heads and disk media, enabling acceptance and use of a much broader range of head and media for hard disk drives.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: January 17, 2017
    Assignee: Agency for Science, Technology and Research
    Inventors: Kui Cai, Yibin Ng
  • Patent number: 9525436
    Abstract: A data detector includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a pruning circuit operable to prune prohibited states from the trellis. The states in the trellis comprise basic states and extended states, where the extended states have a greater number of bits than the basic states.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 20, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Weijun Tan, Bruce A. Wilson, Kelly K. Fitzpatrick, Seongwook Jeong
  • Patent number: 9430324
    Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 30, 2016
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely Tsern
  • Patent number: 9431132
    Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: August 30, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Li-Chun Liang, Kuo-Hsin Lai, Pei-Yu Shih, Tien-Ching Wang
  • Patent number: 9431130
    Abstract: According to one embodiment, a memory controller includes a decoding unit. The decoding unit calculates a syndrome weight in an LDPC code using a codeword read out from a non-volatile memory. The memory controller instructs the non-volatile memory to perform readout using first and second read-out voltages, and determines the first read-out voltage as the optimal read-out voltage in the case where a first syndrome weight based on a read-out result at the first read-out voltage is equal to or less than a second syndrome weight based on a read-out result at the second read-out voltage.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 30, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Sakurada
  • Patent number: 9417957
    Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Rex Kho, Thomas Rabenalt
  • Patent number: 9411740
    Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 9, 2016
    Assignee: SK hynix Inc.
    Inventor: Min-Suk Lee
  • Patent number: 9396063
    Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: July 19, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
  • Patent number: 9336820
    Abstract: A data storage device may be configured with at least one data sector sync mark. Various embodiments are generally directed to a data sector having a sync mark and stored on a data storage medium with the sync mark having either a first or second patterns and a sync circuit configured to distinguish between the two different patterns to identify a status of at least some other portion of the data sector.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: May 10, 2016
    Assignee: Seagate Technology LLC
    Inventor: Bumseok Park
  • Patent number: 9275655
    Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.
    Type: Grant
    Filed: July 13, 2013
    Date of Patent: March 1, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Bruce Wilson, Yang Han, Yu Kou, Rui Cao
  • Patent number: 9262269
    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
    Type: Grant
    Filed: August 26, 2015
    Date of Patent: February 16, 2016
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 9262096
    Abstract: Implementations disclosed herein provide for dynamically mapping logical block addresses (LBA) of unfinished data blocks to unused data blocks during an in-the-field finishing process of a storage medium. Such dynamic mapping creates an impression that the storage medium operates at an advertised capacity before the effective capacity is equal to the advertised capacity.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: February 16, 2016
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Bumseok Park, Gyutaek Kim, Woosik Kim
  • Patent number: 9262261
    Abstract: Memory devices facilitating differing depths of error detection and/or error correction coverage for differing portions of a memory array.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: February 16, 2016
    Assignee: Micron Technology, Inc.
    Inventor: William H. Radke
  • Patent number: 9189324
    Abstract: In a data recording and reproducing apparatus that includes a host computer and a drive in order to improve data reliability, in data recording, the host computer appends a first error correction code to the data and the drive appends a second error correction code to the data. When a failure has occurred in error correction performed by the drive using the second error correction code, the drive reads out the first error correction code and performs error correction using the first error correction code. Since error correction using the first error correction is possible even when error correction using the second error correction code ends in failure, the reliability of data is improved.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: November 17, 2015
    Assignees: Hitachi—LG Data Storage, Inc., Hitachi Consumer Electronics Co., Ltd.
    Inventor: Masayuki Kobayashi
  • Patent number: 9189379
    Abstract: The disclosure is directed to a system for managing data samples utilizing a time division multiplexing controller to allocate time slots for accessing a sample memory according to one or more modes of operation. The time division multiplexing controller is configured to allocate slots for concurrent access by a sample controller, a plurality of detectors, and a noise predictive calibrator when a normal mode is enabled. The time division multiplexing controller is further configured to allocate slots excluding at least one of the sample controller, the plurality of detectors, and the noise predictive calibrator from accessing the sample memory when a retry mode is enabled. In some embodiments, the time division multiplexing controller is further configured to allocate time slots for one or more clients other than the sample controller, the plurality of detectors, and the noise predictive calibrator.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: November 17, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Herjen Wang, Ngok Ying Chu, Johnson Yen, Lei Chen
  • Patent number: 9129654
    Abstract: A system including a first first-in first-out (FIFO) module, a control module, and a second FIFO module. The first FIFO module is configured to receive, from a host, (i) a first block and (ii) a first logical block address corresponding to the first block, where the first block includes first data. The control module is configured to generate a second block, where the second block includes (i) the first data and (ii) the first logical block address. The second FIFO module is configured to receive a third block from the first FIFO module, where the third block includes a second logical block address, and to determine whether the third block is different than the first block depending on whether the second logical block address included in the third block is different than the first logical block address included in the second block.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 8, 2015
    Assignee: Marvell International LTD.
    Inventors: Heng Tang, Gregory Burd, Soichi Isono, Son Hong Ho, Vincent Wong, Zining Wu
  • Patent number: 9124299
    Abstract: A set of branch metrics for a trellis associated with a Viterbi detector is generated. A set of path metrics associated with the trellis is generated based at least in part on the set of branch metrics, including by obtaining a pruned trellis by removing at least some portion of the trellis that is associated with an invalid bit sequence not permitted by a constrained code. A surviving path associated with the pruned trellis is selected based at least in part on the set of path metrics. A sequence of decisions associated with the surviving path is output.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 1, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Jason Bellorado, Marcus Marrow, Zheng Wu
  • Patent number: 9076492
    Abstract: Data processing systems, circuits and methods are disclosed. As one example, a data processing system is disclosed that includes: a buffer circuit, a data processing circuit, and an erasure window set circuit. The buffer circuit is operable to store a data set as a buffered data set, and the data processing circuit is operable to repeatedly apply a data processing algorithm to the buffered data set. The erasure window set circuit is operable to define a location of the erasure window in relation to the buffered data set.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: July 7, 2015
    Assignee: LSI Corporation
    Inventors: Jefferson Singleton, Shaohua Yang
  • Patent number: 9069687
    Abstract: A memory read-channel is provided with selective transmission of error correction data. The disclosed read-channel improves throughput and reduces power consumption when error correction codes are unnecessary. The data read from a memory device comprises user data, error detection data and error correction data. In one embodiment, the error detection data is evaluated to determine if there is a data error; and the error correction data is transmitted only if a data error is detected. In another variation, the error detection data is evaluated during data transmission to determine if there is a data error and the transmission is suspended if a data error is detected. Typically, the error detection data comprises a cyclic redundancy check and the error correction data comprises parity check data.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: June 30, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Nirav P. Dave, Nils Graef, Johnson Yen
  • Patent number: 9065485
    Abstract: An interleaver and method for interleaving are provided, where initialization values are pre-calculated and stored in memory. In one implementation, the method of interleaving includes: calculating in advance an initial value of at least one parameter for use by logic circuitry to initialize interleaving operation; storing the initial value of the at least one parameter as a stored initial value of the at least one parameter; and using the stored initial value of the at least one parameter with the logic circuitry to generate interleaved order positions for the set of data items. In one implementation, the interleaver includes: logic circuitry for generating interleaved order positions for the set of data items and memory coupled to the logic circuitry for holding an initial value of at least one parameter for use by the logic circuitry to initialize interleaving operation.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: June 23, 2015
    Assignee: Altera Corporation
    Inventor: Zhengjun Pan
  • Patent number: 9053748
    Abstract: According to one embodiment, a method for reading data from a medium includes reading a data set from a medium repeatedly using different settings until either: a reconstructed data set is sent to a host and/or stored, or a maximum number of rereads has been reached, after each reading of the data set, storing each row to the reserved data buffer that has no errors or errors in the row are correctable using C1-Error Correction Code (ECC) unless a matching row already exists in the reserved data buffer that has fewer corrected errors therein, assembling the data set from the rows stored in the reserved data buffer to form an assembled data set, correcting any remaining errors in the assembled data set using C2-ECC to form the reconstructed data set, and sending the reconstructed data set to the host and/or storing the reconstructed data set.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Takashi Katagiri, Pamela R. Nylander-Hill
  • Patent number: 9043668
    Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ECC data set are generated and stored in a non-volatile (NV) main memory responsive to a first set of data blocks having a selected logical address. A second data object and an associated second ECC data set are generated responsive to receipt of a second set of data blocks having the selected logical address. The second data object and the second ECC data set are subsequently stored in the in the NV main memory responsive to a mismatch between the first ECC data set and the second ECC data set.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: May 26, 2015
    Assignee: Seagate Technology LLC
    Inventors: Ryan James Goss, Mark Allen Gaertner, Jon D. Trantham
  • Patent number: 9043672
    Abstract: According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: May 26, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Torii, Riki Suzuki, Ryo Yamaki, Naoaki Kokubun, Daisuke Miyashita, Kohei Oikawa
  • Patent number: 9043680
    Abstract: Methods and systems for in-place updating original content stored in a non-volatile storage device and for yielding updated content. Some of the described embodiments illustrate the possibilities for reduction in storage operations, storage blocks, and/or update package size. Some of the described embodiments include the writing of error recovery result(s) such as XOR result(s) which enable the recovery of data in case of an interruption of the update process. In some of the described embodiments, there is re-usage of a protection buffer containing content which is required in the update process.
    Type: Grant
    Filed: January 13, 2008
    Date of Patent: May 26, 2015
    Assignee: RED BEND LTD.
    Inventors: Evyatar Meller, Sharon Peleg
  • Patent number: 9030771
    Abstract: A media drive includes drive side circuitry that, in response to a request to validate compressed data read from media, validates packets of the compressed data while compressed and, in response to detecting end of data on the media without having detected an unrecoverable corrupt one of the packets and without decompressing the compressed data, generates a message indicating that the compressed data read from the media has been validated.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: May 12, 2015
    Assignee: Oracle International Corporation
    Inventor: David G. Hostetter