Abstract: The present disclosure relates to systems, methods, and computer readable media for identifying and responding to a panic condition on a storage system on a computing node. For example, systems disclosed herein may include establishing recovery instructions between a host system and a storage system in responding to a future instance of a panic condition. The storage system may provide an indication of a self-detected panic condition in a variety of ways. In response to identifying the panic condition, the host system may perform one or more recovery actions in accordance with recovery instructions accessible to the host system. This may include performing resets of specific components and reinitializing communication between the host system and storage system in less invasive ways than slower and more expensive conventional approaches for responding to panic conditions on computing nodes.

Abstract: A data processing circuit includes a plurality of transformation blocks suitable for respectively transforming in parallel a plurality of input bit groups into a plurality of output bit groups, wherein each of the transformation blocks transforms a corresponding input bit group into a corresponding output bit group by using a random pattern.

Abstract: Systems, apparatuses, and methods for converting data to a tiling format when implementing convolutional neural networks are disclosed. A system includes at least a memory, a cache, a processor, and a plurality of compute units. The memory stores a first buffer and a second buffer in a linear format, where the first buffer stores convolutional filter data and the second buffer stores image data. The processor converts the first and second buffers from the linear format to third and fourth buffers, respectively, in a tiling format. The plurality of compute units load the tiling-formatted data from the third and fourth buffers in memory to the cache and then perform a convolutional filter operation on the tiling-formatted data. The system generates a classification of a first dataset based on a result of the convolutional filter operation.

Abstract: The present disclosure relates to systems, methods, and computer readable media for identifying and responding to a panic condition on a storage system on a computing node. For example, systems disclosed herein may include establishing recovery instructions between a host system and a storage system in responding to a future instance of a panic condition. The storage system may provide an indication of a self-detected panic condition in a variety of ways. In response to identifying the panic condition, the host system may perform one or more recovery actions in accordance with recovery instructions accessible to the host system. This may include performing resets of specific components and reinitializing communication between the host system and storage system in less invasive ways than slower and more expensive conventional approaches for responding to panic conditions on computing nodes.

Abstract: Effective use of cyclic redundancy check (CRC) signatures is achieved where each sector of a flash management unit (FMU) has a distinct CRC signature. The CRC signatures are XORed together to create a total CRC signature for the FMU. When a host device updates a single sector of the FMU, the CRC signature for the updated single sector can be changed by removing the old CRC signature corresponding to the single sector and replacing the old CRC signature with a new CRC signature corresponding to the updated single sector. The old CRC signature is XORed from the total CRC signature and then the new CRC signature is XORed with the remaining CRC signatures to create a new total CRC signature. In so doing, data integrity is ensured.

Abstract: Disclosed herein are systems and method for performing recovery using a backup image. In one exemplary aspect, a method comprises scanning a plurality of files on one or more storage devices of a computing device. The method may determine a first set of files from the plurality of files that will be used during recovery of the one or more storage devices, and tag a second set of files that will not be used during recovery. The method may copy the second set of files that have been tagged to an external storage device, and may store the first set of files in a backup image for the computing device (excluding the tagged second set of files from the backup image). The method may add, to the backup image, a respective link to each of the tagged second set of files in the external storage device.

Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.

Abstract: Apparatuses and methods of data error check for semiconductor devices are described. An example apparatus includes a plurality of data queue circuits and a CRC combine circuit. The plurality of data queue circuits includes a plurality of CRC calculator circuits. The plurality of CRC calculator circuits includes a CRC calculator circuit. The CRC calculator circuit receives a plurality of data bits and one or more check bits and further provides a plurality of CRC calculation bits. The CRC combine circuit receives the plurality of CRC calculation bits from the plurality of CRC calculator circuits, and further provides a result signal responsive to, at least in part, to the plurality of CRC calculation bits.

Abstract: A bin syncing technique ensures continuous data protection, such as replication and erasure coding, for content driven distribution of data served by storage nodes of a cluster in the event of failure to one or more block services configured to process the data. The cluster maintains information about the block services assigned to host a bin with a copy of the data in a bin assignment table associated with a state. The copies of the data are named, e.g., replica 0 (R0), replica 1 (R1) or replica 2 (R2). In response to failure of one or more block services assigned to host a bin with a replica of the data, an alternate or replacement block service may access the assignments maintained in the bin assignment table, which specify names of the replicas associated with the state.

Abstract: Methods, apparatus, and processor-readable storage media for deleting orphan archived files from a storage array using a time-based decision algorithm are provided herein. An example computer-implemented method includes traversing a database of a local storage system to identify a record associated with a stub file, wherein the record is indicative of a time of a client operation, involving the stub file, on a file system of the local storage system; identifying a particular snapshot in a set of available snapshots of the file system; and providing an indication to a cloud storage platform to delete a cloud object corresponding to the stub file in response to determining that the time of the client operation occurred earlier than a snapshot time associated with the particular snapshot in the set.

Abstract: Methods and systems for use in a dispersed storage network to prioritize data rebuilding operations. In various examples, a device receives data loss information from a set of storage units. Based on the data loss information, data slice errors are detected regarding data stored by the storage units, and corresponding rebuild requests are issued to the storage units. The device also determines a rebuild rate based on a rate of rebuilding associated with the rebuild requests. The device further receives storage error information regarding errors associated with storage requests to the storage units and, based on the data loss information and storage error information, determines a data loss rate. The rebuild rate and the data loss rate are provided to the storage units for use in prioritizing the rebuild requests, such that when the rebuild rate compares unfavorably to the data loss rate, rebuild requests are prioritized over storage requests.

Abstract: Techniques for Implementation of keeping data integrity in multiple dimensions are described. A single but relatively complicated engine is used to encode a line of original data bits in one dimension once and for all, while a linear array of simple engines are used in another dimension to keep revising sets of redundant data bits for successive lines of original data bits, where the redundant data bits become final when a last line of original data bits is accessed.

Abstract: A memory storage device including a memory storage array and a memory controller is provided. The memory storage array is configured to store data. The memory controller is coupled to the memory storage array. The memory controller is configured to write to-be-written data to the memory storage array. The to-be-written data includes a plurality of data bits and a flip bit. The memory controller performs a verification operation on the to-be-written data to determine whether the data bits includes error bits and records information of the error bits. The memory controller, determines, according to a quantity of the error bits, whether to invert parities of the data bits and the flip bit, and records the parity of the flip bit. In addition, a data access method is also provided.

Abstract: A storage unit in a distributed storage network (DSN) transmits resource availability information to a managing unit. The resource availability information includes information indicating a number of available memory devices of the storage unit that are available to be used for storage of encoded data slices. The storage unit receives resource assignment information determined by the managing unit. The resource assignment information includes one or more dispersal parameters, information identifying a set of storage units to be included in a newly instantiated DSN memory, and a DSN address range assigned to the storage unit for use in the newly instantiated DSN memory. The storage unit selects particular available memory devices of the storage unit to assign to the newly instantiated DSN memory. The selection is based on the resource assignment information.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the flash memory module comprises at least one flash memory chip, each flash memory chip comprises a plurality of blocks, each block comprises a plurality of pages, and the method comprises: sending a read command to the flash memory module to ask for data on at least one memory unit; and analyzing state information of a plurality of memory cells of the memory unit based on information from the flash memory module to determine a decoding method adopted by a decoder.

Abstract: In a memory apparatus, a data read-write circuit is configured to access data in a memory cell array. A parity-data read-write circuit is configured to access parity data in a parity memory cell array. A syndrome operation circuit generates an error decoding signal according to the data received from the data read-write circuit and the parity data received from the parity data read-write circuit. During the same read period as reading the data, the data read-write circuit corrects an error bit of the data and outputs the corrected data and a correction bit signal according to the error decoding signal. The syndrome operation circuit further outputs a parity data writing signal to the parity data read-write circuit according to the correction bit signal to update the parity data in the parity memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.

Abstract: A memory system includes a memory controller including: a system error correction code generation circuit configured to generate a first system error correction code and a second system error correction code based on write data; and a memory including: a memory error correction code generation circuit configured to generate a first memory error correction code based on the write data transferred from the memory controller, and generate a second memory error correction code based on the second system error correction code transferred from the memory controller, and a memory core configured to store the write data, the first system error correction code, the second system error correction code, the first memory error correction code and the second memory error correction code.

Abstract: The described technology is generally directed towards mapping mapped storage clusters to resources of a real storage cluster in a way that provides high performance. In one aspect, the mapped storage clusters are divided into logical columns, with each logical column corresponding to a mapped node, and having a column height corresponding to a number of storage resources (e.g., disks) managed by that mapped node. The columns are logically positioned within a logical rectangle having dimensions of the real storage cluster. For example, the logical columns can be selected based on column height, and placed in the logical rectangle in a top-down, back and forth pattern. Once logically positioned, the logical columns in the logical rectangle establish the mapping (e.g., embodied in a mapping table) that results in high performance.

Abstract: A solution is proposed for processing data bits, in which the data bits are transformed into first data bytes by means of a first transformation, in which the first data bytes are stored in a memory, in which second data bytes are read from the memory, in which each of the second data bytes, when there is no error, is a codeword of a block error code and in which one error signal per second data byte is determined that indicates whether or not this second data byte is a codeword.

Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, recording a number of flip(s) for each bit of the codeword, generating reliability information for each bit based on the number of flip(s) for each bit respectively, determining to switch to soft decision decoding according to a switching rule and performing a soft decision decoding on the codeword using the reliability information for each bit.

Abstract: An apparatus includes: a cyclic redundancy check (CRC) encoder configured to receive k information bits and generate p parity bits corresponding to the k information bits, k and p being positive integers; and an interleaver configured to output an interleaved bit sequence, in which the k information bits are interleaved with the p parity bits. The interleaved bit sequence includes a first subset of the k information bits appended with a first parity bit of the p parity bits and a second subset of the k information bits appended with a second parity bit of the p parity bits. The first subset of the k information bits is located earlier than the second subset of the k information bits in the interleaved bit sequence. The second subset of the k information bits and all of preceding information bits in the interleaved bit sequence including the first subset of the k information bits deterministically correlate the second parity bit of the p parity bits.

Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

Abstract: The invention relates to a method for protecting user data of a read/write storage device of an electronic computing system in a motor vehicle. Using test data relating to the run time of the electronic computing system, at least one protection region for protecting a storage region of the read/write storage device is established or removed or is specified in such a manner that the extent and/or position of the protection region with respect to a total storage region comprised by the read/write storage device is changed. The invention further relates to a corresponding electronic computing system.

Abstract: A semiconductor device includes a physical unclonable function (PUF) cell array that includes PUF cells outputting first bits; a non-volatile memory that stores marking bits indicating whether the first bits are valid, first mask bits generated by masking second bits depending on parity of the second bits, and second mask bits generated by masking helper bits of the second bits, the second bits are valid bits from the first bits; an extracting unit that extracts the second bits from the first bits using the marking bits; an unmasking unit that unmasks the second bits using the first mask bits while receiving the second bits to provide the third bits; a bit decoding unit that compresses the third bits to fourth bits while receiving the third bits; and a block decoding unit that generates a security key by decoding the fourth bits and the second mask bits.

Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to determine a temperature-based value of a search parameter in response to detecting that an error rate of a codeword read from the memory exceeds a threshold error rate. The controller is further configured to iteratively modify one or more memory access parameters associated with reducing temperature-dependent threshold voltage variation and to re-read the codeword using the modified one or more memory access parameters.

Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

Abstract: A method for memory quarantine comprises: in response to a memory error, determining an extent associated with the memory error, wherein the extent defines an amount of memory comprising a plurality of chunks; traversing, forward from a beginning chunk of the plurality chunks, the plurality of chunks until a first chunk is determined to be corrupt; traversing, in reverse from a last chunk of the plurality of chunks, the plurality of chunks until a second chunk is determine to be corrupt; flagging a subset of the plurality of chunks as quarantined, wherein the subset begins with the first chunk and ends with the second chunk, and wherein quarantine prevents the subset from being reallocated after being released.

Abstract: A managing unit included in a distributed storage network (DSN) determines resource availability information. The resource availability information includes information indicating a number of memory devices available to be used for storage of encoded data slices. The management unit then chooses dispersal parameters based on the resource availability information. The dispersal parameters are chosen to satisfy a performance threshold associated with storage of the encoded data slices in the DSN, but subject to a constraint requiring a pillar width associated with the encoded data slices to be no larger than the number of memory devices available. The management unit creates a number of storage units, wherein the number of storage units is constrained to be greater than the pillar width, and wherein one or more of the number of memory devices is assigned to each of the number of storage units. The management unit then instantiates a DSN memory that includes the number of storage units.

Abstract: According to one embodiment, physical position information on errors on a recording medium is acquired, physical position relationship between the errors on the recording medium is calculated based on the position information, and a failure mode related to the errors is determined based on the position relationship.

Abstract: Certain aspects of the present disclosure relate to techniques and apparatus for improving decoding latency and performance of Polar codes. An exemplary method generally includes generating a codeword by encoding information bits, using a multi-dimensional interpretation of a polar code of length N, determining, based on one or more criteria, a plurality of locations within the codeword to insert error correction codes generating the error correction codes based on corresponding portions of the information bits, inserting the error correction codes at the determined plurality of locations, and transmitting the codeword. Other aspects, embodiments, and features are also claimed and described.

Abstract: A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and a RAID decoder. The RAID decoder includes: a storage, for storing a syndrome of the first codeword, a syndrome of the second codeword, parity data of the first RS codeword and parity data of the second RS codeword; and a first RS decoder and a second RS decoder for storing the first RS codeword and the second RS codeword, respectively, and for performing decoding on the first RS codeword and the second RS codeword according to the parity data to generate an updated syndrome of the first RS codeword and an updated syndrome of the second RS codeword.

Abstract: There is provided a data transmission/reception system for performing a data communication using interleaving, comprising: a transmission apparatus configured to transmit data in which a synchronization signal including identification data is included; and a reception apparatus configured to extract the synchronization signal from the data received from the transmission apparatus, wherein upon detecting that the extracted synchronization signal is not coincident with any one of a plurality of predetermined code strings, the reception apparatus replaces the extracted synchronization signal with one predetermined code string among the plurality of predetermined code strings, wherein an inter-code word distance between the one predetermined code string and the extracted synchronization signal is the smallest among the calculated inter-code word distances; and the reception apparatus identifies a storage unit for storing the data received from the transmission apparatus based on the identification data included i

Abstract: A storage control apparatus including a first error detection block and a second error detection block is provided. The first error detection block is configured to execute error detection in accordance with a first data unit read from a memory and a first error detection code corresponding to the first data unit. The second error detection block is configured, if a second error detection code corresponding to a second data unit smaller than the first data unit is held in an error detection code hold block different from the memory, to execute error detection in accordance with the second data unit read from the memory and the second error detection code held in the error detection code hold block.

Abstract: A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.

Abstract: A method of detecting a cold-boot attack on an integrated circuit including the steps of: transferring, into a first volatile memory of the integrated circuit, a pattern stored in a non-volatile memory of the circuit; periodically causing a switching down and a switching up of the first volatile memory; and verifying that the number of bits having switched state is within a range of values.

Abstract: The present invention discloses an error correction method applied to a memory device, wherein the memory device has a plurality of pages. The error correction method includes: sequentially retrieving data of a plurality of first sectors of a first page of the pages in response to a first read command; performing a first error correction by an error correction module during retrieval the data of the first page; producing a second read command when the data of the first sectors of the first page are all retrieved; and starting to sequentially retrieve data of a plurality of second sectors of a second page of the pages in response to the second read command after the data of the first sectors of the first page are all retrieved.

Abstract: A method and an apparatus for encoding and decoding packets using a polar code is provided. The method includes acquiring a plurality of blocks constituting the packet, extracting a plurality of codeword candidates corresponding to the blocks, selecting some of the codeword candidates in a descending order of posterior probability among the codeword candidates corresponding to the blocks, combining the selected codeword candidates into a plurality of codeword combinations, selecting a codeword combination having the highest posterior probability and passed Cyclic Redundancy Check (CRC) test without error among the plurality of codeword combinations, and decoding the selected codeword combination. The packet encoding and decoding apparatus and method of the present disclosure is capable of encoding and decoding packets in a unit of blocks efficiently.

Abstract: In one embodiment, a system includes a data processing unit configured to read encoded data from a magnetic tape medium. The data processing unit is also configured to decode a plurality of codeword interleaves (CWIs) from the encoded data, each CWI being a row in a sub data set logically organized into a two-dimensional array. The array includes a predetermined number of rows and columns of predetermined lengths. The data processing unit is also configured to determine an address for a first-written CWI without successfully decoding a corresponding codeword interleave designation (CWID) from the encoded data, each CWID specifying an address for a corresponding CWI. Also, each CWID is calculated as a function of a logical track number and a CWI set number.

Abstract: In at least one embodiment, a read operation in a data storage system having lossy storage media includes fetching target data of the read operation from a lossy storage device into a buffer, transferring the target data from the buffer to an external controller external to the lossy storage device via a communication bus, performing error location processing on the target data during the transferring of the target data, communicating error location information regarding at least one error location to error repair logic via the communication bus, the error repair logic repairing the at least one error in the target data using the error location information, and the external controller causing the target data as repaired to be transmitted toward a destination. By deserializing the suboperations comprising the read operation, read latency can be reduced.

Abstract: Embodiments of the present invention provide a method, system and computer program product for maintaining distributed state consistency in a distributed computing application. In an embodiment of the invention, a method for maintaining distributed state consistency in a distributed computing application can include registering a set of components of a distributed computing application, starting a transaction resulting in changes of state in different ones of the components in the registered set and determining in response to a conclusion of the transaction whether or not an inconsistency of state has arisen amongst the different components in the registered set in consequence of the changes of state in the different ones of the components in the registered set. If an inconsistency has arisen, each of the components in the registered set can be directed to rollback to a previously stored state. Otherwise a committal of state can be directed in each of the components in the registered set.

Abstract: A data processing apparatus and method are provided for performing rearrangement operations. The data processing apparatus has a register data store with a plurality of registers, each register storing a plurality of data elements. Processing circuitry is responsive to control signals to perform processing operations on the data elements.

Abstract: An adaptation technique for decoding low-density parity-check (LDPC) codes for hard disk drive (HDDs) systems is disclosed. The method includes tuning the normalization factor for LDPC decoding for each data zone and read head during the test stage of manufacturing. The LDPC decoder can be either a sum-product algorithm (SPA) decoder or a Min-Sum decoder. The channel detector can be any soft-output detector, such as a soft-output Viterbit detector (SOVA), a BCJR detector, a pattern-dependent noise-predictive (PDNP) detector, or a bi-directional pattern-dependent noise-predictive (BiPDNP) detector. The adaptation technique can optimize the LDPC decoding performance for each data zone and read head, thereby relaxing the acceptance criteria for hard disk drive read/write heads and disk media, enabling acceptance and use of a much broader range of head and media for hard disk drives.

Abstract: A data detector includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a pruning circuit operable to prune prohibited states from the trellis. The states in the trellis comprise basic states and extended states, where the extended states have a greater number of bits than the basic states.

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract: A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command.

Abstract: According to one embodiment, a memory controller includes a decoding unit. The decoding unit calculates a syndrome weight in an LDPC code using a codeword read out from a non-volatile memory. The memory controller instructs the non-volatile memory to perform readout using first and second read-out voltages, and determines the first read-out voltage as the optimal read-out voltage in the case where a first syndrome weight based on a read-out result at the first read-out voltage is equal to or less than a second syndrome weight based on a read-out result at the second read-out voltage.

Abstract: A method of detecting bit errors in a data storage device is provided, which includes comparing a first bit sequence accessed during a read out operation of the data storage device with a second bit sequence that corresponds to an expected memory state of the data storage device.

Abstract: This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.

Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.

Abstract: A data storage device may be configured with at least one data sector sync mark. Various embodiments are generally directed to a data sector having a sync mark and stored on a data storage medium with the sync mark having either a first or second patterns and a sync circuit configured to distinguish between the two different patterns to identify a status of at least some other portion of the data sector.