Disk Array Patents (Class 714/770)
  • Patent number: 10417094
    Abstract: A highly resilient, scalable, high-performance data storage system that stripes its content across peer computers in a data cluster, across data clusters in a cluster group, and across cluster groups in a multi-cluster-group Hyper Storage System. Multiple peers can fail within a data cluster, even beyond the FEC level configured in the cluster, without disrupting the clients. Multiple entire data clusters can fail or be taken out of service without disrupting the clients. Peer failures are detected by the cluster and all missing data is seamlessly regenerated through vertical and/or horizontal resiliency so the great majority of I/O operations complete successfully.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 17, 2019
    Assignee: Peer Fusion, Inc.
    Inventor: Richard S. Levy
  • Patent number: 10133633
    Abstract: A data storage method is used to improve storage consistency of a distributed storage system. The method includes: a primary storage node performs EC coding on a to-be-stored data segment to obtain a target EC stripe; determines in a storage node group to which the primary storage node belongs, m+k target storage nodes used to store m+k target EC blocks of the target EC stripe; sends a preparation message to the target storage nodes; receives a response message sent by a target storage node; and sends an execution message to the target storage nodes to instruct the target storage nodes to write target EC blocks that are in preparation logs.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 20, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Daohui Wang, Feng Zhang, Wei Fan, Zhile Zhang, Yongqiang Zeng
  • Patent number: 9959169
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. A computing device identifies data slices (EDSs) of pillar width (associated with data object) to be stored within a pillar width number of a plurality of storage units (SUs). The computing device the identifies head SUs among the pillar width number of the SUs such that, based on a ring arrangement, each set of EDSs is distributedly stored among the ring arrangement of the pillar width number of the SUs starting with its respective head EDS at a respective head SU and ending with a last tail EDS at a respective last tail SU.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 1, 2018
    Assignee: International Business Machines Corporation
    Inventor: Ethan S. Wozniak
  • Patent number: 9928248
    Abstract: For self-healing in a hash-based deduplication system using a processor device in a computing environment, deduplication digests of data and a corresponding list of the deduplication digests in a table of contents (TOC) are maintained for the self-healing of data that is lost or unreadable. The input data digests are compared to the TOC if directed to data that is lost or unreadable, and the input data digests are used to repair the one of lost and unreadable data.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: March 27, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay H. Akirav, Michael Hirsch
  • Patent number: 9891992
    Abstract: An information processing apparatus can prevent performance deterioration, and maintain fault tolerance, in a storage system having storage nodes of different capacities. The apparatus includes a data writing unit to divide received data into divided data, generate a parity data usable when re-configuring the received data having an error, and write divided data and parity data in storage nodes. The apparatus includes a relocation unit to assign a relocation position of the data based on a predetermined condition and store the data in the assigned storage nodes. The apparatus includes a data reading unit to read the divided data so as not to read parity data stored in the storage nodes by identifying the parity data.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: February 13, 2018
    Assignee: NEC CORPORATION
    Inventor: Hideyuki Takahashi
  • Patent number: 9881696
    Abstract: An operating method of a storage device includes simultaneously buffering first data in a first nonvolatile memory device and a second nonvolatile memory device, simultaneously buffering second data in the second nonvolatile memory device and a third nonvolatile memory device, performing a parity operation on the first data and the second data in the second nonvolatile memory device to generate a parity, and programming the first data, the second data, and the parity into the first nonvolatile memory device, the third nonvolatile memory device, and the second nonvolatile memory device, respectively.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: January 30, 2018
    Assignee: SAMSUNG ELECTRONICS, CO., LTD.
    Inventor: Ju Seok Lee
  • Patent number: 9811415
    Abstract: An application executed on a device reads a portion of a memory during one of an initialization operation and a regular read operation. The application may trigger a preventative read operation during at least one regular read operation. During the preventative read operation the application selects at least one block and at least one page for the preventative read operation. The application determines a cadence for the preventative read operation. The application obtains an error correction code (ECC) status for the portion of the memory, determines if a number of errors associated with the portion is greater than a predefined ECC threshold and performs a correction, responsive to determining that a number of errors associated with the portion is greater than a predefined ECC threshold.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: November 7, 2017
    Assignee: Symbol Technologies, LLC
    Inventors: Shan Chu, James R Fuccello
  • Patent number: 9690659
    Abstract: A parity-layout generating method, includes: creating a first local parity layout with a first calculation range for calculating local parity; creating a second local parity layout with a second calculation range for calculating local parity, a length of the second calculation range being different from a length of the first calculation range; and creating, by a computer, a third local parity layout with the first calculation range and the second calculation range by combining the first local parity layout and the second local parity layout.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 27, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Takeshi Miyamae, Takanori Nakao
  • Patent number: 9529675
    Abstract: A data recovery method, a data recovery device and a distributed storage system are provided, where the method includes: in a case that a distributed storage system loses data of three nodes, recovering data on a target data storage node of the data on the three nodes according to data of a parity node and a data storage node without data loss; and performing degraded recovery on the remaining lost data according to the recovered data of the target data storage node. According to the embodiments of the present invention, a target data storage node first recovered is determined according to the symmetry of lost data, and the lost data of three nodes is recovered according to parity data and data that is not lost, which can improve the data recovery performance of the distributed storage system in a case that the data of three nodes is lost.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: December 27, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaohui Ma, Yaping Sun, Haixiao Chen
  • Patent number: 9471429
    Abstract: A method for disk failure protection, the method may include calculating a first set of parity units by processing a first group of sets of data units that are cached in a cache memory of a storage system; calculating a second set of parity units by processing the first group of sets of data units; wherein the calculating of the second set of parity units is responsive to a first shift that was virtually introduced between each set of data units of the first group of sets of data units; and destaging the first group of sets of data units and the first and second sets of parity units to the first group of disks.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 18, 2016
    Assignee: INFINIDAT LTD.
    Inventor: Yechiel Yochai
  • Patent number: 9454311
    Abstract: A method for dynamically balancing the allocation of data among a plurality of physical data storage devices having a plurality of RAID devices defined thereon, wherein at least one of the plurality of RAID devices is comprised of at least one of a different type of physical storage device or a different number of physical data storage devices than at least one other of the plurality of RAID devices, includes determining a usage factor unique to each RAID device and balancing data I/O based at least in part on the usage factor.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: September 27, 2016
    Assignee: Dell International L.L.C.
    Inventors: Michael J. Klemm, Michael H. Pittelko
  • Patent number: 9407430
    Abstract: An exemplary method is implemented by a radio frequency receiver for synchronizing the recovery of data carried by frames. An indication is generated from error correction of whether the error control coding in the receiver is capable of correcting all the errors induced by the channel within the frame. If the indication declares that all the errors are corrected, then the carrier frequency estimate associated with the error free frame is saved in memory and will be used to initialize the carrier recovery loop at the beginning of the following frames until such frequency estimate is declared unreliable. A new carrier frequency estimate is available at the end of each frame, and if such estimate is proven to be reliable for future use, the current estimate in memory will be overwritten by the new estimate and the freshness of the frequency estimate is extended.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: August 2, 2016
    Assignee: Northrop Grumman Systems Corporation
    Inventor: Mark B. Wong
  • Patent number: 9305618
    Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: April 5, 2016
    Assignee: International Business Machines Corporation
    Inventors: Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
  • Patent number: 9300329
    Abstract: Decoding associated with a second error correction code and a first error correction code is performed. Ns first and second-corrected segments of data, first sets of parity information, and second sets of parity information are intersegment interleaved to obtain intersegment interleaved data, where the Ns segments of data, the Ns first sets of parity information, and the Ns second sets of parity information have had decoding associated with the first and the second error correction code performed on them (Ns is the number of segments interleaved together). Decoding associated with a third error correction code is performed on the intersegment interleaved data and interleaved parity information to obtain at least third-corrected interleaved data. The third-corrected interleaved data is de-interleaved.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 29, 2016
    Assignee: SK hynix memory solutions inc.
    Inventors: Naveen Kumar, Zheng Wu, Jason Bellorado, Lingqi Zeng, Marcus Marrow
  • Patent number: 9262268
    Abstract: An apparatus includes a memory and a controller. The memory includes a plurality of memory devices. Each memory device has a plurality of page types. The plurality of page types are classified based on error rate variations. The controller may be configured to write user data and error-correction data to the memory. The user data and the error-correction data are organized as a super-page. The super-page includes a plurality of sub-pages. The plurality of sub-pages are written across the plurality of memory devices such that the plurality of sub-pages are stored using more than one of the plurality of page types.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: February 16, 2016
    Assignee: Seagate Technology LLC
    Inventors: Yu Cai, Ning Chen, Yunxiang Wu, Erich F. Haratsch, Earl T. Cohen, Timothy L. Canepa
  • Patent number: 9256490
    Abstract: The storage apparatus has a control unit that includes: an identification unit that is configured to determine that a first data element contained in the data is incorrect, when a first restoration calculation first data element, which is restored from the first data element using other data elements of the data excluding the first data element and a new redundancy code obtained from the data by a first calculation method, coincides with a second restoration calculation first data element, which is restored from the first data element using the other data elements and a new redundancy code obtained from the data by a second calculation method; and a restoration unit that is configured to correct the first data element in the storage devices that is determined to be incorrect by the identification unit, to either the first restoration calculation first data element or the second restoration calculation first data element.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: February 9, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Ai Satoyama, Hiroaki Akutsu, Mikio Fukuoka, Eiju Katsuragi
  • Patent number: 9244762
    Abstract: A method and apparatus uses a flexible buffering scheme in an XOR engine to generate checksums, allowing a user to recover data when a disk drive partly or completely fails. An XOR engine may include three or more arithmetic units and three or more local result buffers, which may be used to generate a combination of any of a “P” checksum, a “Q” checksum, and an unmodified copy of the user data, in a single read. The local result buffers and arithmetic units allow the use of multiple Galois field Multiply coefficients so that multiple distinct “Q” checksums may be generated with only one read of the user data.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: January 26, 2016
    Assignee: Marvell International Ltd.
    Inventors: David Geddes, Xinhai Kang
  • Patent number: 9229813
    Abstract: Data storage devices are described with an ECC system that generate additional on-demand ECC information for a previously written track to provide for correction of data errors in the track and thereby avoid having to rewrite the track. Embodiments of the invention address the squeeze-error problem that arises when writing the next (second) track in a sequence causes errors to be introduced in the adjacent previously written (first) track. In alternative embodiments the existence of the data errors in the first track can be detected by reading the track or by estimating the number of likely errors using head position data measured while writing the first and second tracks. The additional on-demand ECC information can be written on any track that is available.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: January 5, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Sridhar Chatradhi, Martin Aureliano Hassner, Kirk Hwang, Satoshi Yamamoto
  • Patent number: 9183127
    Abstract: A region of memory is logically divided into a number of segments, each of which is logically divided into a number of blocks. Blocks are allocated sequentially. A head pointer and a tail pointer demarcate the section of allocated blocks. As allocated blocks are added, the tail pointer is moved so that it remains at the end of the section of allocated blocks. If the tail pointer is within a threshold distance of the head pointer, then the head pointer is moved from its current position to a new position, and the allocated blocks between the current and new positions are freed (deallocated and/or erased). Thus, writes to the memory can be performed sequentially, and blocks can be freed in advance of when they are actually needed.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: November 10, 2015
    Assignee: Symantec Corporation
    Inventors: Dilip Madhusudan Ranade, Niranjan Pendharkar, Anindya Banerjee
  • Patent number: 9176822
    Abstract: A method begins by a processing module receiving a large data file for storage in a dispersed storage network (DSN) and determining initial dispersed storage error encoding parameters. The method continues with the processing module encoding, during a first time interval of receiving the large data file, first data segments of the large data file using the initial dispersed storage error encoding parameters to produce a first plurality of sets of encoded data slices. The method continues with the processing module writing the first plurality of sets of encoded data slices to the DSN and monitoring processing of the writing to produce first write processing performance information. When the first write processing performance information compares unfavorably to a desired write performance range, the method continues with the processing module adjusting, for a second time interval, the initial dispersed storage error encoding parameters to produce adjusted dispersed storage error encoding parameters.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: November 3, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Yogesh Ramesh Vedpathak, Ramin Rouzbeh, Jason K. Resch
  • Patent number: 9170746
    Abstract: In one embodiment, a node is a member of a cluster having a plurality of nodes, where each node is coupled to one or more storage arrays of solid state drives (SSDs) that serve as main storage. The node executed a storage input/output (I/O) stack having a redundant array of independent disks (RAID) layer that organizes the SSDs within the one or more storage arrays as one or more RAID groups. Configuration information is stored as a cluster database. The configuration information identifies (i) one or more RAID groups associated with an extent store, (ii) SSDs within each RAID group, and (iii) an identification of a node that owns the extent store. The cluster database is stored separate and apart from the main storage.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: October 27, 2015
    Assignee: NetApp, Inc.
    Inventors: Rajesh Sundaram, Bharat Baddepudi
  • Patent number: 9170741
    Abstract: An information processing system includes a first information processing apparatus coupled to a first magnetic-disk-device groups including first magnetic disk devices whose motors rotate, a second information processing apparatus coupled to a second magnetic-disk-device group including one or more second magnetic disk devices whose motors rotate and a plurality of third magnetic disk devices whose motors are in a stop state. A management apparatus which included in the system is configured to manage the first and second information processing apparatuses, wherein, when data is to be written, the management apparatus outputs a write request to any of the plurality of first magnetic disk devices and any of the one or more second magnetic disk devices, and when data is to be read, the management apparatus outputs a read request to any of the plurality of first magnetic disk devices.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 27, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yotaro Konishi, Noboru Iwamatsu
  • Patent number: 9153347
    Abstract: The method delivers a storage system for Big Data usage. The system contains a matrix of unreliable physical data devices and data in this reliable big capacity storage system is protected by the triple protection so the method and system can protect storage system from more than 2 fault data devices. In some cases, the system can still deliver data when system has many failed data devices at the same. Floating Parity technology can also avoid heavily writing data to some device surfaces, due to parity update, which cause data device to be failed before expected device life time.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: October 6, 2015
    Inventor: Feiyue Xu
  • Publication number: 20150149869
    Abstract: Physical subsector error marking allows for selectively marking subsectors of a physical sector of a storage medium as unreadable. The error marking may include a bad sector mask to indicate that the subsector is unreadable combined with an error signature to confirm that the bad sector mask was set intentionally. The remaining readable subsectors of the physical sector may be returned to the host.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Seagate Technology LLC
    Inventors: Weihua Lin, Brian Thomas Edgar, Gerald Allen Houlder, Yong Yang, Shuangyi Tang, Vidya Krishnamurthy
  • Patent number: 9043689
    Abstract: A method begins by a processing module obtaining common storage name information regarding data that is stored in storage units of a distributed storage network (DSN) as a set of data slices. Each data slice of the set of data slices has a unique storage name, where each of the unique storage names for the set of data slices has common naming information regarding the data. The method continues where the processing module interprets the common storage name information to determine whether a difference exists between the common naming information of a data slice of the set of data slices and the common naming information of other data slices of the set of data slices. When the difference exists, the method continues where the processing module indicates a potential storage error of the data slice and implements a storage error process regarding the potential storage error of the data slice.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 26, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, John Quigley, Wesley Leggette, Andrew Baptist
  • Publication number: 20150143200
    Abstract: A method of operating a computer memory system with ECC features that will enable operational modes with less electrical power consumption. A chip mark normally used to mark a failing DRAM device may instead be used to mark a non-failing DRAM device before a computer memory system shuts off electrical power to the marked non-failing DRAM device to reduce power consumption, putting the rank of memory that contains the DRAM device in a low power consumption mode. Upon a request from the computer memory system, the chip mark may be removed from the marked non-failing DRAM device in order to return the non-failing DRAM device to normal operation.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Marc A. Gollub, Joab D. Henderson
  • Patent number: 9032271
    Abstract: In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yongke Sun, Dengtao Zhao, Jui-Yao Yang
  • Patent number: 9026891
    Abstract: A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: LSI Corporation
    Inventors: Scott M. Dziak, Jeffrey P. Grundvig, Jason D. Byrne
  • Patent number: 9021339
    Abstract: A data storage system configured to implement a data reliability scheme is disclosed. In one embodiment, a data storage system controller detects uncorrectable errors using intra page parity when data units are read from a set of pages. When an uncorrectable error is detected, the data storage system controller attempts to recover user data using inter page parity without using all data from each page of the set of pages. Recovery of user data can thereby be performed without reading all data from each page. As a result, the amount of time needed to read data can be reduced in some cases and overall data storage system performance can be increased.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 28, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, Inc.
    Inventors: Guangming Lu, Leader Ho, Radoslav Danilak, Rodney N. Mullendore, Justin Jones, Andrew J. Tomlin
  • Patent number: 9021335
    Abstract: Some aspects of the disclosure relate to a data storage system that includes multiple memory device storage devices. If a memory device of a memory device array fails within a first data storage device, some portions of the lost or corrupted data from the failed memory device are recovered by reading them from a second data storage device. Other portions of the lost or corrupted data from the failed memory device are recovered from parity information in the first data storage device.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: April 28, 2015
    Assignee: NetApp, Inc.
    Inventor: Atul Goel
  • Publication number: 20150089328
    Abstract: System and method embodiments are provided for managing storage systems. In an embodiment, a storage system includes an over-provisioned redundant array of independent disks (RAID); and a flexible erasure coding controller coupled to the RAID, the controller comprising a flexible exclusive-or engine configured to provide erasure coding for the over-provisioned RAID using M-parity convolution codes.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 26, 2015
    Inventors: Xiaobing Lee, Chunlei Dong, Yong Chen, Jinshui Liu
  • Patent number: 8990665
    Abstract: A flash memory controller, a computer readable medium and a method. The method may include performing, by a flash memory controller, multiple read attempts of a group of flash memory cells, using multiple read thresholds, to provide multiple read results; determining, by the flash memory controller and based upon the multiple read results, a reliability metric of each of the multiple read results; and error correction decoding the multiple read results based upon reliability metrics associated with the multiple read results.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Densbits Technologies Ltd.
    Inventors: Avi Steiner, Hanan Weingarten, Erez Sabbag
  • Patent number: 8984371
    Abstract: A method begins, as data objects are ingested, by determining, for each of some of the data objects, a priority indicator to produce a listing of priority indicators. The method continues for a data object by determining encoding parameters based on a corresponding priority indicator. The method continues by encoding the data object in accordance with the encoding parameters to produce a plurality of sets of encoded data slices and storing them. The method continues by identifying a first data object for analysis based on a corresponding priority indicator and an analysis priority. The method continues by decoding a plurality of sets of encoded data slices to recover the first data object and analyzing it in accordance with analysis criteria to determine its relevancy. The method continues by issuing a command to delete the plurality of sets of encoded data slices when the relevancy is below a threshold.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: March 17, 2015
    Assignee: Cleversafe, Inc.
    Inventors: S. Christopher Gladwin, Thomas Franklin Shirley, Jr., Jason K. Resch
  • Patent number: 8977931
    Abstract: A method begins by a DS processing module generating a plurality of encoded slices from a data segment using an error encoding function. The method continues with the DS processing module identifying a plurality of DS storage units for storing the plurality of encoded slices. The method continues with the DS processing module selecting an encoded slice of the plurality of encoded slices for sub-slicing using a sub-slicing encoding function to produce a selected encoded slice. The method continues with the DS processing module outputting the plurality of encoded slices to the plurality of DS storage units. The method continues with the DS processing module outputting a command to a DS storage unit of the plurality of DS storage units corresponding to the selected encoded slice, wherein the command includes an instruction to sub-slice the selected encoded slice.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 10, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8966341
    Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 24, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
  • Patent number: 8965939
    Abstract: A method begins, in accordance with a segmentation approach, dividing large data to be stored into regions and dividing a region into segments. The method continues by generating preliminary DSN storage information for one or more regions. The method continues by identifying other large data stored in the DSN that has a relationship with the large data to be stored in the DSN and retrieving DSN storage information for the other large data. The method continues by comparing, at a region level, the preliminary DSN storage information with the retrieved DSN storage information. When a region of the large data to be stored has substantially similar DSN storage information as a region of the other large data, the method continues by utilizing the DSN storage information for the region of the other large data for the DSN storage information of the region of the large data.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Wesley Leggette, Jason K. Resch
  • Patent number: 8949312
    Abstract: An embodiment generally relates to a method of updating clients from a server. The method includes maintaining a master copy of a software on a server and capturing changes to the master copy of the software on an update disk image, where the changes are contained in at least one chunk. The method also includes merging the update disk image with one of two client disk images of the client copy of the software.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: February 3, 2015
    Assignee: Red Hat, Inc.
    Inventors: Mark McLoughlin, William Nottingham, Timothy Burke
  • Patent number: 8949695
    Abstract: A method begins by a DS processing module generating a plurality of encoded slices from a data segment using an error encoding function. The method continues with the DS processing module identifying a plurality of DS storage units for storing the plurality of encoded slices. The method continues with the DS processing module selecting an encoded slice of the plurality of encoded slices for sub-slicing using a sub-slicing encoding function to produce a selected encoded slice. The method continues with the DS processing module outputting the plurality of encoded slices to the plurality of DS storage units. The method continues with the DS processing module outputting a command to a DS storage unit of the plurality of DS storage units corresponding to the selected encoded slice, wherein the command includes an instruction to sub-slice the selected encoded slice.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: February 3, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8935593
    Abstract: A method and apparatus uses a flexible buffering scheme in an XOR engine to generate checksums, allowing a user to recover data when a disk drive partly or completely fails. An XOR engine may include three or more arithmetic units and three or more local result buffers, which may be used to generate a combination of any of a “P” checksum, a “Q” checksum, and an unmodified copy of the user data, in a single read. The local result buffers and arithmetic units allow the use of multiple Galois field Multiply coefficients so that multiple distinct “Q” checksums may be generated with only one read of the user data.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Marvell International Ltd.
    Inventors: David Geddes, Xinhai Kang
  • Patent number: 8930780
    Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 6, 2015
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Bruce A. Wilson
  • Publication number: 20140380128
    Abstract: A method begins by a processing module determining to change storage format from a redundant array of independent disks (RAID) format to a dispersed storage network (DSN) format. The method continues with the processing module retrieving the data from a RAID memory that is stored in the RAID format to produce retrieved RAID data. The method continues with the processing module converting stripe-block data of the retrieved RAID data into a plurality of sets of encoded data slices and reprovisioning the RAID memory for storing DSN formatted data to produce reprovisioned memory. The method continues with the processing module outputting the plurality of sets of encoded data slices to at least one of the RAID memory and a DSN memory for storage therein.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Andrew Baptist, Gary W. Grube, Timothy W. Markison, Jason K. Resch
  • Publication number: 20140380127
    Abstract: Data is obtained at a data storage system. Codewords are generated from the obtained data. The codewords are computed using a folded code and each codeword comprises symbols. The codewords are stored on an array of disks associated with the data storage system in accordance with a codeword symbol mapping that is specified by at least one parameter of the folded code used to generate each codeword.
    Type: Application
    Filed: January 29, 2014
    Publication date: December 25, 2014
    Applicant: EMC CORPORATION
    Inventors: Alexander N. Alexeev, Peter V. Trifonov
  • Patent number: 8918701
    Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr?1 erasures in any one of the remaining r?1 rows, up to tr?2 erasures in any one of the remaining r?2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
  • Patent number: 8914706
    Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: December 16, 2014
    Assignee: Streamscale, Inc.
    Inventor: Michael H. Anderson
  • Patent number: 8910031
    Abstract: A block CRC based fast data hash provides efficient data integrity verification functions. A hash word is generated from block CRCs that are stored along with data blocks in a hard drive for each data and/or parity track of a storage system, such as a RAID array. Each storage system member writes the hash word into a global memory. Thereafter, a director verifies data integrity using all member's hash words with one or more XOR operations. Use of the hash words for data integrity verification saves system bandwidth and CPU processing resources.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 9, 2014
    Assignee: EMC Corporation
    Inventors: ZhiGang Liu, Dale Elliott, Stephen Richard Ives, Shen Liu, Andrew Chanler
  • Patent number: 8910022
    Abstract: A computing device includes a central processing unit (CPU) and a memory system module. The CPU includes a data dispersed storage error coding (DSEC) module operable to DSEC decode a set of encoded ingress data slices to recapture ingress data and DSEC encode egress data to produce a set of encoded egress data slices, an instruction DSEC module operable to DSEC decode a set of encoded instruction slices to recapture an instruction, and an arithmetic logic unit (ALU) operable to, execute the instruction on the ingress data and execute the instruction to produce the egress data. The memory system module is operable to coordinate retrieval of the set of encoded ingress data slices from memory, coordinate retrieval of the set of encoded instruction slices from the memory, and coordinate storage of the set of encoded egress data slices in the memory.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: December 9, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
  • Patent number: 8880981
    Abstract: A data access request is received specifying a data block stored in a stripe of a parity group that includes a plurality of data storage devices to store data blocks and a parity storage device to store parity information for the data. The stripe includes a data block from each of the plurality of data storage devices and the stripe includes a parity block from the parity storage device. An error is detected in the data block specified by the data access request. The error is identified as a lost write error for the data block or a lost write error for the parity block. Identifying the error includes comparing a first storage device signature stored in a metadata field associated with the data block to a second storage device signature stored in a label block identifying a data storage device where the data block is stored.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 4, 2014
    Assignee: NetApp, Inc.
    Inventors: Tomislav Grcanac, Atul Goel, Jagadish Vasudeva, Gururaj Mj
  • Patent number: 8874995
    Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
  • Patent number: 8869006
    Abstract: Embodiments of the invention relate to correcting erasures in a storage array. A read stripe is received from a plurality of n storage devices. The read stripe includes an array of entries arranged in m rows and n columns with each column corresponding to one of the storage devices. The entries include data entries and mr+s parity entries. Each row contains at least r parity entries generated from the data entries according to a partial maximum distance separable (PMDS) code. It is determined that the read stripe includes at least one erased entry, at most mr+s erased entries and that no row has more than r+s erased entries. The erased entries are reconstructed from the non-erased entries, resulting in a recovered read stripe.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business machines Corporation
    Inventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
  • Patent number: 8856620
    Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson