Disk Array Patents (Class 714/770)
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Patent number: 8726127Abstract: A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.Type: GrantFiled: January 10, 2012Date of Patent: May 13, 2014Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
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Publication number: 20140129905Abstract: Various embodiments of the present inventions provide systems and methods for data processing with a flexible LDPC seed.Type: ApplicationFiled: November 6, 2012Publication date: May 8, 2014Applicant: LSI CORPORATIONInventors: Lei Chen, Shaohua Yang, Johnson Yen
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Patent number: 8719668Abstract: Provided in one embodiment is a nonvolatile storage system having multiple nonvolatile storage media and a controller coupled to the multiple nonvolatile storage media. The controller has a storage area configured to store management information including probability management information denoting error probability information of a unit physical area in a nonvolatile storage medium, and an error correcting circuit configured to carry out coding and decoding by a low density parity check code. The controller, in a data read process, is configured to identify based on management information an error probability, uses the identified error probability to correct the read data using the error correcting circuit.Type: GrantFiled: November 1, 2011Date of Patent: May 6, 2014Assignee: Hitachi, Ltd.Inventors: Akiyoshi Hashimoto, Akifumi Suzuki, Takashi Tsunehiro
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Patent number: 8719667Abstract: The invention proposes a method and device for adding redundancy data in a distributed data storage system. Among others, the invention allows to keep impact on network resources low through the use of coordinated regenerating codes according to the invention.Type: GrantFiled: June 30, 2011Date of Patent: May 6, 2014Assignee: Thomson LicensingInventors: Nicolas Le Scouarnec, Gilles Straub
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Patent number: 8713405Abstract: Allocation process that allows erasure coded data to be stored on any of a plurality of disk drives, in a pool of drives, so that the allocation is not tied to a fixed group of drives. Still further, the encoded data can be generated by any of multiple different erasure coding algorithms, where again storage of the encoded data is not restricted to a single group of drives based on the erasure algorithm being utilized to encode the data. In another embodiment, the encoded data can be “stacked” (aligned) on select drives to reduce the number of head seeks required to access the data. As a result of these improvements, the system can dynamically determine which one of multiple erasure coding algorithms to utilize for a given incoming data block, without being tied to one particular algorithm and one particular group of storage devices as in the prior art.Type: GrantFiled: November 22, 2011Date of Patent: April 29, 2014Assignee: SimpliVity CorporationInventors: Michael W. Healey, Jr., David Cordella, Arthur J. Beaverson, Steven Bagby
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Publication number: 20140115426Abstract: Examples are disclosed for facilitating recovery from failures associated with a storage array having a plurality of storage devices.Type: ApplicationFiled: January 2, 2014Publication date: April 24, 2014Applicant: Empire Technology Development LLCInventors: Junwei CAO, Xiao LIN
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Patent number: 8700975Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.Type: GrantFiled: March 15, 2013Date of Patent: April 15, 2014Assignee: Hitachi, Ltd.Inventor: Tomohiro Yoshihara
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Publication number: 20140101518Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: International Business Machines CorporationInventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
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Patent number: 8694849Abstract: A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one or both of the error correction code units form an error correction code for correcting data bit errors in the data unit. Because the memory page containing the data unit does not have a storage capacity for simultaneously storing the error correction code and the data unit, the data storage device is capable of correcting a greater number of data bit errors in the data unit by using the error correction code in comparison to using an error correction code that would fit in the memory page.Type: GrantFiled: December 19, 2011Date of Patent: April 8, 2014Assignee: PMC-Sierra US, Inc.Inventors: Rino Micheloni, Alessia Marelli, Peter Z. Onufryk
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Patent number: 8694866Abstract: MDS (maximum distance separable) array codes are widely used in storage systems to protect data against erasures. The rebuilding ratio problem is addressed and efficient parity codes are proposed. A controller as disclosed is configured for receiving configuration data at the controller that indicates operating features of the array and determining a parity code for operation of the array according to a permutation, wherein the configuration data specifies the array as comprising nodes defined by A=(ai,j) with size rm×k for some integers k,m, and wherein for T={v0 , . . . , Vk-1} ?Zrm a subset of vectors of size k, where for each v=(v1, . . . , vm)?T, gcd (v1, . . . , vm, r), where gcd is the greatest common divisor, such that for any l, 0?l?r?1, and v ?T, the code values are determined by the permutation fvl:[0,rm?1]?[0,rm?1]by fvl(x)=x+lv.Type: GrantFiled: March 15, 2012Date of Patent: April 8, 2014Assignee: California Institute of TechnologyInventors: Itzhak Tamo, Zhiying Wang, Jehoshua Bruck
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Patent number: 8694865Abstract: A method is provided for performing a write operation in a data storage device comprising a storage medium, a processing unit, and a buffer memory storing data to be transferred to the storage medium under control of the processing unit. The method comprises aggregating data in the buffer memory as a strip group comprising multiple data strips, transferring data strips in at least one strip group to the storage medium, calculating a parity strip based on the transferred data strips of the at least one strip group without additional access to the buffer memory, and transferring the parity strip to the storage medium.Type: GrantFiled: November 21, 2011Date of Patent: April 8, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung Hoon Baek, Won Moon Cheon
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Patent number: 8683296Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.Type: GrantFiled: December 30, 2011Date of Patent: March 25, 2014Assignee: Streamscale, Inc.Inventors: Michael H. Anderson, Sarah Mann
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Publication number: 20140068381Abstract: The present inventions are related to systems and methods for irregular decoding of regular codes in an LDPC decoder, and in particular to allocating decoding resources based in part on data quality.Type: ApplicationFiled: September 4, 2012Publication date: March 6, 2014Inventor: Fan Zhang
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Patent number: 8667371Abstract: A centralized DVR includes a dispersed storage error encoding module, storage nodes, and a distribution module. The dispersed storage error encoding module encodes a broadcast of data in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices, which is stored in the storage nodes. For a first playback request, the distribution module determines a first unique combination and retrieves, as a first unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the first unique combination. For a second playback request, the distribution module determines a second unique combination and retrieves, as a second unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the second unique combination.Type: GrantFiled: April 25, 2013Date of Patent: March 4, 2014Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison
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Publication number: 20140040703Abstract: A method begins with a processing module receiving an access request for the data object. The method continues by ascertaining that the data object is divided into a plurality of data segments and that plurality of data segments are dispersed storage error encoded to produce a plurality of sets of encoded data slices. The method continues by ascertaining batching of the plurality of sets of encoded data slices, wherein the plurality of sets of encoded data slices are arranged into a set of batched encoded data slices. The method continues by outputting a set of access requests for the set of batched encoded data slices to storage units of the DSN.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: CLEVERSAFE, INC.Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
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Patent number: 8645798Abstract: The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture.Type: GrantFiled: January 22, 2013Date of Patent: February 4, 2014Assignee: Marvell World Trade Ltd.Inventor: Arvind Pruthi
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Patent number: 8645799Abstract: A random permutation code is described which provides efficient repair of data nodes. A specific implementation of a permutation code is also described, followed by description of a MISER-Permutation code. Finally, an optimal repair strategy is explained that involves an iterative process of downloading the most effective available parity data, updating costs of remaining parity data, and repeating until the data is recovered.Type: GrantFiled: December 31, 2010Date of Patent: February 4, 2014Assignee: Microsoft CorporationInventors: Jin Li, Viveck Cadambe, Cheng Huang
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Publication number: 20140026017Abstract: A method begins by a dispersed storage (DS) processing module determining that a plurality of sets of encoded data slices is to be stored in a set of storage units of a dispersed storage network (DSN) and identifying one or more devices of the DSN that will potentially issue a read request for at least some sets of encoded data slices. The method continues with the (DS) processing module determining transmission times between the one or more devices and the set of storage units and determining a storage strategy for storing the plurality of sets of encoded data slices in the set of storage units based on the transmission times and memory devices of the set of storage units such that, from set to set of encoded data slices, at least a threshold number of encoded data slices are retrievable with comparable read response times.Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: CLEVERSAFE, INC.Inventors: Gary W. Grube, Timothy W. Markison
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Publication number: 20140013186Abstract: A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request.Type: ApplicationFiled: September 9, 2013Publication date: January 9, 2014Applicant: CLEVERSAFE, INC.Inventors: Gary W. Grube, Timothy W. Markison
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Patent number: 8627178Abstract: A method begins with a processing module determining that storage of data requires updating, wherein the data is stored as a plurality of sets of encoded data slices in DSN memory. For a first type of updating, the processing module increases the total number while maintaining the decode threshold number. The processing module then, for each set of encoded data slices, creates another encoded data slice in accordance with the dispersed storage error encoding function and the increased total number and sends the new encoded data slices to the DSN memory. For a second type of updating, the processing module increases the total number and the decode threshold number. The processing module then recovers the data and encodes it in accordance with the dispersed storage error encoding function using the increased total number and the increased decode threshold number to produce an updated plurality of sets of encoded data slices.Type: GrantFiled: July 19, 2013Date of Patent: January 7, 2014Assignee: Cleversafe, Inc.Inventors: Bart Clifone, Jason K. Resch, S. Christopher Gladwin
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Patent number: 8627177Abstract: A method begins with a processing module determining a retrieval threshold for retrieving a set of encoded data slices from a dispersed storage network (DSN). The set of encoded data slices represents data encoded using a dispersed storage error encoding function having a number of encoded data slices in the set of encoded data slices equal to or greater than a decode threshold and the retrieval threshold is equal to or greater than the decode threshold. The method continues with the processing module issuing data retrieval requests to the DSN for the set of encoded data slices and receiving encoded data slices of the set of encoded data slices to produce received encoded data slices. The method continues with the processing module decoding the received encoded data slices to recapture the data when a number of received encoded data slices compares favorably to the retrieval threshold.Type: GrantFiled: May 20, 2013Date of Patent: January 7, 2014Assignee: Cleversafe, Inc.Inventors: Greg Dhuse, Ilya Volvovski, Andrew Baptist, Sebastien Vas, Zachary J. Mark
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Patent number: 8621271Abstract: A method begins by a processing module identifying a memory device having an expired useable memory life with respect to a legacy storage protocol. The method continues with the processing module extracting data from the memory device. The method continues with the processing module reprovisioning the memory device from the legacy storage protocol to a dispersed storage error coding storage protocol.Type: GrantFiled: August 5, 2011Date of Patent: December 31, 2013Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison, Jason K. Resch
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Patent number: 8612827Abstract: A computer includes an interface and a processing module. The processing module receives, over time and via the interface, requests to playback recorded broadcast data, wherein a single copy of the recorded broadcast data is dispersed error encoded to produce a plurality of sets of encoded data slices that is stored in a dispersed storage network (DSN). In response to the playback requests, the processing module identifies unique combinations of at least a threshold number of encoded data slices for sets of the plurality of sets of encoded data slices to produce unique copies of the recorded broadcast data. For a particular playback request, the processing module retrieves a unique copy of the unique copies of the recorded broadcast data from the DSN and outputs, via the interface, the retrieved unique copy to a device associated with the particular playback request.Type: GrantFiled: January 8, 2013Date of Patent: December 17, 2013Assignee: Cleversafe, Inc.Inventors: S. Christopher Gladwin, Kumar Abhijeet, Greg Dhuse, Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Patent number: 8612831Abstract: A method begins by a processing module forward error correction (FEC) encoding data to produce FEC encoded data and dividing the FEC encoded data into a set of FEC encoded words. The method continues with the processing module generating integrity information based on the data and generating a word name for an FEC encoded word of the set of FEC encoded words. The method continues with the processing module affiliating an address of allocated address space of a dispersed storage memory with the word name and storing the integrity information, the word name, and the address. The method continues with the processing module creating a write command to store the FEC encoded word at the address in the dispersed storage memory.Type: GrantFiled: June 6, 2011Date of Patent: December 17, 2013Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison
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Patent number: 8607122Abstract: A method begins by a dispersed storage (DS) processing module generating a data object identifier for data to be stored in a dispersed storage network (DSN) and partitioning the data into a plurality of data partitions based on a set of retrieval preferences and data boundary information. For a data partition, the method continues with the DS processing module dispersed storage error encoding the data partition to produce a plurality of sets of encoded data slices and generating a plurality of sets of DSN addresses for the plurality of sets of encoded data slices, wherein a DSN address of the plurality of sets of DSN addresses includes a representation of the data object identifier, a representation of one or more retrieval preferences of the set of retrieval preferences, a representation of a corresponding portion of the data boundary information, and dispersed storage addressing information.Type: GrantFiled: September 12, 2012Date of Patent: December 10, 2013Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Wesley Leggette
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Patent number: 8601348Abstract: Provided are a method, system, and article of manufacture for error checking addressable blocks in storage. Addressable blocks of data are stored in a storage in stripes, wherein each stripe includes a plurality of data blocks for one of the addressable blocks and at least one checksum block including checksum data for the addressable block. A write request is received to modify data in one of the addressable blocks. The write and updating the checksum are performed in the stripe having the modified addressable block. An indication is made to perform an error checking operation on the stripe for the modified addressable block in response to the write request, wherein the error checking operation reads the data blocks and the checksum in the stripe to determine if the checksum data is accurate. An error handling operation is initiated in response to determining that the checksum data is not accurate.Type: GrantFiled: January 15, 2013Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: James L. Hafner, David R. Kahler, Robert A. Kubo, David F. Mannenbach, Karl A. Nielsen, James A. O'Connor, Richard B. Stelmach, Krishnakumar R. Surugucchi
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Patent number: 8595586Abstract: Fault-tolerant storage is provided using a distributed data storage system that receives input data from clients and divides that data into data blocks for storage. The data blocks are processed using a coding scheme that generates redundant level one error correction blocks (L1EC Blocks). The L1EC blocks enable the reconstruction of one or more damaged or inaccessible data blocks, so long as sufficient undamaged elements are still accessible. The L1EC blocks and the data blocks are divided into distribution sets and these sets are stored at a plurality of data storage locations. At each data storage location additional level two error correction blocks (L2EC blocks) are generated that provide local data redundancy. The L2EC blocks enable reconstruction of damaged elements at a data storage location without requiring communication with the other data storage locations.Type: GrantFiled: April 25, 2012Date of Patent: November 26, 2013Assignee: Facebook, Inc.Inventors: Dhrubajyoti Borthakur, Per Brashers, Jason Matthew Taylor
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Patent number: 8595596Abstract: A method begins by receiving streaming data. The method continues by partitioning the streaming data into a first data stream and a second data stream. For the first data stream, the method continues by encoding, in accordance with error coding dispersed storage function parameters, the first data stream into a first encoded data slices. The method continues by determining first memory of a DSN to store the first encoded data slices and facilitating storage of the first encoded data slices in the first memory. For the second data stream, the method continues by encoding, in accordance with the error coding dispersed storage function parameters, the second data stream into a second encoded data slices. The method continues by determining second memory of the DSN to store the second encoded data slices and facilitating storage of the second encoded data slices in the second memory.Type: GrantFiled: April 25, 2013Date of Patent: November 26, 2013Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison
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Patent number: 8595595Abstract: A storage server stores data in a stripe of a parity group that includes a plurality of data storage devices to store data and a parity storage device to store parity information. The stripe includes a data block from each of the data storage devices and a parity block from the parity storage device. The storage server receives a data access request specifying a data block in the stripe, and a lost write detection module detects an error in the data block. The lost write detection module compares a first storage device signature stored in a metadata field associated with the data block to a second storage device signature stored in a global field of the data storage device containing the data block. If the first storage device signature matches the second storage device signature, the lost write detection module compares a consistency point count stored in the metadata field to a reconstructed consistency point count.Type: GrantFiled: December 27, 2010Date of Patent: November 26, 2013Assignee: NetApp, Inc.Inventors: Tomislav Grcanac, Atul Goel, Jagadish Vasudeva, Gururaj MJ
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Patent number: 8583988Abstract: A computer program product for performing input/output (I/O) processing is provided. The computer program product is configured to perform: obtaining information relating to an I/O operation at a channel subsystem; generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data check word generation field and/or a data check word save field; responsive to receiving an input data transfer request including at least one data check word, storing the at least one data check word in the data check word save field and performing a check of the data to determine whether the data has been corrupted; and responsive to receiving an output data transfer, generating at least one data check word based on the data check word generation field and appending the at least one data check word to the data.Type: GrantFiled: June 1, 2011Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: Clinton E. Bubb, Daniel F. Casper, John R. Flanagan
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Patent number: 8583990Abstract: An apparatus and associated method provided for a plurality of storage elements arranged and concurrently accessible in an array. A controller executes programming instructions stored in memory to append an error correction code (ECC) block to a first data block and to store the first data block with appended ECC block in a first storage element of the plurality, the appended ECC block associated with a second data block other than the first data block.Type: GrantFiled: November 30, 2011Date of Patent: November 12, 2013Assignee: Spectra Logic CorporationInventor: Matthew Thomas Starr
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Patent number: 8583989Abstract: An input/output processing method includes generating and storing at least one address control word (ACW) including a data check word generation field and/or a data check word save field in local channel memory of a channel subsystem, and generating and forwarding to a network interface an address control structure specifying a location in the local channel memory of a corresponding ACW. The method also includes, responsive to a data transfer request, storing the at least one data check word in the data check word save field and routing the data to a host memory location specified by the corresponding ACW responsive to performing a check of the data and determining that the data has not been corrupted, or retrieving the data based on the corresponding ACW, generating and appending at least one data check word and routing the data and the at least one data check word to the interface.Type: GrantFiled: October 22, 2012Date of Patent: November 12, 2013Assignee: International Business Machines CorporationInventors: Clinton E. Bubb, Daniel F. Casper, John R. Flanagan
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Patent number: 8583992Abstract: Embodiments of the present invention provide a storage device of a serial-attached small computer system interface/serial advanced technology attachment (PCI-Express) type that supports a low-speed data processing speed for a host. Specifically, the present invention provides a SSD memory system comprising (among other components) a set (at least one) of SSD memory disk units. Each SSD memory disk unit generally comprises (among other components), a host interface unit; a serial-attached small computer system interface (SAS) protocol controller for controlling a SAS protocol of the SSD memory disk unit coupled to the host interface unit; a direct memory access (DMA) controller for controlling access to the SSD memory disk unit coupled to the host interface unit; and a data buffer for buffering data stored in the SSD memory disk unit coupled to the DMA controller.Type: GrantFiled: January 20, 2011Date of Patent: November 12, 2013Assignee: Taejin Info Tech Co., Ltd.Inventor: Byungcheol Cho
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Patent number: 8583984Abstract: A method and apparatus to enable data integrity checking of a block of data while the block of data is being transferred from a volatile memory to a non-volatile storage device is provided. The data integrity checking is performed in conjunction with Direct Memory Access operations and Redundant Array of Independent Disk (RAID) operations. In addition, data integrity checking of syndrome blocks in the RAID is performed during transfers to/from the storage devices in the RAID system and during RAID update and RAID data reconstruction operations.Type: GrantFiled: December 22, 2010Date of Patent: November 12, 2013Assignee: Intel CorporationInventors: Mark A. Schmisseur, Sivakumar Radhakrishnan, Pankaj Kumar, Marc A. Goldschmidt, Peter Molnar
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Patent number: 8566673Abstract: A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.Type: GrantFiled: August 4, 2011Date of Patent: October 22, 2013Assignee: LSI CorporationInventors: Kevin Kidney, Kenneth Day
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Patent number: 8555130Abstract: A method begins by a processing module receiving a write request that includes a batch of encoded data slices and a corresponding batch of slice names, wherein the batch of encoded data slices includes encoded data slices that have slices names that have a common data object storage name, a common slice storage name, and a different data segment storage name. The method continues with the processing module determining whether a storage file exists based on the common data object storage name. The method continues with the processing module creating the storage file based on the common data object storage name when the storage file does not exist. The method continues with the processing module storing the batch of encoded data slices in the storage file based on the corresponding batch of slice names.Type: GrantFiled: October 4, 2011Date of Patent: October 8, 2013Assignee: Cleversafe, Inc.Inventors: Andrew Baptist, Ilya Volvovski, Wesley Leggette, Greg Dhuse, Jason K. Resch
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Patent number: 8555142Abstract: A method for verifying integrity of data stored in dispersed storage memory begins by a processing module retrieving integrity information of the data that is stored as a set of forward error correction (FEC) encoded words in the dispersed storage memory and continues with the processing module receiving FEC encoded words of the set of FEC encoded words from the dispersed storage memory to produce received FEC encoded words and decoding a unique subset of the received FEC encoded words to produce recovered data. The method continues with the processing module generating recovered integrity information from the recovered data and comparing the recovered integrity information with the integrity information. The method continues with the processing module indicating that at least one of the received FEC encoded words of the unique subset of the received FEC encoded words is corrupt when the recovered integrity information compares unfavorably with the integrity information.Type: GrantFiled: June 6, 2011Date of Patent: October 8, 2013Assignee: Cleversafe, Inc.Inventors: Gary W. Grube, Timothy W. Markison
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Patent number: 8549378Abstract: Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.Type: GrantFiled: June 24, 2010Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Luiz C. Alves, Luis A. Lastras-Montano, Patrick J. Meaney, Eldee Stephens, Barry M. Trager
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Patent number: 8549388Abstract: According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit.Type: GrantFiled: February 25, 2011Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Fukutomi, Hiroshi Yao, Shinichi Kanno, Shigehiro Asano, Toshikatsu Hida, Yasuhiro Kimura
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Publication number: 20130238957Abstract: A centralized DVR includes a dispersed storage error encoding module, storage nodes, and a distribution module. The dispersed storage error encoding module encodes a broadcast of data in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices, which is stored in the storage nodes. For a first playback request, the distribution module determines a first unique combination and retrieves, as a first unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the first unique combination. For a second playback request, the distribution module determines a second unique combination and retrieves, as a second unique copy of the broadcast data from the storage nodes, encoded data slices of the plurality of sets of encoded data slices in accordance with the second unique combination.Type: ApplicationFiled: April 25, 2013Publication date: September 12, 2013Applicant: CLEVERSAFE, INC.Inventors: Gary W. Grube, Timothy W. Markison
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Patent number: 8533570Abstract: According to one embodiment, there is provided a magnetic recording apparatus configured to record data subjected to error correcting coding according to a shingled recording scheme, the magnetic recording apparatus including a magnetic recording medium in which unit bits of the data subjected to error correcting coding are recorded with phase shifted between adjacent tracks, a read head having a width covering a plurality of tracks and configured to read data from the plurality of tracks, and a recording controller configured to record the data subjected to error correcting coding and a parity for the data in the plurality of tracks covered by the read head, in a divided manner.Type: GrantFiled: August 12, 2011Date of Patent: September 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Akihiro Itakura, Masatoshi Sakurai
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Patent number: 8527828Abstract: A method begins by a processing module receiving a plurality of record requests to record a broadcast of data. The method continues with the processing module encoding the data using an error coding dispersal storage function to produce a plurality of sets of encoded data slices. The method continues with the processing module generating a list of requesting device identities corresponding to the plurality of requests and storing the plurality of sets of encoded data slices and the list of requesting device identities in a dispersed storage network memory. The method continues with the processing module receiving a playback request from a device identified in the list of requesting device identities, generating a unique retrieval matrix for the device, and outputting a unique plurality of sets of encoded data slices from the plurality of sets of encoded data slices in accordance with the unique retrieval matrix.Type: GrantFiled: July 2, 2012Date of Patent: September 3, 2013Assignee: Cleversafe, Inc.Inventors: Timothy W. Markison, Gary W. Grube
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Publication number: 20130227346Abstract: A method for controlling a nonvolatile memory device includes reading a sub stripe including a plurality of sub pages stored in a first region, writing data stored in valid sub pages of the sub stripe to a second region different from the first region, and generating parity data using the data written to the second region and constituting a new sub stripe.Type: ApplicationFiled: September 13, 2012Publication date: August 29, 2013Inventor: Yang-Sup Lee
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Patent number: 8522074Abstract: A method begins by a processing module receiving a first request to store a program. The method continues with the processing module determining first error coding dispersal storage function parameters and encoding a data segment of the program. The method continues with the processing module determining whether a second request to store the program is received. The method continues with the processing module encoding a second data segment of the program in accordance with the first error coding dispersal storage function parameters when the second request is not received. The method continues with the processing module changing the first error coding dispersal storage function parameters based on the another request to produce second error coding dispersal storage function parameters when the second request is received. The method continues with the processing module encoding the second data segment in accordance with the second error coding dispersal storage function parameters.Type: GrantFiled: July 23, 2010Date of Patent: August 27, 2013Assignee: Cleversafe, Inc.Inventors: Timothy W. Markison, Gary W. Grube, S. Christopher Gladwin, Alan E. Holmes, Wesley Leggette, Jason K. Resch
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Patent number: 8516342Abstract: A triple parity (TP) technique reduces overhead of computing diagonal and anti-diagonal parity for a storage array adapted to enable efficient recovery from the concurrent failure of three storage devices in the array. The diagonal parity is computed along diagonal parity sets that collectively span all data disks and a row parity disk of the array. The parity for all of the diagonal parity sets except one is stored on the diagonal parity disk. Similarly, the anti-diagonal parity is computed along anti-diagonal parity sets that collectively span all data disks and a row parity disk of the array. The parity for all of the anti-diagonal parity sets except one is stored on the anti-diagonal parity disk. The TP technique provides a uniform stripe depth and an optimal amount of parity information.Type: GrantFiled: May 15, 2012Date of Patent: August 20, 2013Assignee: NetApp, Inc.Inventors: Peter F. Corbett, Atul Goel
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Patent number: 8504847Abstract: A data element can be encoded into multiple encoded data elements using an encoding algorithm that includes an encoding function and one or more encoder constant. The encoded data elements can be organized into multiple pillars, each having a respective pillar number. Each of the pillars is sent to a different storage unit of a distributed storage network. To recover the original data element, the encoded data elements are retrieved from storage, and the encoder constant is recovered using multiple encoded data elements. Recovering the encoder constant allows the encoding algorithm originally used to encode the data elements to be determined, and used to recover the original data element. The security of the stored data is enhanced, because an encoded data element from a single pillar is insufficient to identify the encoder constant.Type: GrantFiled: April 18, 2010Date of Patent: August 6, 2013Assignee: Cleversafe, Inc.Inventors: Jason K. Resch, Wesley Leggette
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Publication number: 20130191703Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.Type: ApplicationFiled: January 19, 2012Publication date: July 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
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Patent number: 8495460Abstract: An apparatus, system, and method are disclosed for reconfiguring an array of solid-state storage elements. The method includes determining that one or more storage elements are unavailable to store data. The storage elements are configured in an array of N storage elements that each store a portion of a first ECC chunk and P storage elements that store first parity data corresponding to the first ECC chunk. The method includes generating a second ECC chunk comprising at least a portion of the data of the first ECC chunk. The method includes storing the second ECC chunk and associated second parity data across (N+P)?Z storage elements where 1?Z?P.Type: GrantFiled: October 4, 2012Date of Patent: July 23, 2013Assignee: Fusion-IO, Inc.Inventors: David Flynn, Jonathan Thatcher, Joshua Aune, Jeremy Fillingim, Bill Inskeep, John Strasser, Kevin Vigor
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Patent number: 8495469Abstract: A method and controller for implementing enhanced input/output (IO) data conversion with an enhanced protection information model including an enhanced parity format of the data integrity fields (DIF), and a design structure on which the subject controller circuit resides are provided. The controller implements a protection information model including a unique parity data integrity fields (DIF) format. The unique parity DIF format enables corruption detection for RAID parity blocks. The unique parity DIF format includes a predefined size for a protection information model logical block guard cyclic redundancy check (CRC) field and a logical block Reference Tag (RT) field. A plurality of storage devices in a RAID configuration are coupled to the controller, and configured to store data and RAID parity redundancy data, and wherein a strength of RAID parity redundancy data is not reduced when a loss of a single storage device in the plurality of storage devices occurs.Type: GrantFiled: May 16, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Brian E. Bakke, Robert E. Galbraith, Adrian C. Gerhard, Daniel F. Moertl, Rick A. Weckwerth
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Patent number: 8495468Abstract: According to one embodiment, a data storage apparatus including memory chips includes an error correction encoder, a RAID controller, error detectors and memory units. Each of the memory chips includes a semiconductor memory. The error correction encoder adds an error correction code to an encoded data stream. The RAID controller divides the encoded data stream from the error correction encoder into data blocks. The RAID controller generates a parity data block based on the data blocks. The RAID controller outputs the data blocks and parity data block to the error detectors, respectively. The error detectors add an error detection code to the data blocks and parity data block output from the RAID controller. Each of the memory units includes the memory chips. The memory units write the data blocks and parity data block from the error detectors to the memory chips.Type: GrantFiled: January 27, 2011Date of Patent: July 23, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Kenshi Dachiku