Disk Array Patents (Class 714/770)
  • Publication number: 20150149869
    Abstract: Physical subsector error marking allows for selectively marking subsectors of a physical sector of a storage medium as unreadable. The error marking may include a bad sector mask to indicate that the subsector is unreadable combined with an error signature to confirm that the bad sector mask was set intentionally. The remaining readable subsectors of the physical sector may be returned to the host.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Seagate Technology LLC
    Inventors: Weihua Lin, Brian Thomas Edgar, Gerald Allen Houlder, Yong Yang, Shuangyi Tang, Vidya Krishnamurthy
  • Patent number: 9043689
    Abstract: A method begins by a processing module obtaining common storage name information regarding data that is stored in storage units of a distributed storage network (DSN) as a set of data slices. Each data slice of the set of data slices has a unique storage name, where each of the unique storage names for the set of data slices has common naming information regarding the data. The method continues where the processing module interprets the common storage name information to determine whether a difference exists between the common naming information of a data slice of the set of data slices and the common naming information of other data slices of the set of data slices. When the difference exists, the method continues where the processing module indicates a potential storage error of the data slice and implements a storage error process regarding the potential storage error of the data slice.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 26, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, John Quigley, Wesley Leggette, Andrew Baptist
  • Publication number: 20150143200
    Abstract: A method of operating a computer memory system with ECC features that will enable operational modes with less electrical power consumption. A chip mark normally used to mark a failing DRAM device may instead be used to mark a non-failing DRAM device before a computer memory system shuts off electrical power to the marked non-failing DRAM device to reduce power consumption, putting the rank of memory that contains the DRAM device in a low power consumption mode. Upon a request from the computer memory system, the chip mark may be removed from the marked non-failing DRAM device in order to return the non-failing DRAM device to normal operation.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Marc A. Gollub, Joab D. Henderson
  • Patent number: 9032271
    Abstract: In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.).
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yongke Sun, Dengtao Zhao, Jui-Yao Yang
  • Patent number: 9026891
    Abstract: A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 5, 2015
    Assignee: LSI Corporation
    Inventors: Scott M. Dziak, Jeffrey P. Grundvig, Jason D. Byrne
  • Patent number: 9021335
    Abstract: Some aspects of the disclosure relate to a data storage system that includes multiple memory device storage devices. If a memory device of a memory device array fails within a first data storage device, some portions of the lost or corrupted data from the failed memory device are recovered by reading them from a second data storage device. Other portions of the lost or corrupted data from the failed memory device are recovered from parity information in the first data storage device.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: April 28, 2015
    Assignee: NetApp, Inc.
    Inventor: Atul Goel
  • Patent number: 9021339
    Abstract: A data storage system configured to implement a data reliability scheme is disclosed. In one embodiment, a data storage system controller detects uncorrectable errors using intra page parity when data units are read from a set of pages. When an uncorrectable error is detected, the data storage system controller attempts to recover user data using inter page parity without using all data from each page of the set of pages. Recovery of user data can thereby be performed without reading all data from each page. As a result, the amount of time needed to read data can be reduced in some cases and overall data storage system performance can be increased.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: April 28, 2015
    Assignees: Western Digital Technologies, Inc., Skyera, Inc.
    Inventors: Guangming Lu, Leader Ho, Radoslav Danilak, Rodney N. Mullendore, Justin Jones, Andrew J. Tomlin
  • Publication number: 20150089328
    Abstract: System and method embodiments are provided for managing storage systems. In an embodiment, a storage system includes an over-provisioned redundant array of independent disks (RAID); and a flexible erasure coding controller coupled to the RAID, the controller comprising a flexible exclusive-or engine configured to provide erasure coding for the over-provisioned RAID using M-parity convolution codes.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 26, 2015
    Inventors: Xiaobing Lee, Chunlei Dong, Yong Chen, Jinshui Liu
  • Patent number: 8990665
    Abstract: A flash memory controller, a computer readable medium and a method. The method may include performing, by a flash memory controller, multiple read attempts of a group of flash memory cells, using multiple read thresholds, to provide multiple read results; determining, by the flash memory controller and based upon the multiple read results, a reliability metric of each of the multiple read results; and error correction decoding the multiple read results based upon reliability metrics associated with the multiple read results.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: March 24, 2015
    Assignee: Densbits Technologies Ltd.
    Inventors: Avi Steiner, Hanan Weingarten, Erez Sabbag
  • Patent number: 8984371
    Abstract: A method begins, as data objects are ingested, by determining, for each of some of the data objects, a priority indicator to produce a listing of priority indicators. The method continues for a data object by determining encoding parameters based on a corresponding priority indicator. The method continues by encoding the data object in accordance with the encoding parameters to produce a plurality of sets of encoded data slices and storing them. The method continues by identifying a first data object for analysis based on a corresponding priority indicator and an analysis priority. The method continues by decoding a plurality of sets of encoded data slices to recover the first data object and analyzing it in accordance with analysis criteria to determine its relevancy. The method continues by issuing a command to delete the plurality of sets of encoded data slices when the relevancy is below a threshold.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: March 17, 2015
    Assignee: Cleversafe, Inc.
    Inventors: S. Christopher Gladwin, Thomas Franklin Shirley, Jr., Jason K. Resch
  • Patent number: 8977931
    Abstract: A method begins by a DS processing module generating a plurality of encoded slices from a data segment using an error encoding function. The method continues with the DS processing module identifying a plurality of DS storage units for storing the plurality of encoded slices. The method continues with the DS processing module selecting an encoded slice of the plurality of encoded slices for sub-slicing using a sub-slicing encoding function to produce a selected encoded slice. The method continues with the DS processing module outputting the plurality of encoded slices to the plurality of DS storage units. The method continues with the DS processing module outputting a command to a DS storage unit of the plurality of DS storage units corresponding to the selected encoded slice, wherein the command includes an instruction to sub-slice the selected encoded slice.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 10, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8966341
    Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 24, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
  • Patent number: 8965939
    Abstract: A method begins, in accordance with a segmentation approach, dividing large data to be stored into regions and dividing a region into segments. The method continues by generating preliminary DSN storage information for one or more regions. The method continues by identifying other large data stored in the DSN that has a relationship with the large data to be stored in the DSN and retrieving DSN storage information for the other large data. The method continues by comparing, at a region level, the preliminary DSN storage information with the retrieved DSN storage information. When a region of the large data to be stored has substantially similar DSN storage information as a region of the other large data, the method continues by utilizing the DSN storage information for the region of the other large data for the DSN storage information of the region of the large data.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Wesley Leggette, Jason K. Resch
  • Patent number: 8949312
    Abstract: An embodiment generally relates to a method of updating clients from a server. The method includes maintaining a master copy of a software on a server and capturing changes to the master copy of the software on an update disk image, where the changes are contained in at least one chunk. The method also includes merging the update disk image with one of two client disk images of the client copy of the software.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: February 3, 2015
    Assignee: Red Hat, Inc.
    Inventors: Mark McLoughlin, William Nottingham, Timothy Burke
  • Patent number: 8949695
    Abstract: A method begins by a DS processing module generating a plurality of encoded slices from a data segment using an error encoding function. The method continues with the DS processing module identifying a plurality of DS storage units for storing the plurality of encoded slices. The method continues with the DS processing module selecting an encoded slice of the plurality of encoded slices for sub-slicing using a sub-slicing encoding function to produce a selected encoded slice. The method continues with the DS processing module outputting the plurality of encoded slices to the plurality of DS storage units. The method continues with the DS processing module outputting a command to a DS storage unit of the plurality of DS storage units corresponding to the selected encoded slice, wherein the command includes an instruction to sub-slice the selected encoded slice.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: February 3, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8935593
    Abstract: A method and apparatus uses a flexible buffering scheme in an XOR engine to generate checksums, allowing a user to recover data when a disk drive partly or completely fails. An XOR engine may include three or more arithmetic units and three or more local result buffers, which may be used to generate a combination of any of a “P” checksum, a “Q” checksum, and an unmodified copy of the user data, in a single read. The local result buffers and arithmetic units allow the use of multiple Galois field Multiply coefficients so that multiple distinct “Q” checksums may be generated with only one read of the user data.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Marvell International Ltd.
    Inventors: David Geddes, Xinhai Kang
  • Patent number: 8930780
    Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: January 6, 2015
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Bruce A. Wilson
  • Publication number: 20140380127
    Abstract: Data is obtained at a data storage system. Codewords are generated from the obtained data. The codewords are computed using a folded code and each codeword comprises symbols. The codewords are stored on an array of disks associated with the data storage system in accordance with a codeword symbol mapping that is specified by at least one parameter of the folded code used to generate each codeword.
    Type: Application
    Filed: January 29, 2014
    Publication date: December 25, 2014
    Applicant: EMC CORPORATION
    Inventors: Alexander N. Alexeev, Peter V. Trifonov
  • Publication number: 20140380128
    Abstract: A method begins by a processing module determining to change storage format from a redundant array of independent disks (RAID) format to a dispersed storage network (DSN) format. The method continues with the processing module retrieving the data from a RAID memory that is stored in the RAID format to produce retrieved RAID data. The method continues with the processing module converting stripe-block data of the retrieved RAID data into a plurality of sets of encoded data slices and reprovisioning the RAID memory for storing DSN formatted data to produce reprovisioned memory. The method continues with the processing module outputting the plurality of sets of encoded data slices to at least one of the RAID memory and a DSN memory for storage therein.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Andrew Baptist, Gary W. Grube, Timothy W. Markison, Jason K. Resch
  • Patent number: 8918701
    Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to tr erasures in any one of the r rows, up to tr?1 erasures in any one of the remaining r?1 rows, up to tr?2 erasures in any one of the remaining r?2 rows, and so on, such that the encoding allows recovery from up to t1 erasures in the last remaining row. Encoded write data is output from the encoding. The encoded write data is written as a write stripe across n storage devices in a storage array.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
  • Patent number: 8914706
    Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: December 16, 2014
    Assignee: Streamscale, Inc.
    Inventor: Michael H. Anderson
  • Patent number: 8910031
    Abstract: A block CRC based fast data hash provides efficient data integrity verification functions. A hash word is generated from block CRCs that are stored along with data blocks in a hard drive for each data and/or parity track of a storage system, such as a RAID array. Each storage system member writes the hash word into a global memory. Thereafter, a director verifies data integrity using all member's hash words with one or more XOR operations. Use of the hash words for data integrity verification saves system bandwidth and CPU processing resources.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: December 9, 2014
    Assignee: EMC Corporation
    Inventors: ZhiGang Liu, Dale Elliott, Stephen Richard Ives, Shen Liu, Andrew Chanler
  • Patent number: 8910022
    Abstract: A computing device includes a central processing unit (CPU) and a memory system module. The CPU includes a data dispersed storage error coding (DSEC) module operable to DSEC decode a set of encoded ingress data slices to recapture ingress data and DSEC encode egress data to produce a set of encoded egress data slices, an instruction DSEC module operable to DSEC decode a set of encoded instruction slices to recapture an instruction, and an arithmetic logic unit (ALU) operable to, execute the instruction on the ingress data and execute the instruction to produce the egress data. The memory system module is operable to coordinate retrieval of the set of encoded ingress data slices from memory, coordinate retrieval of the set of encoded instruction slices from the memory, and coordinate storage of the set of encoded egress data slices in the memory.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: December 9, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
  • Patent number: 8880981
    Abstract: A data access request is received specifying a data block stored in a stripe of a parity group that includes a plurality of data storage devices to store data blocks and a parity storage device to store parity information for the data. The stripe includes a data block from each of the plurality of data storage devices and the stripe includes a parity block from the parity storage device. An error is detected in the data block specified by the data access request. The error is identified as a lost write error for the data block or a lost write error for the parity block. Identifying the error includes comparing a first storage device signature stored in a metadata field associated with the data block to a second storage device signature stored in a label block identifying a data storage device where the data block is stored.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 4, 2014
    Assignee: NetApp, Inc.
    Inventors: Tomislav Grcanac, Atul Goel, Jagadish Vasudeva, Gururaj Mj
  • Patent number: 8874995
    Abstract: Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving and arranging read data in array that includes m rows and n columns of entries, with each entry including at least one sector. In the array, mr+s locations are assigned to parity entries, such that each row has at least r parity entries. The parity entries correspond to a partial-maximum distance separable (PMDS) code that allows recovery from up to r erasures in each of the m rows as well as s additional erasures in any locations in the data array, where s is an integer greater than zero. The write data and the associated parity entries are written to the set of storage devices.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
  • Patent number: 8869006
    Abstract: Embodiments of the invention relate to correcting erasures in a storage array. A read stripe is received from a plurality of n storage devices. The read stripe includes an array of entries arranged in m rows and n columns with each column corresponding to one of the storage devices. The entries include data entries and mr+s parity entries. Each row contains at least r parity entries generated from the data entries according to a partial maximum distance separable (PMDS) code. It is determined that the read stripe includes at least one erased entry, at most mr+s erased entries and that no row has more than r+s erased entries. The erased entries are reconstructed from the non-erased entries, resulting in a recovered read stripe.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business machines Corporation
    Inventors: Mario Blaum, James L. Hafner, Steven R. Hetzler
  • Patent number: 8856620
    Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
  • Patent number: 8856619
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for storing data reliably across groups of storage nodes. In one aspect, a method includes receiving (n?f) data chunks for storage across n groups of storage nodes and generating (f?1) error-correcting code chunks using an error-correcting code and the (n?f) data chunks. The (n?f) data chunks are stored at a first group of storage nodes. Each data chunk of the (n?f) data chunks is stored at a respective second group of storage nodes. Each code chunk of the (f?1) code chunks is stored at a respective third group of storage nodes. Each second group of storage nodes and each third group of storage nodes is distinct from each other and from the first group of storage nodes.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 7, 2014
    Assignee: Google Inc.
    Inventor: Robert Cypher
  • Patent number: 8843806
    Abstract: Dynamic graduated memory device protection in redundant array of independent memory (RAIM) systems that include a plurality of memory devices is provided. A first severity level of a first failing memory device in the plurality of memory devices is determined. The first failing memory device is associated with an identifier used to communicate a location of the first failing memory device to an error correction code (ECC). A second severity level of a second failing memory device in the plurality of memory devices is determined. It is determined that the second severity level is higher than the first severity level. The identifier from the first failing memory device is removed based on determining that the second severity level is higher than the first severity level. The identifier is applied to the second failing memory device based on determining that the second severity level is higher than the first severity level.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: September 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, William J. Clarke, Eldee Stephens, Judy S. Johnson
  • Patent number: 8843808
    Abstract: An apparatus comprising an array controller and a frame buffer. The array controller may be configured to read/write data to/from a drive array in response to one or more input/output requests. The frame buffer may be implemented within the array controller and may be configured to perform (i) a first data integrity check to determine a first type of data error and (ii) a second data integrity check to determine a second type of data error. The frame buffer may log occurrences of the first type of error and the second type of error in a field transmitted with the data. The field may be used to determine a source of possible corruption of the data.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: September 23, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Mahmoud K. Jibbe, Arunkumar Ragendran, Britto Rossario, Senthil Kannan, Padmanabhan Pandurangan
  • Publication number: 20140281818
    Abstract: A method and system for performing a shortened acquire cycle for at least one fragment of at least one data sector having coherently written fragments, the coherently written fragments being written during a single rotation of a storage medium. The method includes performing a full acquire cycle for a first fragment of a particular data sector of the at least one data sector. The method further includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. The method also includes reusing at least a portion of the acquisition information of the first fragment to perform a shortened acquire cycle for at least one subsequent coherently written fragment. Additionally, the method includes performing the shortened acquire cycle for the at least one subsequent coherently written fragment.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LSI CORPORATION
    Inventors: Scott M. Dziak, Jeffrey P. Grundvig, Jason D. Byrne
  • Patent number: 8839073
    Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: September 16, 2014
    Assignee: LSI Corporation
    Inventor: Earl T Cohen
  • Patent number: 8832521
    Abstract: An apparatus and method for processing optical information using a low density parity check code are suggested. An optical information recording method includes the steps of encoding data to record into a low density parity check code; representing the data, which is encoded into the low density parity check code, to a spatial light modulator in the unit of a data page; and modulating a recording beam into the data page representing the spatial light modulator to be recorded in the form of hologram in a recording medium. By blocking inexact probability information from being concentrated in the LDPC code block, by achieving exact probability information through effective allocation of a mark, and by improving average accuracy of the pixel, which corresponds to the LDPC code, failure rate of decoding can be minimized so that decoding performance can be improved.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 9, 2014
    Assignee: Maple Vision Technologies
    Inventor: Bi-Woong Chung
  • Publication number: 20140250347
    Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette
  • Patent number: 8819522
    Abstract: A disk array apparatus, if a rebuild error occurs, stores information indicating an error occurrence place in a sector holding unit, and then stops rebuild processing. A host computer, if a rebuild error occurs in the disk array apparatus, acquires the information indicating the error occurrence place from the disk array apparatus. The host computer determines whether the rebuild error does not obstruct continuation of the rebuild processing based on the acquired information indicating the error occurrence place. If it is determined that the rebuild error does not obstruct continuation of the rebuild processing, the host computer instructs the disk array apparatus to resume the rebuild processing while skipping the error occurrence place. In response to the instruction from the host computer, the disk array apparatus resumes the rebuild processing while skipping the error occurrence place.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: August 26, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tatsuru Baba
  • Patent number: 8806300
    Abstract: The storage system includes a plurality of flash memory devices, each of the flash memory devices including a flash memory controller and flash memory chips, which are configured as a RAID group and a storage controller, coupled to the plurality of flash memory devices, configured to receive data from a computer and send the data to a first flash memory device of the plurality of flash memory devices. The flash memory controller of the flash memory device is configured to receive the data from the storage controller and execute a parity operation using the data.
    Type: Grant
    Filed: May 25, 2009
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Jun Kitahara, Masanori Takada, Sadahiro Sugimoto
  • Patent number: 8799598
    Abstract: A system comprising a processor and a memory, wherein said memory comprises instructions that when executed by said processor implement a method. The method includes loading a first portion of a set of redundancy data into a register of the processor for each redundant sector of a plurality of redundant sectors. A second portion of a set of redundancy data is also loaded into the volatile memory for each redundant sector of the plurality of redundant sectors. Loading the second portions of the sets of redundancy data comprises loading a third portion of redundancy data comprising a plurality of second portions of redundancy data for the plurality of redundant sectors.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: August 5, 2014
    Assignee: Spansion LLC
    Inventors: Wei-Kent Ong, Jih-Hong Beh, Sei-Wei Henry Lau, Oon-Poh Ang
  • Patent number: 8788876
    Abstract: The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 8782491
    Abstract: A method begins by a dispersed storage (DS) processing module of a DS unit selecting a data slice for corruption analysis and requesting integrity information for the data slice from one or more other DS units of a dispersed storage network. When the one or more requested integrity information is received, the method continues with the DS processing module analyzing the one or more received integrity information and local integrity information of the data slice stored in the DS unit. When the analysis of the one or more received integrity information and the local integrity information of the data slice is unfavorable, the method continues with the DS processing module identifying the data slice as being corrupted.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: July 15, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Greg Dhuse, Wesley Leggette, Andrew Baptist
  • Patent number: 8782494
    Abstract: A method begins by a dispersed storage (DS) processing module receiving a zero information gain (ZIG) encoded data slice and a subset of encoded data slices of a set of encoded data slices. The method continues with the DS processing module generating a set of ZIG encoded data slices using a ZIG function and corresponding ones of the subset of encoded data slices, wherein the set of ZIG encoded data slices represents additional components of recovery information of a first encoded data slice. The method continues with the DS processing module recreating the first encoded data slice from the ZIG encoded data slice and the set of ZIG encoded data slices. The method continues with the DS processing module decoding the subset of encoded data slices and the first encoded data slice using a dispersed storage error coding function to reproduce data.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 15, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8782113
    Abstract: The invention discloses a method and controller for processing data multiplication in a RAID system. Map tables are generated for all values in a field, respectively. The length of an XOR operation unit is chosen to be appropriate w bits (e.g., 332 bits or 64 bits). One or several XOR operation units form a multiplication unit of a data sector. When computing on-line, data in a disk drive of a disk array are performed with XOR operations in accordance with one of the map tables using an XOR operation unit as one unit while computing on the multiplication unit to obtain a product of multiplication. Making use of the RAID system established according to the disclosed method, only XOR operations are required to compute parity data or recover damaged user data. Moreover, several calculations can be performed simultaneously. Therefore, the efficiency of the RAID system can be effectively improved.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: July 15, 2014
    Assignee: Infortrend Technology, Inc.
    Inventors: Michael Gordon Schnapp, Ching-Hao Chou
  • Patent number: 8769379
    Abstract: A method begins by a processing module obtaining common storage name information regarding data that is stored in storage units of a distributed storage network (DSN) as a set of data slices. Each data slice of the set of data slices has a unique storage name, where each of the unique storage names for the set of data slices has common naming information regarding the data. The method continues where the processing module interprets the common storage name information to determine whether a difference exists between the common naming information of a data slice of the set of data slices and the common naming information of other data slices of the set of data slices. When the difference exists, the method continues where the processing module indicates a potential storage error of the data slice and implements a storage error process regarding the potential storage error of the data slice.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: July 1, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, John Quigley, Wesley Leggette, Andrew Baptist
  • Patent number: 8756480
    Abstract: A method begins by a dispersed storage (DS) processing module monitoring storage of data, wherein the data is encoded using a dispersed storage error coding function to produce a plurality of sets of encoded data slices and is stored as the plurality of sets of encoded data slices. The method continues with the DS processing module determining analysis priority of the data in accordance with an analysis prioritization protocol. When the analysis priority of the data compares unfavorably to a first priority threshold, the method continues with the DS processing module issuing a command to delete an encoded data slice from each set of at least some of the plurality of sets of encoded data slices.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: June 17, 2014
    Assignee: Cleversafe, Inc.
    Inventors: S. Christopher Gladwin, Thomas F. Shirley, Jr., Jason K. Resch
  • Publication number: 20140164877
    Abstract: A method begins, in accordance with a segmentation approach, dividing large data to be stored into regions and dividing a region into segments. The method continues by generating preliminary DSN storage information for one or more regions. The method continues by identifying other large data stored in the DSN that has a relationship with the large data to be stored in the DSN and retrieving DSN storage information for the other large data. The method continues by comparing, at a region level, the preliminary DSN storage information with the retrieved DSN storage information. When a region of the large data to be stored has substantially similar DSN storage information as a region of the other large data, the method continues by utilizing the DSN storage information for the region of the other large data for the DSN storage information of the region of the large data.
    Type: Application
    Filed: February 18, 2014
    Publication date: June 12, 2014
    Applicant: CLEVERSAFE, INC.
    Inventors: Wesley Leggette, Jason K. Resch
  • Patent number: 8751897
    Abstract: Fault-tolerant storage is provided using a distributed data storage system that receives input data from clients and divides that data into data blocks for storage. The data blocks are processed using a coding scheme that generates redundant level one error correction blocks (L1EC Blocks). The L1EC blocks enable the reconstruction of one or more damaged or inaccessible data blocks, and the L1EC blocks and the data blocks are divided into distribution sets and stored at a plurality of data storage locations. At each data storage location additional level two error correction blocks (L2EC blocks) are generated that provide local data redundancy. Upon detecting a data disruption event, an inaccessible data storage location is identified and the elements that were stored at the inaccessible data storage location are reconstructed.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: June 10, 2014
    Assignee: Facebook Inc.
    Inventors: Dhrubajyoti Borthakur, Per Brashers, Jason Matthew Taylor
  • Patent number: 8745467
    Abstract: A dual redundant process controller is provided. The controller comprises a process control application that executes on a first and a second module. When executed by the first module, a first application instance writes a first synchronization information to the second module, reads a second synchronization information from the first module, and, when the second disagrees with the first synchronization information after passage of a time-out interval, performs a resynchronization function; and wherein, when executed by the second module, the second application instance writes the second synchronization information to the first module, reads the first synchronization information from the second module, and, when the first disagrees with the second synchronization information after passage of the time-out interval, performs the resynchronization function.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: June 3, 2014
    Assignee: Invensys Systems, Inc.
    Inventors: Alan A. Gale, Andrew L. Kling, Mark E. Timperley, Lawrence T. Bass, John J. Lavallee, George W. Cranshaw, Alan M. Foskett
  • Patent number: 8738991
    Abstract: Apparatuses, systems, and methods are disclosed for reconfiguring an array of storage elements. A storage element error module is configured to determine that one or more storage elements in an array of storage elements are in error. An array of storage elements stores a first ECC block and first parity data generated from the first ECC block. A data reconfiguration module is configured to generate a second ECC block comprising at least a portion of data of a first ECC block. A new configuration storage module is configured to store a second ECC block and associated second parity data on fewer storage elements than a number of storage elements in an array.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 27, 2014
    Assignee: Fusion-Io, Inc.
    Inventors: David Flynn, Jonathan Thatcher, Joshua Aune, Jeremy Fillingim, Bill Inskeep, John Strasser, Kevin Vigor
  • Patent number: 8732556
    Abstract: A dual redundant process controller is provided. The controller comprises a first processor, memory, and instance of a process control application stored in the first memory. The controller further comprises a second processor, memory, and instance of the process control application stored in the second memory.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 20, 2014
    Assignee: Invensys Systems, Inc.
    Inventors: Alan A. Gale, Andrew L. Kling, Mark E. Timperley, Lawrence T. Bass, John J. Lavallee, George W. Cranshaw, Alan M. Foskett
  • Patent number: 8726129
    Abstract: An embodiment of a method of writing erasure coded data swaps a new data block for an old data block within a stripe of erasure coded data. The stripe of erasure coded data comprises data blocks and a redundancy block. The method computes a redundancy update parameter for the redundancy block using the new data block and the old data block. The method updates the redundancy block using the redundancy block, the redundancy update parameter, and a mathematical operator. An embodiment of a method of recovering erasure coded data obtains a lock on a subset of data blocks and one or more redundancy blocks. The method determines whether the subset of the data blocks and the one or more redundancy blocks includes sufficient blocks to restore the stripe. If not, the method relaxes the lock to allow at least one update of the one or more redundancy blocks while not allowing any writes of the data blocks. The method uses the subset to restore the stripe.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: May 13, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Marcos Kawazoe Aguilera, Ramaprabhu Janakiraman
  • Patent number: 8726127
    Abstract: A method begins by a computing device determining that dispersed storage network (DSN) memory is to be accessed regarding data. The method continues when the computing device is paired with a DSN access token module with the DSN access token module retrieving a plurality of sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with at least one of the computing device and the DSN access token module decoding the plurality of sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function and executing, by one or more of the computing device and the DSN access token module, the DS error coding function to access the DSN memory regarding the data.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 13, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison, Greg Dhuse, Jason K. Resch, Ilya Volvovski, Wesley Leggette