Abstract: Two levels of error correction decoding are performed using first and second level decoders. A composite code formed by combining an inner component code and an outer component code can be used to decode the data and correct any errors. Performing two level decoding using a composite code allows the size of the inner parity block to be reduced to a single Reed-Solomon symbol while keeping a good code rate. The first level decoder generates soft information. The soft information can indicate a most likely error event for each possible syndrome value of the inner component code. The soft information can also include error metric values for each of the most likely error events. The second level decoder generates corrected syndrome values based on the soft information using the outer component code. The most likely trellis path that corresponds to the corrected syndrome values is then selected.

Abstract: ACS (Add Compare Select) implementation for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. During each processing iteration, an ACS module generates a hard decision for each of two trellis stages, as well as a corresponding reliability for each of the two hard decisions. Also, the ACS module is operative to generate the updated state metric for the state at the current trellis stage. Multiple operations are performed simultaneously and in parallel, and control logic circuitry and/or operations employed to select which of the multiple simultaneously-generated resultants is to be employed for each of the hard decisions, reliabilities, and next state metric for the current trellis stage.

Abstract: A partial bit demodulation section demodulates partial bits among a plurality of bits that form one symbol of each modulated signal using a detection method different from likelihood detection. Signal point reduction sections reduce the number of candidate signal points using demodulated partial bits. A likelihood detection section obtains received digital signals by performing likelihood detection based on the Euclidian distances between the reduced candidate signal points and a reception point. Only some bits which are unlikely to be erroneous are found by the partial bit demodulation section, and other bits can be found by the likelihood detection section, enabling bit error rate performances to be effectively improved with a comparatively small computational complexity.

Abstract: Register exchange network for radix-4 SOVA (Soft-Output Viterbi Algorithm). Two trellis stages are processed simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within an REX (Register Exchange) module are implemented using a radix-4 architecture to increase data throughput. Any one or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) are implemented in accordance with the principles of radix-4 decoding processing.

Abstract: A method and apparatus for decoding of tailbiting convolutional codes (TBCC) are disclosed. The proposed modified maximum-likelihood TBCC decoding technique preserves error correction performance of optimal maximum-likelihood based TBCC decoding, while the computational complexity is substantially decreased since a reduced number of decoding states has been evaluated. Compare to other sub-optimal TBCC decoding algorithms, modified maximum-likelihood TBCC decoding achieves improved packet error rate performance with similar computational complexity.

Abstract: Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.

Abstract: An LDPC decoder has a determined number of processing units operating in parallel. Storage circuitry contains first words having a juxtaposition of a first type of message. The storage circuitry also contains second words having a juxtaposition of a second type of message. A message provision unit provides each processing unit with the messages. A message write unit may write words into the storage circuitry in a way that depends on the contents of the words. The message provision unit may provide data in a way that depends on the contents of the words.

Abstract: A decoding apparatus, decoding the LDPC code using a message passing algorithm, sets a message as a log likelihood ratio having, as a base, a real number “a” which is a power of 2, and includes a check node processing calculating unit for receiving a message from a bit node to calculate a message from a check node. The check node processing calculating unit includes a converter for converting an absolute value x of the message to output f (x) and a converting unit supplied as an input y with a sum of the absolute values x of the message from the totality of the bit nodes less one, converted by the converter, subdividing the input y in preset domains and for converting the number in the domain into g (y), and expresses the boundary values of the domains of the input y and f (x) by a power of 2.

Abstract: A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix with a shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns are grouped, so that only one column in the group contributes to the parity check sum in a row. A parity check value estimate memory is arranged in banks logically connected in various data widths and depths. A parallel adder generates extrinsic estimates for generating new parity check value estimates that are forwarded to bit update circuits for updating of probability values. Parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.

Abstract: Methods and apparatus are provided for determining survivor paths in a Viterbi detector, using a trace-ahead algorithm. A trellis memory is maintained having a depth L that stores L trellis stages, each of the L stages having a plurality, N, of trellis states; and a status memory is maintained for each of the N states of the trellis, wherein each entry in the status memory identifies a least recent trellis state stored in the trellis memory of a survivor path that begins at a given state on a side of the trellis associated with most recent states. A bit sequence of one or more of the survivor paths in the trellis is determined in an order that the bits are received by examining least and most recent trellis stages of the trellis and the status memory. One or fork memories maintain an indicator of whether a given fork is active; a list of active forks; a trellis position of active forks in the trellis; and a fork type of one or more forks in the trellis.

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).

Abstract: A digital signal processor performs turbo and Virterbi channel decoding in wireless systems. The computation block of the digital signal processor is provided with an accelerator for executing instructions associated with trellis computations. An ACS instruction performs trellis computations of alpha and beta metrics. Multiple butterfly calculations can be performed in response to a single instruction. A TMAX instruction is used to calculate the log likelihood ratio of the trellis.

Abstract: In the method for termination of turbo decoding, a plurality of first LLR values (Lai(k)) of a-priori information and a plurality of second LLR values (Lei(k)) of extrinsic information are called up. A value is determined for a decision variable which is characteristic of the number of mathematical sign discrepancies between the first Lai(k)) and the second Lei(k)) values. The turbo decoding is terminated if the number of mathematical sign discrepancies is less than or at least equal to a first number or if the number is greater than or at least equal to a second number.

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract: A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected forward Viterbi operator and two associated reverse Viterbi operators process the entire block of data, in order, to produce soft decision data.

Abstract: A system and method are provided for maximum likelihood estimation in a channel receiving data with inter-symbol interference (ISI). The method receives a serial stream of digital information bits. Decisions are made concerning the received information bit values, which the method accepts as processed information, with soft decisions (SDs) and corresponding initial hard decisions (HDs). The method then identifies a sequence of processed information in a correction matrix, and uses the correction matrix to cross-reference the sequence to a HD look-up value. In response to accessing the HD look-up value, a modified HD is created. The modified HD is decoded, for example, by using forward error correction (FEC), creating a decoded HD. The method compares the decoded HD to the initial HD, and updates the correction matrix HD look-up value in response to the comparison.

Abstract: A method and an apparatus is provided for producing branch metrics in a LogMAP turbo decoding operation. During a forward recursion of a trellis, a set of primary branch metrics is generated. The primary branch metrics are stored in receiver form in a relatively small memory cache module and corresponding secondary branch metrics are produced by negating the primary branch metrics. The primary branch metrics and the secondary branch metrics constitute all possible branch metrics for a given state in the trellis. During a backwards recursion of the trellis, the stored primary branch metrics are retrieved from the memory cache module and the secondary branch metrics are regenerated by negating the retrieved primary branch metrics.

Abstract: A receiver baseband processor comprises a channel estimator that generates a channel estimate from a received symbol. A phase demodulator receives the channel estimate from the channel estimator and selectively rotates the phase of the received symbol. A decoder comprises a branch metric calculator that computes a plurality of branch metrics based on the channel estimate and selectively phase rotated received symbol. A most-likely symbol estimator estimates a clean symbol based on the plurality of branch metrics.

Abstract: A method of assessing an encoded signal to determine whether a candidate format was used to arrange the signal into blocks before the encoding was done, the method comprising: using the Viterbi algorithm to determine trellis metrics for a point in said signal that would be an end point of a candidate block according to the candidate format; determining from said metrics the likelihood of occupation at said point of an end state of an encoding scheme used to create the encoded signal; decoding a part of said signal ending at said point; and performing a check using said decoded part to determine whether the candidate block satisfies an error protection scheme of the candidate format.

Abstract: According to one embodiment, a maximum likelihood decoder includes a branch metric calculator, a processor configured to perform addition, comparison, and selection of an output from the branch metric calculator and a path metric memory, and outputs a selection signal for identifying a selection result, a path memory configured to store a time variation of the selection signal, and a path detection module configured to detect a decoding signal based on the time variation of the stored selection signal. A decoding method includes selecting operation modes of at least one of the branch metric calculator, the processor, and the path memory between a first operation mode in which an operation is performed at a channel rate frequency and a second operation mode in which an operation is performed at a specific frequency lower than the channel rate frequency.

Abstract: An error correction decoder possessing a decoding method with high error correction performance and capable of operating at a low operating frequency and on a reduced circuit scale. A decoding method based on the SOVA method for improving error correction performance and boosting reliability of the soft decision output by allowing branching of paths other than the survival path at trace-back is achieved by preparing a trace-back circuit for each state, and selecting an output from that output and survival state (survival state+difference of likelihood).

Abstract: A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss.

Abstract: The present invention concerns a method of coding information symbols according to a code defined on a Galois field Fq, where q is an integer greater than 2 and equal to a power of a prime number, and of length n=p(q?1), where p>1. This coding is designed so that there exists a corresponding decoding method, also disclosed by the invention, in which the correction of transmission errors essentially comes down to the correction of errors in p words of length (q?1) coded according to Reed-Solomon. The invention is particularly advantageous when, through a suitable choice of parameters, the code according to the invention is an algebraic geometric code: in this case, it is possible to correct the transmission errors by the method already mentioned and/or by a conventional method which is less economical but has a higher performance.

Abstract: A decoding system for eight-to-fourteen modulation or eight-to-sixteen modulation (EFM/ESM), which has an analog to digital converter (ADC), an adaptive equalizer and a Viterbi decoder. The ADC receives an analog signal with an EFM or ESM feature, and converts the analog signal into a digital signal with the EFM or ESM feature. The adaptive equalizer converts the EFM or ESM digital signal into a first signal with a minimum phase feature. The Viterbi decoder receives the first signal and generates a decoding signal in accordance with a Viterbi algorithm and a channel model, and the Viterbi decoder discards nonexistent paths in accordance with the EFM or ESM feature when computing branch metric of a branch or a node.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream. Another method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of N stages for decoding the bits, the first stage using a first of M component codes, and simultaneously executing a plurality of the N stages of decoding, each of the plurality of N stages using a different one of the M component codes.

Abstract: The coding apparatus, coding processing target sequence forming method and Viterbi decoding apparatus of the present invention can realize low delay processing with a minimum number of repetitive processing and suppress the degradation of the accuracy of decoding at the ends of a decoded sequence due to truncation error. In the coding apparatus mounted on the transmitting apparatus (100), a control information rearranging section (130) receives as input a control information sequence, in which a plurality of control information blocks are arranged in a predetermined order, and forms a coding processing target sequence by rearranging the order of the plurality of control information blocks to form an assembled sequence grouping control information blocks comprised of predictable bit sequences in the plurality of control information blocks, and to allocate the assembled sequence to a predetermined position in the control information sequence.

Abstract: The error correction capability for wireless communication carried out involving propagation path fluctuation in time and frequency selectivity can be improved. A soft decision likelihood value inputted to an error correction decoder is multiplied by a weight determined according to the distance between the data symbol and pilot symbol corresponding to the soft decision likelihood value. Namely, the soft decision bit likelihood value corresponding to the data symbol is weighted according to the distances in time or frequency between the pilot symbol and data symbol. The weight is made smaller when the distance in time or frequency is larger.

Abstract: A system and method for communicating data includes an inner encoder for encoding data with the recursive inner rate one code. A modulator coherently modulates a communications signal that carries the data that has been encoded. An interleaver is operative with the inner encoder and modulator to aid in removing correlation of multipath fading channels on consecutive bits. A convolutional encoder is followed by a random interleaver. The modulator can be operative with mini-probe sequences. An equalizer and decoder receives the communications signal and iteratively decodes any recursive inner rate one code and convolutional code in a turbo fashion.

Abstract: The present invention relates to a receiver device and method of detecting a block length of a data block in a data network, wherein a respective theoretical maximum value for a metric of a decoding operation is calculated for each of a plurality of candidate block lengths, and the calculated respective theoretical maximum value is compared to a respective actual value of the metric obtained for each of the plurality of candidate block lengths by the decoding operation. The candidate block length with the highest ratio between the respective actual value and the respective theoretical maximum value is then selected from the plurality of candidate block lengths to determine the block length of the data block.

Abstract: A method of detecting an occurrence of an error event in data and an apparatus for the same are provided. The method includes: preparing an error detection code wherein syndrome sequences for dominant error events are all different; generating a codeword from source data using the error detection code; detecting the occurrence of the dominant error event in the codeword by checking a syndrome computed from the codeword; and determining a type and likely error starting positions of the occurred dominant error event using the syndrome sequences correspond to the syndrome.

Abstract: Block-encoded transmissions of a multi-antenna terminal unit are effectively detected in the presence of co-channel interfering transmissions when the base station has a plurality of antennas, and interference cancellation is combined with maximum likelihood decoding. More specifically, the signals received at the base station antennas are combined in a linear combination that relates to the channel coefficients between the various transmitting terminal units and the base antennas. By selecting proper coefficients for the linear combination and choosing probable transmitted signals that minimize a minimum mean squared error function, the signals of the various terminal units are canceled when detecting the signal of a particular unit. In another embodiment of the invention, the basic approach is used to obtain an initial estimate of the signals transmitted by one terminal unit, and the contribution of those signals is removed from the received signals prior to detecting the signals of other terminal units.

Abstract: A system and method for communicating data includes an inner encoder for encoding data with the recursive inner rate one code. A modulator coherently modulates a communications signal that carries the data that has been encoded. An interleaver is operative with the inner encoder and modulator to aid in removing correlation of multipath fading channels on consecutive bits. A convolutional encoder is followed by a random interleaver. The modulator can be operative with mini-probe sequences. An equalizer and decoder receives the communications signal and iteratively decodes any recursive inner rate one code and convolutional code in a turbo fashion.

Abstract: A decoder decodes a code by selecting, based on a predetermined condition, a path out of paths representing a transition of each of states in a trellis diagram. A storing unit stores, when a path at time k is selected, information on a selection history of a path selected at time prior to time (k?(a constraint length of a code)+1). A path detecting unit detects a path to be excluded from a path selection candidate, based on the information stored in the storing unit and information on a state of a transition source when a state transition occurs from time k?1 to time k.

Abstract: A Viterbi decoder includes a computing device, a memory and a bus. The computing device receives sets of data values and calculates distances for the received sets of data values, accumulates and compares the calculated distances according to a Viterbi algorithm, decides data values and generates control signals dependent on a plurality of decisions associated with a plurality of paths. The memory stores the decided data values and provides at least one output value. The bus connects the computing device and the memory and is configured to convey the control signals to the path memory. The computing device or the memory shifts data strings in the memory according to conditions of the Viterbi algorithm with the control signals associated with the plurality of paths.

Abstract: A method for receiving a signal modulated according to a multilevel coding technique, comprising at least two coding levels each having different noise robustness, said signal including a plurality of symbols each comprising at least one bit, assigned to one of said coding levels, said method comprising at least one decoding iteration including successive steps of decoding each of said received bits, at least one of said decoding steps integrated the result of at least one possible previous decoding step. The invention is characterized in that it consists in decoding said bits according to a predetermined sequence taking into account the robustness of said levels, the bit(s) assigned to the decoding level having the higher noise robustness, called most robust level, being decoded first.

Abstract: A method and apparatus for performing channel compensation and symbol demodulation using an estimated channel impulse response during coherent demodulation of a received Orthogonal Frequency Division Multiplexing (OFDM) signal are provided. In the apparatus, an FFT processor IFFT-processes a received signal. A channel compensator generates a channel-compensated signal by multiplying the FFT received signal by an estimated channel impulse response and calculates the power of the estimated channel impulse response. A symbol demodulator sets the power of the estimated channel impulse response as a reference point defining a minimum distance between signal points in a signal constellation, and decides soft metric values for channel decoding using the reference point and I-channel and Q-channel signal components of the channel-compensated signal. A decoder recovers information bits by decoding the soft metric values.

Abstract: A communication device comprising an ML-APP detector coupled to at least two antennas. The ML-APP detector comprises at least one Hx unit coupled to at least one LLR unit. The Hx unit generates a portion of all possible symbols that can be received and transfers each generated symbol candidate to the LLR unit which performs a conversion operation on the transferred symbol candidate to generate another symbol candidate that is not part of the special portion. In this manner all of the possible symbol candidates are obtained by the LLR unit. The LLR unit compares the symbol candidates to a received symbol to perform a cost calculation. The symbol candidate yielding the lowest cost from the cost calculations of all possible symbol candidates is selected as the best candidate. APP decoding is then performed on the selected candidate using soft information associated with the selected candidate which soft information is generated by the LLR unit.

Abstract: System and method of estimating radio channel bit error rate (BER) in a digital radio telecommunications system wherein the soft output of the turbo decoder is used as pointer or index to look-up-tables containing the bit-wise BER of a certain bit in the data field of the received frame. A quantizer quantizes the received data frame and the quantized bit operates on a switch which selects the appropriate look-up-table. By means of accumulation and scaling the average BER of a certain amount of bits are calculated. Decoding bit-errors may occur but as they are submitted to posterior probability estimation, systematic errors which normally happen at low SNR are avoided.

Abstract: An analog Viterbi decoder for decoding an analog signal is provided that includes a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells arranged to correspond to respective nodes of a trellis diagram, for decoding analog input data using an analog signal processing cell having a circulation type connection structure in which the last processing part is connected to the first processing part; a control unit for performing in parallel a sequential designation of the processing parts with respect to the decoding units; an analog data storage unit including a plurality of capacitors connected in parallel with the processing parts provided in the decoding units; and a first switch unit for storing analog input data in a specific capacitor of the analog data storage units under the control of the control unit. Accordingly, the decoding speed can be remarkably improved.

Abstract: A system and method for communicating data includes an inner encoder for encoding data with the recursive inner rate one code. A modulator coherently modulates a communications signal that carries the data that has been encoded. An interleaver is operative with the inner encoder and modulator to aid in removing correlation of multipath fading channels on consecutive bits. A convolutional encoder is followed by a random interleaver. The modulator can be operative with mini-probe sequences. An equalizer and decoder receives the communications signal and iteratively decodes any recursive inner rate one code and convolutional code in a turbo fashion.

Abstract: The invention relates to a maximum likelihood decoding device that performs Partial Response Maximum Likelihood decoding on a reproduced data signal from a recording media or another source. The device includes a Viterbi detector that performs bit detection from the reproduced signal. The Viterbi device can have variable setting for branch metric calculations based on the reference levels in the reproduced signal. The device measures and attempts to reduce the Euclidean distance between a maximum likelihood path selected by the Viterbi detector and a second path.

Abstract: Considering both performance and cost of an iterative receiver, the present invention provides an iterative signal receiving method for a wireless communications system. The iterative signal receiving method includes utilizing a channel estimating (CE) process to perform channel estimation for a received signal according to first log-likelihood ratio (LLR) data to generate second LLR data, and then generating the first LLR data according to an error correction code (ECC) decoding process and the second LLR data. When the ECC decoding process is a convolutional decoding process, the CE process is a zero-forcing process, a minimum mean square error (MMSE) process or an interpolation-based process. When the ECC decoding process is a low density parity check code (LDPC) decoding process, the CE process is a maximum likelihood (ML) process or a maximum a posteriori (MAP) process.

Abstract: A method is provided to decode data encoded by any block code in a manner that substantially improves the error correction capability of the block codes, and that is independent of the encoder. The structure associated with the method desirably allows the testing of those hypotheses that are known to exist, such that one can use the a priori knowledge of the possible set of hypotheses to only search from among them. The method of decoding data is both advantageous and desirable since knowing the subset of the code word space that is being utilized in essence allows the distance between the code words to be increased yielding significant decoding benefits.

Abstract: A receiver in an OFDM system may include a multi-mode estimator to estimate symbol timing offset for different performance measures. In addition to a maximum likelihood estimation mode, the estimator may have a minimum failure probability estimation mode, a minimum mean square error estimation mode, and a minimum modified mean square error estimation mode.

Abstract: A method of approximating the generation of a logarithm of a sum of exponents, for use in a log-MAP decoding operation, by performing a first operation on the data, calculating a correction term in a second operation, and adding the correction term to the results of the first operation, in which the second operation comprises calculating an approximate correction term by an operation including at least one division stage in which a first result obtained based on said data and at least a first coefficient is divided by a second result obtained based on said data and at least a second coefficient.

Abstract: The system in one embodiment relates to tightly integrating parameter estimation, symbol hypothesis testing, decoding, and rate identification. The present invention provides Turbo-decoding for joint signal demodulation based on an iterative decoding solution that exploits error correction codes. The system iteratively couples an initial amplitude estimator, a symbol estimator, a bank of decoders, and a joint amplitude estimator to produce the symbol estimates.

Abstract: A Viterbi decoding apparatus and a method thereof are disclosed. According to each partial surviving path formed by the decision information of every k continuous symbols of a symbol sequence, the apparatus can write its start trellis state and corresponding partial decoded information into a memory unit. On the other hand, the apparatus performs traceback reads and decode reads according to the content of the memory unit, thereby decoding a decoded information sequence corresponding to the symbol sequence. In this manner, memory space can be saved and the operating speed for traceback/decode reads need no acceleration. Thus, hardware cost and design complexity can be reduced simultaneously.

Abstract: Disclosed is a decoding apparatus for decoding an encoded signal on the basis of a plurality of state-transition trellises having differing state counts. The decoding apparatus includes a decoding section for decoding the encoded signal on the basis of a first state-transition trellis, and a mode selection section for selecting either a first operating mode based on the first state-transition trellis or a second operating mode based on a second state-transition trellis. The second state-transition trellis has a state count smaller than that of the first state-transition trellis. If the mode selection section selects the second operating mode, the decoding section decodes the encoded signal by carrying out a state transition switch from a first state transition to a second state transition.

Abstract: A record reproduction apparatus includes an encoding unit that encodes sector data to be written into a recording medium, by dividing the data into a predetermined number of blocks, and an iterative decoding unit that iteratively decodes the sector data read from the recording medium, by dividing the sector data into the predetermined number of blocks.

Abstract: Efficient front end memory arrangement to support parallel bit node and check node processing in LDPC (Low Density Parity Check) decoders. A novel approach is presented by which the front end design of device capable to decode LDPC coded signals facilitates parallel decoding processing of the LDPC coded signal. The implementation of the front end memory management in conjunction with the implementation of a metric generator operate cooperatively lend themselves for very efficient parallel decoding processing of LDPC coded signals. There are several embodiments by which the front end memory management and the metric generator may be implemented to facilitate this parallel decoding processing of LDPC coded signals. This also allows for the decoding of variable code rate and/or variable modulation signals whose code rate and/or modulation varies as frequently as on a block by block basis (e.g., a block may include a group of symbols within a frame).