Abstract: The present invention concerns a sphere decoder for maximum likelihood receiver intended to receive M-PPM-M?-PAM symbols at M modulation positions and at M? amplitude levels from a plurality P of sources. The sphere decoder uses a Schnorr-Euchner type enumeration adapted to classify the points of a multidimensional PPM-PAM modulation.

Abstract: A method for near maximum-likelihood sequential decoding is provided. According to the method, paths unlikely to become the maximum-likely path are deleted during decoding through a level threshold to reduce decoding complexity. Besides, the method performs maximum-likelihood decoding through sequential decoding by adopting a metric, so that a received signal does not have to go through a hard decision procedure.

Abstract: Embodiments of an iterative decoder with early-exit condition detection and methods for decoding are generally described herein. Other embodiments may be described and claimed. In some embodiments, a first codeword is generated from decoded bits after one or more half-iterations of an iterative decoder, a second codeword from decoded bits after an additional half-iteration of the iterative decoder, and the first and second codewords are compared to determine whether the decoded bits are valid. In some embodiments, double or triple codeword matching is selected based on an estimated signal-to-noise ratio (SNR) and the modulation level.

Abstract: An encoder and decoder using LDPC-CC (Low Density Parity Check-Convolutional Codes) is disclosed. The encoder exhibits encoding rates realized with a small circuit-scale and a high data reception quality. In the encoder (200), an encoding rate setting unit (250) sets an encoding rate (s?1)/s (s=z), and an information creating unit (210) sets information including from information Xs,i to information Xz?1,i to zero. A first information computing unit (220-1) receives information X1,i at time point i to compute the X1(D) term of formula (1). A second information computing unit (220-2) receives information X2,i at time point i to compute the X2(D) term of formula (1). A third information computing unit (220-3) receives information X3,i at time point i to compute the X3(D) term of formula (1). A parity computing unit (230) receives parity Pi?1 at time point i?1 to compute the P(D) of formula (1). The exclusive OR of the results of the computation is obtained as parity Pi at time i. Ax.

Abstract: A transmitter and a receiver are disclosed herein that support transmit antenna diversity using space-time block coding in a wireless communication system. The transmitter produces symbol combinations containing, as their elements, input symbols, the inversions and conjugates of the symbols, and symbols obtained by rotating the phases of the symbols once, forms a matrix having symbols in at least two columns orthogonal to each other with the symbol combinations, and transmits the matrix. The receiver detects symbols that minimize maximum likelihood (ML) decoding metrics over all possible symbols using channel gains from transmit antennas to a receive antenna. Also, the receiver selects candidate symbols among all possible symbols according to the characteristics of transmitted modulation symbols and detects symbols that minimize the ML decoding metrics.

Abstract: A decoding apparatus includes a first decoder and a second decoder as a decoding processor for performing iterative decoding on received data, a hard decision section for calculating hard decision results based on logarithmic likelihood ratios L1 and L2 from the first and second decoders, and a stop determination section performing stop determination on whether or not to stop the iterative decoding on the received data based on the result of the hard decision section. The decoding apparatus completes one-time iterative decoding by executing decoding process in each of the first and second decoders. The stop determination section executes stop determination at the timings of completion of the decoding process in the first decoder and completion of the decoding process in the second decoder.

Abstract: A method for generating soft bit values for a multi-bit symbol encoded in one or more received signals comprises (a) for a plurality of different combinations of multiple bit values, iteratively generating, for each combination, a metric value based on the one or more received signals. The method further comprises (b) for each iteration, maintaining (i) a global extremum register containing a global extremum of the metric values; (ii) a bit occupancy for the global extremum register; and (iii) a plurality of bit bk registers, one for each bit bk in the symbol. Each bit bk register contains an extremum of the metric values corresponding to combinations of multiple bit values whose bit bk value is opposite the bit bk value of the bit occupancy for the global extremum register. The method further comprises (c) generating, for each bit bk in the symbol, a soft bit value based on a difference between the value in the global extremum register and the value in the corresponding bit bk register.

Abstract: A method of demapping in a receiver including deriving M intermediate soft bit values yj for the I and Q data of the input signal as a function of the spacing in the constellation; and limiting the range of the M values yj. A look-up table index is derived for each of the limited M values yj. A look-up table, having 2N+1 entries for supporting up to N soft bit outputs, is indexed using the derived indices; and K soft bits for each of the M values yj of the I and Q data are outputted.

Abstract: Various embodiments of the present invention provide systems and methods for decoding encoded information. For example, a decoder including a branch metric calculator that conditionally calculates a branch metric based on either an actual input or a saturated input. Such a branch metric calculator is operable to receive an actual input, and to compare the actual input with an expected range. At times, the aforementioned comparison yields a comparison result indicating that the actual input is outside of the expected range. A first branch metric associated with a first branch is calculated. Where the first branch has an expected value representing a boundary of the expected range, calculating the first branch metric is done using the saturated input. Further, a second branch metric associated with a second branch is calculated. Where the second branch has an expected value representing something other than a boundary of the expected range, calculating the second branch metric is done using the actual input.

Abstract: Provided is a turbo decoder with a variable scaling factor. The decoding convergence degree of the turbo decoder is evaluated using a sign difference ratio (SDR) value, the iterative-decoding number is limited, a variable scaling factor is calculated and applied in each decoding convergence area based on the SDR value, and the average number of decoding iterations is reduced.

Abstract: An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB) each including a high bit and a low bit. A first ACS circuit produces the first bit-pair and a first carry. A limiting circuit generates the MSB based on the first carry, and limits the MSB to a first predetermined value. A MSB maximum select (MS) unit receives an MSB of second path metrics from another ACS unit, and compares the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection. A MSB storage unit stores the MSB of the first path metrics. A reset unit resets the high bit of the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.

Abstract: Device, system, and method of multi-level feedback. In some embodiments, an apparatus includes: an estimator to estimate a likelihood of correctly decoding an incoming encoded Hybrid Automatic Repeat Request packet of an incoming wireless communication signal by one or more decoders of the apparatus; and a transmitter to transmit a multiple-bit representation of the likelihood of correctly decoding the incoming encoded Hybrid Automatic Repeat Request to a device that transmitted the incoming encoded Hybrid Automatic Repeat Request packet.

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract: The present invention provides systems and methods for detecting a media defect. A circuit providing a hard output and a soft output is used with the hard output and the soft output being combined and the product compared with a threshold. Based at least in part on the comparison, a media defect may be identified.

Abstract: A method for synchronizing receivers that receive turbo encoded signals to a received signal. Turbo encoding may enable signals to be decoded at a much lower signal to noise ratio than previously practical. A traditional method of synchronizing a receiver to an incoming signal is to use a slicer to determine a received symbol and then to compare the determined symbol to the incoming waveform, in order to adjust the phase of the slicer with respect to the incoming signal. At signal low levels, at which turbo encoded signals may be decoded, this slicing method may be prone to errors that may disrupt the synchronization of the receiver to the incoming signal. By replacing the slicer by a Viterbi decoder with zero traceback (i.e., one which does not consider future values of the signal only past values) a prediction as to what the incoming signal is can be made.

Abstract: A DTV transmitting system includes a first pre-processor for coding first enhanced data having a high priority for forward error correction (FEC) at a first coding rate and expanding the first enhanced data at a first expansion rate, and a second pre-processor for coding second enhanced data having a low priority for FEC at a second coding rate and expanding the second enhanced data at a second expansion rate. The receiving system further includes a data formatter for generating enhanced data packets, a multiplexer for multiplexing the enhanced data packets with main data packets, an RS encoder for RS-coding the multiplexed data packets, and a data interleaver for interleaving the RS-coded data packets and outputting a group of interleaved data packets having a head, a body, and a tail.

Abstract: An evaluation value calculating apparatus includes the following elements. A difference metric selecting unit selects a difference metric for a specific recorded sequence in recorded sequences obtained in a maximum likelihood decoding process when information expressed with marks and spaces on a recording medium is played back, the difference metric being obtained in the maximum likelihood decoding process. A difference metric error value calculating unit determines a difference metric error value for the selected difference metric using a calculation method that is selected according to an edge shift direction of each of the marks on a time axis, the difference metric error value representing an error from an ideal difference metric and the edge shift direction on the time axis. A statistical processing unit performs statistical processing on the determined difference metric error value on the basis of each of states of path meeting points to generate an evaluation value.

Abstract: To specify defect management information to be used in a short time in an information recording medium having a defect information area capable of recording plural sets of defect management information and a selection information area capable of recording plural sets of selection information for selecting a set of defect management information from the defect information area. The selection information includes information about a position where the latest management information at the time of writing is written, and history information indicating that the selection information is updated.

Abstract: Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function that is based on an address mapping which corresponds to an interleave inverse order of decoding processing (??1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function that is based on an mapping and the interleave (?) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (?) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

Abstract: A Viterbi detector includes a plurality of possible bit patterns that correspond to branches of a detector trellis and a plurality of data dependent noise prediction filters, with multiple filters of different orders being associated with a given bit pattern. A method of decoding includes applying observables to a Viterbi detector that associates a plurality of data dependent noise filters with a given possible bit pattern that corresponds to a branch of the detector trellis, calculating the composite maximum likelihood branch metric by incorporating the results of filtering the observables through the associated plurality of filters, calculating the composite maximum likelihood branch metrics in the same manner for other possible bit patterns, and so forth, and associating soft output values with detected bits in the observables based on the calculated branch metrics.

Abstract: Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

Abstract: Various aspects of a method for minimum mean square error soft interference cancellation (MMSE-SIC) based sub-optimal maximum likelihood (ML) detection for a multiple input multiple output (MIMO) wireless system may comprise selecting at least one constellation point in a constellation map based on at least one of a plurality of received symbols. A number of the at least one constellation point may be less than or equal to a number of previously selected constellation points in a previous constellation map. At least one of the plurality of received symbols may be decoded based on the selected at least one constellation point.

Abstract: In a nonvolatile memory system, data is read from a memory array and used to obtain likelihood values, which are then provided to a soft-input soft-output decoder. The soft-input soft-output decoder calculates output likelihood values from input likelihood values and from parity data that was previously added according to an encoding scheme.

Abstract: There is provided an addressing architecture for parallel processing of recursive data. A basic idea is to store a calculated new path metric at the memory location used by the old path metric, which old metric was employed to calculate the new metric. If m metric values are read and m metric values are simultaneously calculated in parallel, it is possible to store the new, calculated metrics in the memory position where the old metrics were held. This is advantageous, since the size of the storage area for the path metrics is reduced to half compared to the storage area employed in prior art Viterbi decoders for the same performance with regard to path metric computations.

Abstract: To read one or more flash memory cells, the threshold voltage of each cell is compared to at least one integral reference voltage and to at least one fractional reference voltage. Based on the comparisons, a respective estimated probability measure of each bit of an original bit pattern of each cell is calculated. This provides a plurality of estimated probability measures. Based at least in part on at least two of the estimated probability measures, respective original bit patterns of the cells are estimated. Preferably, the estimated probability measures are initial probability measures that are transformed to final probability measures under the constraint that the bit pattern(s) (collectively) is/are a member of a candidate set, e.g. a set of codewords.

Abstract: Aspects of a method and system for UMTS HSDPA Shared Control Channel processing may include calculating at a receiver, for each one of a plurality of control channels, a quality metric derived from at least one Viterbi Decoder state metric. A control channel may be selected on the basis of the quality metrics, where the quality metric is selected that provides maximum confidence. The selected control channel may be chosen if its corresponding 3GPP metric is greater than a specified threshold, where the threshold is a design parameter. A validity of a selected control channel may be determined based on consistency and a CRC, where the CRC may be derived from decoding a sub-frame. The calculating and selecting may be done for a first slot of a sub-frame for High-Speed Shared Control Channels.

Abstract: A dynamic power adjusting device for a Viterbi decoder is disclosed. The device includes a processing unit for receiving a plurality of data to be decoded, detecting whether the data to be decoded have any bit errors, and estimating a number of the bit errors of the data. The device further includes a control unit for receiving the bit errors and the number of the bit errors of the data detected by the processing unit, so as to enable the Viterbi decoder to perform decoding, and disable the Viterbi decoder after the Viterbi decoder has performed the decoding the number of times equivalent to the number of the bit errors. By way of the dynamic adjustment technique, coupled with the bit-error detection and estimation, workload of the Viterbi decoder in operation is capable of being adjusted according to bit error rate (BER) such that less power is consumed in a decoding process.

Abstract: In one or more embodiments, a method of processing a soft value sequence according to an iterative soft-input-soft-output (SISO) algorithm comprises carrying out sliding-window processing of the soft value sequence in a first iteration using first window placements and in a second iteration using second window placements, and varying the window placements between the first and second iterations. In at least one embodiment, a communication receiver circuit is configured to carry out iterative SISO processing, wherein it processes a soft value sequence using sliding windows, and wherein it varies window placements between one or more iterations. The communication receiver circuit comprises, for example, all or part of a turbo decoding circuit or other type of iterative block decoding circuit, an equalization and decoding circuit, a soft demodulation and decoding circuit, a multi-user detection and decoding circuit, or a multiple-input-multiple-output detection and decoding circuit.

Abstract: In a nonvolatile memory system a Soft-Input Soft-Output (SISO) decoder corrects errors in data that is read from a memory and a statistical unit connected to the SISO decoder collects data regarding corrections. The statistical unit generates at least one output based on the collected data and at least one operating parameter of the memory is modified in response to the output.

Abstract: Systems and methods for generating likelihood metrics for trellis-based detection and/or decoding are described. In some embodiments, likelihood metrics for a first subset of bit locations in an error pattern (e.g., bit locations that fall within the error event update window) are updated based on a first metric, such as the path metric difference, associated with an alternate path that converges to the same trellis state as the decoded sequence. In some embodiments, likelihood metrics for a second subset of bit locations in the error patterns (e.g., bit locations that do not fall within the error event update window) are updated based on a second metric, such as a predetermined value of zero, a small metric, or the path metric difference for a path that does not converge into the same winning state as the decoded sequence for the particular error update window of interest.

Abstract: A non-linear post-processor for estimating at least one source of signal-dependent noise is disclosed. The post processor may receive a set of preliminary decisions from a sub-optimal detector along with the sampled data signal. The post-processor may then compute the transition jitter and white noise associated with each preliminary decision in the set and assign a cost metric to each decision based on the total signal noise. The post-processor may output the decision with the lowest cost metric as the final decision of the detector.

Abstract: The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; a second convolutional code encoder; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutational interleaver and the second outputting means.

Abstract: An iterative decoder includes at respective variable nodes, that is, at nodes that correspond to the bits of the code word, bit error detectors that after convergence determine if the respective hard decision bit values have changed from the bit values provided by the channel. The change in value for a given bit indicates that a bit error has been corrected. The bit error detector, for message-passing decoders that perform calculations by addition rather than multiplication, can be readily implemented as an XOR gate. Thus, a bit error is detected at the variable node by XOR'ing the sign bits of the input symbol and the variable node sum. After convergence, the output values produced by the bit error detectors at the respective variable nodes are added together using an adder tree that accumulates the detected bit errors for an entire date block, or ECC code word.

Abstract: Encoded symbols of a concatenated convolutional-encoded and block encoded signal are presented to a conventional first stage of a concatenated decoder, comprising in sequence a soft metric generator, a Viterbi decoder, a first de-interleaver and a first block decoder such as a Reed-Solomon decoder. The encoded symbols are also presented to a delay chain to produce progressively delayed encoded symbols. Where an output block of the conventional decoder is indicated as being a valid codeword by the first block decoder, the bytes in this block are marked as being correct. These bytes that are known to be correct are then used after interleaving and serialization as known bits input to a second stage of the decoder process operating on the delayed encoded symbols and incorporating a modified soft metric generator constrained by the known bits. This process can be extended to further iterations as required.

Abstract: The present invention relates to an iterative decoding receiver for reducing complexity of a partial sphere decoding operation in a spatial multiplexing system, and a method thereof. In the present invention, an iterative detection and decoding (IDD) method using a cost function-based iterative partial sphere decoding method and a soft cancellation-based iterative partial sphere decoding method is used to correct an initial estimation error. In a channel encoding spatial multiplexing system, since the iterative decoding receiver using decoding algorithms including a BCJR algorithm, an MPA, and a VA performs an SISO sphere decoding operation providing an optimum detection solution, the iterative decoding receiver may detect transmission symbols at a whole dimension by detecting the transmission symbols at a partial dimension, and therefore the complexity of the SISO sphere decoding operation may be greatly reduced.

Abstract: A decoding device which performs error correction decoding of encoded data formed from a combination of an outer code for first error correction and an inner code for second error correction is disclosed. The decoding device has: a demodulator for creating a data series of likelihood information values; a second error correction decoder for creating a hard decision value series by executing repetitive decoding for the second error correction based on the likelihood information values; and a first error correction decoder for detecting a lost bit in the hard decision value series and creating an erasure flag indicating the position of the detected lost bit.

Abstract: In a digital system using a turbo code, a method for performing iterative decoding in accordance with a Log-MAP Algorithm comprises the steps of:—generating a look-up table comprising a plurality of values representative of a correcting factor;—performing a first calculation to obtain a forward metric;—performing a second calculation to obtain a backward metric;—performing a third calculation to obtain a log-likelihood ratio for every information bit to be decoded. In accordance with the method, at least one and no more than two of such calculations are performed by the use of said look-up table for implementing the Log-MAP decoding algorithm and the remaining calculations are performed implementing a Max-Log-MAP decoding algorithm.

Abstract: Serial concatenated trellis coded modulation (SCTCM) includes an outer coder, an interleaver, a recursive inner coder and a mapping element. The outer coder receives data to be coded and produces outer coded data. The interleaver permutes the outer coded data to produce interleaved data. The recursive inner coder codes the interleaved data to produce inner coded data. The mapping element maps the inner coded data to a symbol. The recursive inner coder has a structure which facilitates iterative decoding of the symbols at a decoder system. The recursive inner coder and the mapping element are selected to maximize the effective free Euclidean distance of a trellis coded modulator formed from the recursive inner coder and the mapping element. The decoder system includes a demodulation unit, an inner SISO (soft-input soft-output) decoder, a deinterleaver, an outer SISO decoder, and an interleaver.

Abstract: When a convolution code is decoded, electric power consumption is suppressed keeping error correction capability. In a Viterbi decoder which decodes received signal, a convolution code, having plural series with a soft decision Viterbi decoding method, an estimation control unit estimates quality of the received signal and outputs a control signal according to the quality to a branch metric calculation data obtaining unit. The branch metric calculation data obtaining unit performs logical combination operation between digital multi-value data expressing amplitude of the received signal and the control signal, and thereby, outputs the digital multi-value data directly to a decoding execution unit if the quality of the received signal is lower than a prescribed level, and outputs the digital multi-value data reduced by series each as branch metric calculation data to the decoding execution unit if the quality of the received signal is no less than the prescribed level.

Abstract: In a maximum likelihood decoder, when undersampling occurs, selectors 205 to 207 do not select branch metrics from branch metric calculation sections 202 to 204 but select a value “0”, and a path metric calculation section 208 calculates a path metric based on the value “0” selected by the selectors 205 to 207, while calculating a path selection signal. An input signal wsdt_d, which is input to the branch metric calculation sections 202 to 204 and which is subjected to maximum likelihood decoding, is adjusted, with consideration given to the time of the occurrence of the undersampling at which the selectors 205 to 207 select the value “0”, so as to be a signal delayed by the number of clocks corresponding to that occurrence time. Thus, correct decoding results are obtainable even when the undersampling occurs, thereby ensuring proper operation.

Abstract: A turbo decoder iteratively decodes a received, encoded signal with one or more constituent decoders employing a simplified log-maximum a posteriori (SMAP) decoding algorithm. The SMAP decoding algorithm calculates reliability information as a log likelihood ratio for a log-MAP algorithm using a reduced set of path metrics recursively updated based on maximum likelihood recursion. Updated extrinsic information for a subsequent decoding may be derived from the LLR calculated by the SMAP decoding algorithm.

Abstract: A MIMO receiver implements a method for the soft bit metric calculation with linear MIMO detection for LDPC codes, after linear matrix inversion MIMO detection. In the receiver, a detector detects the estimated symbol and the noise variance. Further, a soft metric calculation unit computes the distance between the estimated symbol and the constellation point, and then divides the distance by the noise variance to determine the soft bit metrics.

Abstract: A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding binary and duo-binary code. The reconfigurable MAP calculation circuit comprises M memory banks for storing N input data samples. Each input data sample comprises systematic data, non-interleaved parity data and interleaved parity data. The N input data samples are divided into M logical blocks and input data samples from each logical block are stored in each of the M memory banks. The reconfigurable MAP calculation circuit comprises M processing units. Each processing unit processes one of the M logical blocks. The reconfigurable MAP calculation circuit comprises a communication switch for coupling the M processing units to the M memory banks such that the M processing units simultaneously access input data samples from each of the M logical blocks in each of the M memory banks without collision.

Abstract: In one embodiment a wireless communication device is provided that: acquires a phase rotation angle in the propagation channel which phase rotation angle is contained in a received symbol and that performs rotation compensation of the acquired phase rotation angle for the received symbol; generates a coordinate value of the respective I, Q axis in the signal constellation on which the information of the respective reference signal point is set; for the respective transmission bit, obtains respective probabilities that the transmission bit is 0 and 1 by making a distance determination of the distance between the received symbol after the rotation compensation and the respective reference signal level on only one of the I and Q axes; and makes a likelihood determination of the bit value of the respective transmission bit in accordance with a probability value obtained.

Abstract: A method for selecting a signal to noise ratio for a communications code includes obtaining extrinsic information transfer (EXIT) information for a repeat-zigzag Hadamard (RZH) code responsive to a Hadamard order and a signal to noise ratio, determining code parameters for an irregular repeat zigzag Hadamard (IRZH) code for a corresponding code rate in response to the obtained EXIT values, and repeating the step of obtaining the EXIT information for a different signal to noise ratio if the corresponding code rate is other than a selected rate. The corresponding code rate is related to a bit error rate. In a preferred embodiment, the step of obtaining EXIT information includes one of obtaining an EXIT curve for repeat-zigzag Hadamard code by Monte Carlo simulation using serial decoding or obtaining an EXIT function for parallel decoding of the repeat-zigzag Hadamard code by using equations.

Abstract: The disclosed technology provides a less resource intensive way to decode a parity check code using a modified min-sum algorithm. For a particular parity check constraint that includes n variable nodes, an LDPC decoder can compute soft information for one of the variable nodes based on combinations of soft information from other variable nodes, wherein each combination includes soft information from at most a number d of other variable nodes. In one embodiment, soft information from one of the other variable nodes is used in a combination only if it corresponds to a non-most-likely value for the other variable node.

Abstract: A detector includes a Viterbi based detector and an erasure detector that detects as erasures one or more bits associated with a decoding window in which survivor paths do not merge within the decoding window.

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors.

Abstract: A soft output decoder capable of performing decoding with a small computational complexity necessary for likelihood calculation thereby to reduce the scale of the operation circuit and to shorten the processing delay time. The soft output decoder (100) comprises a &ggr;? calculating section (101), timing adjusters (102, 103), a &ggr;? calculation section (104), and a &Lgr; calculating unit (110). The &Lgr; calculating unit (110) is composed of a hard decision decoding section (111), a loss likelihood calculating section (112), a win likelihood storage section (113), and a subtractor (114). The likelihoods determined by a Max-log-MAP decoder are separated into win likelihoods and loss likelihoods, and only the loss likelihoods are calculated. A hard decision decoding section (111) for sequentially specifying the states through which the maximum likelihood path passes is used for a method for distinguishing the win and loss likelihoods.

Abstract: Hypothesis tests, such as maximum likelihood detections, are executed on symbol sequences received by, for example, a user equipment (UE) in a communication system. The hypothesis tester checks a received sequence against a group of predetermined sequences that possibly could have been sent to the UE. For received sequences that are matched or not matched by the hypothesis tester with high confidence, complete decoding, for example, with a Viterbi decoder, is not necessary. Instead, complete decoding is used as a “tie-breaker” for those sequences which the hypothesis tester cannot match or not match with desired confidence levels.