Abstract: A method for providing wireless communications between a locomotive control unit (LCU) (14) on board a locomotive (16) and a portable operator control unit (OCU) (12) for use in controlling operation of the locomotive from an off-board location includes calculating a transmit bit error check value for a wireless message. The wireless message includes an explicit sequence number assigned to the message so that the explicit sequence number is implicitly encoded in the transmit bit error check value. The method also includes transmitting an encoded message between the OCU and the LCU with the transmit bit error check value and without the explicit sequence number effective to reduce a total amount information needed to be transmitted compared to a message including the explicit sequence number.

Abstract: A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.

Abstract: An apparatus, a carrier medium storing instructions to implement a method, and a method in a node of a wireless network able to receive packets that exactly or substantially conform to a wireless network standard according to which each packet includes a header having bits that have respective correct values in the case that the packet exactly conforms to the standard. The method includes receiving a start-of-packet (SOP) trigger that indicates that a packet may have been received, checking one or more bits in the header to determine whether or not they have their respective correct values, and continuing to process the packet in the case that the checking indicates that the checked bits have their respective correct values. In one implementation, the header includes a first field modulated at a known rate that has one or more reserved bit locations, and a second field modulated at a data rate indicated in the first field.

Abstract: Specific bits of an incoming transmission are compared against a predetermined bit pattern. If the selected bits do not match the predetermined bit pattern, then the incoming transmission is rejected as a false packet. The predetermined bit pattern can include legal values for predetermined bits in a plurality of fields. Notably, these legal values are set by a networking standard. A parity check may check may be performed in addition to checking for predetermined bits in other fields. A user interface can be used to determine the predetermined bit pattern.

Abstract: A method for efficiently detecting bus contention from a register transfer level (RTL) description is provided. A bus contention occurs if more than two components try to propagate data onto a bus at the same time. The provided method simulates possible input combinations and detects whether there is a possibility for a bus contention. In addition, the provided method is designed for testability, therefore using the method, the designer may identify contention that may exist in test mode at the RTL level of the design even when such conditions may not occur in system mode. The method provides the designer with the input combination as well as the RTL statement that caused the contention. The method detects the bus contention by simulating a small number of input combinations.

Abstract: A method and apparatus are provided for detecting a receiver over a PCI-Express bus. A receiver is detected on a PCI-Express link by adjusting a common mode voltage using a current injected into one or more transmitter output nodes and detecting whether a receiver is present based on a voltage change rate. The current can be injected, for example, by a charge pump. In various embodiments, the charge pump can be integrated with a CML transmit buffer or an H-bridge type of transmit buffer. The amplitude control circuit can compare the adjusted common mode voltage to one or more predefined voltages and maintain the adjusted common mode voltage between two predefined voltages. The amplitude control circuit provides a signal to the charge pump to control the current injected into the transmitter output nodes. The amplitude control circuit also provides a signal to an exemplary timer that measures the voltage change rate.

Abstract: An apparatus, a carrier medium storing instructions to implement a method, and a method in a node of a wireless network able to receive packets that exactly or substantially conform to a wireless network standard according to which each packet includes a header having bits that have respective correct values in the case that the packet exactly conforms to the standard. The method includes receiving a start-of-packet (SOP) trigger that indicates that a packet may have been received, checking one or more bits in the header to determine whether or not they have their respective correct values, and continuing to process the packet in the case that the checking indicates that the checked bits have their respective correct values. In one implementation, the header includes a first field modulated at a known rate that has one or more reserved bit locations, and a second field modulated at a data rate indicated in the first field.

Abstract: Disclosed is a method of validating a byte sequence having a plurality of states, the method comprising designating one or more noise states from among the plurality of states; generating a most probable state sequence for the byte sequence; utilizing said state sequence to identify all noise in the byte sequence; and localizing said noise in said noise states. Once localized, the noise may be deleted from the byte sequence.

Abstract: A D/A converter has a serial interface. Of the sets of the data representing multiple control signals output from latch circuits, the data representing input data, the data representing strobe signal, and the data representing clock signal are supplied to the D/A converter. A mask circuit is provided in the path supplying the strobe signal. When a parity detection circuit detects a transmission error, the mask circuit masks the strobe signal to be supplied to the D/A converter, thereby preventing the D/A converter from outputting an analog output signal corresponding to the input data.

Abstract: A method of performing a modified RLP that reduces the transmission delay in a communications system by detecting frame erasures when they occur. The modified RLP method requests retransmission of erased frames based on pattern violations instead of sequence number violations. The method is preconditioned to expect a particular repeating pattern of frame delivery. For a system running a VSELP vocoder, the method in a receiving device expects to receive full rate or data (F) and DTX (D) frames in a repeating pattern FFDFFDFFD. For a system running an AMBE vocoder, the method in a receiving device expects to receive frames in a repeating pattern DFDFDFDD. The method detects when the pattern is violated and in desired instances immediately requests retransmission of the expected frame.

Abstract: A method and program product for verifying a logic design for proper operation of tri-state buses in the design, comprises, for each bus in the circuit design, determining the smallest cut set, a min-cut, of the logic controlling the bus, performing an exhaustive analysis on a min-cut set of logic, and performing a full exhaustive analysis of the bus when the exhaustive analysis on the min-cut set of logic is inconclusive. In a preferred embodiment, prior to performing the min-cut set analysis, implication based conflict-free and float-free analyses are performed on the bus.

Abstract: A unit test signal having duration T is repeatedly supplied from an LSI tester to an IC under test and, simultaneously, a power source current is supplied from the LSI tester through a current detection unit to the IC under test. The power source current is monitored by the current detection unit and a current information obtained by the monitoring is analyzed by a spectrum analyzer unit. Since the repetition period of the test signal is T, the power source current having a period nT flows through the IC under test along with a state shift of the IC under test, where n is an integer. When the IC under test has a fault, the power source current flows with a period n′T, where n′ is an integer different from n, or an abnormal power source current flows with the period nT, due to a change of the state shift of the IC under test.

Abstract: Method and system for compensating for a segment length of one or more of three consecutive mark and space segments utilized in a computer system. The three segments are received at a first pre-processor, the first segment is separated and issued separately from the remaining two segments, and the first segment length is compared with a permitted range of lengths. If the first segment length is not within the permitted range, a first error signal is issued, preferably indicating the non-complying first length. This process is repeated at second and third pre-processors. A segment processor receives the three individual segments and the error signals and non-complying lengths, if any, and compensates or corrects for any non-complying segment lengths before further processing occurs.

Abstract: A flexible method of error coding uses at least two generating polynomials to provide different degrees of error protection and to optionally superimpose a phantom channel on a primary channel, without the need for explicit signaling from transmitter to receiver. An encoded message is CRC decoded the on the receive side with at least two different generating polynomials. Based on the results of the twin decoding, the present method can determine which of the generating polynomials was used to encode the message and respond accordingly. For instance, if the a particular generating polynomial was used, then this may be use to indicate that a second channel has been superimposed onto the primary channel and that second channel may be extracted. On the other hand, if another generating polynomial, such as the default generating polynomial, was used, this may be used to indicate that no second channel has been superimposed.

Abstract: Improved error screening techniques are used in processing digital audio or other types of information received in a digital communication system. Control information associated with a given packet of the received information is identified and compared with a decoding requirement of the packet, in order to control the generation of an error indicator for the packet. More particularly, the error indicator may be generated in response to an inconsistency between the control information and the decoding requirement. For example, the control information may include an indication of packet length that can be compared to a number of bits required to decode the corresponding packet, with any inconsistency between the packet length indication and the number of required bits leading to the generation of an error flag for the packet.

Abstract: A phase-locked loop (PLL) is tested based on a divide-and-conquer strategy. First, digital components in the PLL are isolated from analog components and tested. Next, the digital components are connected to the analog components and the PLL is exercised by causing it to undergo a series of frequency transitions.

Abstract: Disclosed is an apparatus and method for detecting errors in one-hot words, which have only a single bit set in the absence of errors. The apparatus comprises a plurality of input signal lines, a plurality of switching devices, a plurality of intermediate signal lines, and logic circuitry. The switching devices are connected to the input signal lines. The intermediate signal lines are also connected to the switching devices. The connection is in such a way that when a particular input signal line is set, all intermediate signal lines connected by a switching device to that particular input signal line are forced to a predetermined logic state. The intermediate signal lines are input to the logic circuitry, which outputs a signal indicative of whether at least two of the plurality of input signal lines are set. The method detects non-one-hot conditions in a group of M bits.

Abstract: Methods and systems for fault location are described. In one described embodiment, an “in circuit” solution is provided for locating faults along a passive transmission line. Once a fault occurs, various hardware gathers information that is necessary to determine which of a number of different replaceable components has failed. This enables the subsystem to properly respond to the fault condition and thereby eliminate any guessing that could potentially lead to loss of data availability. In the particular described embodiment, signals are driven and received through a selected input/output (I/O) pad. Logic circuitry is provided and launches a wave onto the passive transmission line. Immediately following the launching of the wave, the I/O pad is monitored and can sense the reflections from the wave that has just been launched. By analyzing the reflections, and more specifically the time that it takes for the reflection to be sensed, a determination is made as to the fault location.

Abstract: Device and method of EEPR4 post processing in an EPR4 detection system to remove single bit errors by applying 1+D to the samples and comparing this to (1−D)(1+D)3 to the detected EPR4 bits.

Abstract: An application specific integrated circuit includes a clock recovery circuit which recovers from an input signal a repetitive sequence of data values wherein no two consecutive values are the same and a recovered clock. An address generator responds to the recovered clock to cause storage of the data values in said memory in a set of locations having addresses generated by the address generator, so that the address generated by the generator increments in response to a repetitive transition in the recovered clock. The existence of a clock glitch is found by reading the data values from the set of locations to determine whether any two consecutive locations contain the same data value.

Abstract: A method of debugging a system by analyzing transactions of a serial intra-system bus is particularly applicable to IIC or SPI intra-system busses. The method includes steps of capturing frames of the bus in a capture data file, extracting frames from the capture data file; checking frames for out-of-bounds addresses; and decoding an address of frames to identify a particular slave device type. Once a particular device type is identified, state changes indicated in frames are tracked with a computer model of the slave device; and state error information is recorded when frames indicate state changes that are not permissible state changes of the slave device.

Abstract: A communication device and method for electronic price label (EPL) systems which use EPL components. The device includes a microcontroller, a first EPL circuit enabled by the microcontroller which sends a first signal to an EPL computer in response to a first polling signal from the EPL computer indicating that data from the microcontroller is ready for transmission, a number of second EPL circuits which store the data from the microcontroller and which send the data to the EPL computer in response to a second polling signal from the EPL computer, a third EPL circuit which receives a second signal from the EPL computer acknowledging receipt by the EPL computer of the data, and which signals the microcontroller of the receipt of the data, a keypad coupled to the microcontroller for recording the data from an operator, and a display for displaying the data as it is recorded and for displaying an indication of the receipt of the data.

Abstract: A method and apparatus for detecting and mapping digital errors on optical media is provided which includes an invalid symbol detector capable of detecting errors in real time. The method and apparatus further includes the ability to set a run-length mask enabling selective display of specific run-lengths. The method and apparatus of error mapping enables the detection of errors at the time that the data is read and before the data is processed by traditional error detection and correction circuits. Capturing the errors relative to their physical location on the optical media allows the creation of an error map or surface presentation of the errors. The resulting error map displays the location and magnitude of digital errors caused by invalid symbols. The error map allows the test operator to quickly determine the specific location and or distribution of errors on the optical media.

Abstract: A method and program product for verifying a logic design for proper operation of tri-state buses in the design, comprises, for each bus in the circuit design, determining the smallest cut set, a min-cut, of the logic controlling the bus, performing an exhaustive analysis on a min-cut set of logic, and performing a full exhaustive analysis of the bus when the exhaustive analysis on the min-cut set of logic is inconclusive. In a preferred embodiment, prior to performing the min-cut set analysis, implication based conflict-free and float-free analyses are performed on the bus.

Abstract: Method and apparatus for image transmission using arithmetic coding, based on continuous error detection uses a controlled amount of added redundancy. A continuous error detection scheme is provided, wherein there is a trade-off between the amount of added redundancy and the time needed to detect an error once it occurs. Herein, there is no need for the cyclic redundancy check (CRC) to wait until an entire block of data has been received and processed before an error can be detected. The invention can be used to great advantage both in the automatic repeat request (ARQ) and other concatenated coding schemes. Errors in the received bit stream are detected by introducing added redundancy, e.g., a forbidden symbol, in the arithmetic coding operation. The forbidden symbol is never intended to be encoded. The redundancy error causes loss of synchronization, which is used to detect errors. If a forbidden symbol gets decoded, it means that an error has occurred.

Abstract: A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal.

Abstract: A communication device and method for electronic price label (EPL) systems which use EPL components. The device includes a microcontroller, a first EPL circuit enabled by the microcontroller which sends a first signal to an EPL computer in response to a first polling signal from the EPL computer indicating that data from the microcontroller is ready for transmission, a number of second EPL circuits which store the data from the microcontroller and which send the data to the EPL computer in response to a second polling signal from the EPL computer, a third EPL circuit which receives a second signal from the EPL computer acknowledging receipt by the EPL computer of the data, and which signals the microcontroller of the receipt of the data, a keypad coupled to the microcontroller for recording the data from an operator, and a display for displaying the data as it is recorded and for displaying an indication of the receipt of the data.

Abstract: A chip testing system using an internal signal of the chip under test to produce a blanking signal so as to avoid a conflict in the turn-around cycle between input mode and output mode. The preceding signal, posterior signal and reverse phase signal of the output enable signal of the chip under test are used to match with a testing circuit for producing a blanking signal, which is driven only when the output enable signal is at a high potential, enabling the state machine in the chip to control data reading time, so as to avoid a conflict in the turn-around cycle between input mode and output mode.

Abstract: A communication device and method for electronic price label (EPL) systems which use EPL components. The device includes a microcontroller, a first EPL circuit enabled by the microcontroller which sends a first signal to an EPL computer in response to a first polling signal from the EPL computer indicating that data from the microcontroller is ready for transmission, a number of second EPL circuits which store the data from the microcontroller and which send the data to the EPL computer in response to a second polling signal from the EPL computer, a third EPL circuit which receives a second signal from the EPL computer acknowledging receipt by the EPL computer of the data, and which signals the microcontroller of the receipt of the data, a keypad coupled to the microcontroller for recording the data from an operator, and a display for displaying the data as it is recorded and for displaying an indication of the receipt of the data.

Abstract: A method and system for packet-switched flow control of transaction requests that maximizes resource utilization and throughput, and minimizes latency. A system controller provides dedicated transaction request queues and controls the forwarding of transactions from a processor to a slave. The transaction requests are automatically forwarded to an intended slave on the same address bus as the system controller immediately. The system controller determines whether the proper criteria are met for that slave to receive such a request, such as the slave's request receive queue is not full and that global ordering requirements are met. If so, then on a separately provided line, the system controller validates the request for immediate reception by the slave.

Abstract: In a communication system wherein a collecting communication unit of a plurality of communication units collects state information from report communication units to manage the state information, each of the report communication units comprises a state information memory for storing the state information of own communication unit, a state monitoring portion for monitoring the state information of own communication unit and then rewriting the stored state information into new state information after change if the state information has been changed, and a transmitting/receiving portion for adding the stored state information and own address to the recovery command and then transmitting the recovery command when respective report communication units receive the recovery command for recovering the state information, whereby the collecting communication unit can receive the recovery command to which changed state information and their own addresses of respective report communication units are added collectively.

Abstract: Any of several information processing techniques may be used in various information storage and transmission applications to prevent the occurrence of certain “forbidden” bit patterns. According to an encoding technique, a reversible coding process is used to generate an encoded representation of an information stream that cannot contain any forbidden data patterns. This may be accomplished by partitioning the information stream into segments and encoding each segment according to a respective encoding key that is selected such that the results of the coding process cannot contain a forbidden data pattern. According to one substitution technique, all occurrences of forbidden data patterns are replaced with permissible data patterns that do not otherwise occur in the information stream.

Abstract: When manufactured, an optical data carrier is provided with digital information, which is written and stored in accordance with at least one previously defined encoding method for error correction and which may be read and decoded at a later stage by means of an optical reader with correction of errors in accordance with said encoding method. A predetermined number of logical symbols or bits are selected at predetermined positions in the digital information to be stored on the data carrier. A set of logical errors are intentionally created by replacing the selected symbols with corresponding symbols in a predetermined code sequence representing the identity of the data carrier. The logical errors are of such a type as to be normally corrected by the optical reader, when the data carrier is read and/or copied.

Abstract: The present invention relates to a circuit of reception of bits transmitted on an asynchronous signal, including a circuit for providing a clock reconstructed from the asynchronous signal, this clock being used to sample the asynchronous signal to form a synchronous output signal, and a reception error detection circuit. The reception error detection circuit includes an edge detector providing a detection pulse for each edge of predetermined direction of the asynchronous signal; and an alarm circuit activating an alarm signal when an edge of predetermined direction of the synchronous signal occurs outside a detection pulse.

Abstract: A system for detecting an initialization flag signal and distinguishing it from a normal flag signal having half the duration of the initialization flag signal. The initialization flag detection system may be included in the command buffer of a packetized DRAM that is used in a computer system. In one embodiment, the initialization flag detection system includes a pair of shift registers receiving the flag signal at their respective data inputs. One of the shift registers is clocked by a signal corresponding to an externally applied to command clock signal, while the other shift register is clocked by a quadrature clock signal. Together, the shift registers store a number of samples taken over a duration that is longer than the duration of the normal flag signal. The outputs of the shift registers are applied to a logic circuit, such as a NAND gate, that generates an initialization signal when all of the samples stored in the shift registers correspond to the logic levels of the flag signal.

Abstract: A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.

Abstract: A reconfigurable circuit wherein part or all of an instruction or a result of decoding thereof and output of said register file are inputted and a circuit structure thereof can be changed by an external signal is provided. If a bug occurs when part or all of the instruction or the result of decoding thereof and the output of the register file satisfy a particular condition, the reconfigurable circuit is reconstructed by an external signal so as to output a first signal under that particular condition. An interrupt control circuit controls a processing unit so as to carry out processing based on the first signal or processing to avoid the bug when the first signal is inputted.

Abstract: Highly efficient, enhanced RLL and MTR constrained or modulation codes and a unified methodology for generating the same. The new codes also include partial error detection (PED) capability. RLL/PED code rates of 8/9, 16/17, 24/25 and 32/33 or higher are disclosed. The new generalized RLL/PED block coding schemes are derived with fixed length n: n/(n+1)(d=0, k=n-1/l=n), n/n+1(0,[n/2]/l=n+4) and m/(n+1)(d=0, k=[n/2]/l=n) for n.gtoreq.5 (where [ ]denotes the enteger part of the argument). The codes n/(n+1)(0,[n/2]/l=n+4) are also shown in a concatenated ECC/modulation architecture, where the modulation decoder, capable of detecting bits in error, generates symbol byte erasures to boost the performance of the outer ECC decoder.

Abstract: An energy efficient remote control protocol uses a start bit which has a variable length which corresponds to the parity of the transmitted symbol, a guard time which is fixed at a predetermined length, and a data transmission time which corresponds to the data to be transmitted. The data to be transmitted is transmitted as a logic low, thus improving the energy efficiency of the system. During the transmission of a code, only one stop bit is used at the end of the transmission. The guard time and parity check are used to verify proper transmission.