Abstract: Aggregation of coverage data for a design-under-test (DUT) can be performed using a coverage testbench without running any simulations on the DUT. Stimulus data that was used previously for performing different simulations on the DUT can be saved in a database. The coverage testbench can read the saved stimulus data and aggregate the coverage data from the stimulus data using a coverage model. When the DUT is updated, the coverage model can be updated, and updated coverage data can be collected using the coverage testbench without re-running the simulations on the DUT.

Abstract: A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the sub-circuit, and performing a simulation or a formal verification of the optimized HDL output file to determine whether a signal associated with the net glitches.

Abstract: A process is disclosed to identify the minimal set of sequential and combinational signals needed to fully reconstruct the combinational layout after emulation is complete. A minimal subset of sequential and combinational elements is output from the emulator to maximize the emulator speed and limit the utilization of emulator resources, e.g., FPGA resources. An efficient reconstruction of combinational waveforms or SAIF data is performed using a parallel computing grid.

Abstract: A method for testing a system under test (SUT) in an active environment includes generating, by a testing system, several tests for testing the SUT. The tests are generated based on a coverage model of the SUT, which includes multiple attributes. The method further includes creating, by the testing system, a minimal set of tests from the tests by selecting tests that do not exceed a predetermined performance threshold. The method further includes executing, by the testing system, the minimal set of tests on the SUT for analyzing a soft failure of the SUT in the active environment. The soft failure occurs in the active environment during execution of the SUT based at least in part on a performance parameter of the active environment.

Abstract: A method for testing a system under test (SUT) in an active environment includes generating, by a testing system, a set of tests for testing the SUT, the tests generated based on a coverage model of the SUT, wherein the coverage model uses several attributes. The method further includes creating, by the testing system, a minimal set of tests from the generated tests by selecting tests for a disjoint set of attributes from the several attributes of the coverage model. The method further includes executing, by the testing system, the minimal set of tests on the SUT for analyzing a soft failure of the SUT in the active environment, wherein the soft failure occurs in the active environment during execution of the SUT based at least in part on a parameter of the active environment.

Abstract: Methods and example implementations described herein are generally directed to a System on Chip (SoC) design and verification system and method that constructs SoC from functional building blocks circuits while concurrently taking into account numerous chip level design aspects along with the generation of a simulation environment for design verification. An aspect of the present disclosure relates to a method for generating a System on Chip (SoC) from a floor plan having one or more integration descriptions. The method includes the steps of generating one or more connections between the integration descriptions of the floor plan based at least on a traffic specification, and conducting a design check process on the floor plan. If the design check process on the floor plan is indicative of passing the design check process, then the method generates the SoC according to the one or more connections generated between the integration descriptions.

Abstract: A fault monitoring and management method that collects readings from hardware components and software functions to deduce the source of a system failure by utilizing a system representation method based on directed graphs. The presented method utilizes a system description that establishes absolute dependence, which means that the failure of a component leads to certain failure of the successor components that depend on the output of the failed component, between system or process elements. The change in the system behaviour upon the failure of each system element is automatically determined by algorithms that process the graph depiction of the system architecture.

Abstract: A simulation apparatus includes: a factor amount converting information storage unit in which factor amount converting information, which is information indicating correspondence between low-fidelity information and high-fidelity information, is stored; a writing pattern information storage unit in which writing pattern information is stored; an ADI simulation unit that performs an ADI simulation using one or more evaluation points, for a writing pattern indicated by the writing pattern information, thereby acquiring one or more factor amounts; a converting unit that acquires high-fidelity information, which is one or more factor amounts, corresponding to the low-fidelity information, which is one or more factor amounts, using the factor amount converting information; and an etching simulation unit that performs an etching simulation using the one or more factor amounts acquired by the converting unit.

Abstract: An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.

Abstract: Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.

Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.

Abstract: A complete, unified material-to-systems simulation, design, and verification method for semiconductor design and manufacturing may include evaluating effects of semiconductor material or process changes on software algorithms. The method may include translating the material or process change into a database of characteristics; generating primitive circuit structures using the database of characteristics; performing an electrical characterization of the primitive circuit structures; providing an output of the electrical characterization to a script to generate compact models; generating a lite version of standard cells; generating a digital system based on the lite version of the standard cells; and evaluating a performance of a software algorithm on the digital system to determine an effect of the material or process change for the semiconductor manufacturing process.

Abstract: Disclosed is a high-linearity low-voltage input buffer circuit. The buffer circuit includes main buffers of positive and negative input terminals comprised of NMOS transistor MN1 and MN3 as well as MN2 and MN6, auxiliary buffer comprised of PMOS transistors MP1 and MP3 as well as MP2 and MP4, replica current amplifier comprised of NMOS transistors MN3 and MN4 as well as MN5 and MN6. Two ends of a replica capacitor Cc are respectively connected with positive and negative output terminals of the auxiliary buffer. The auxiliary buffer is used to simulate a load effect of the main buffers to generate a replica current of a load current, then the replica current is mirrored to a load transistor of the main buffer by the current amplifier, and the load capacitor is charged and discharged through the load transistor.

Abstract: A method to provide an automated circuit design tool that mitigates or overcomes the inefficiencies present in the prior art tools ensuring a more efficient use of computer resources and a reduction in the time taken to design a suitable circuit that meets the design specification is presented. The computer-implemented method of designing a circuit configuration of a circuit, has the following steps 1) providing a first set of circuit configurations comprising one or more circuit configurations, 2) simulating each, circuit configuration of the first set of circuit configurations. In addition, the steps include: 3) scoring each, circuit configuration of the first set of circuit configurations based on a design specification and the simulation, or simulations, of step 2), and 4) providing a second set of circuit configurations comprising one or more circuit configurations that are dependent on the scores as determined in step 3).

Abstract: A system and method for SAT-sweeping is disclosed. According to one embodiment, a method includes determining gate classes by inputting simulation patterns to gates in an integrated circuit design, selecting a candidate gate based on an inverse topological ordering of the gates, and then selecting a driver gate belonging to the same gate class as the candidate gate. A SAT-solver is called based on the candidate gate and the driver gate to confirm equivalence. The candidate gate and the driver gate are then merged in the integrated circuit design.

Abstract: A method for evaluating a heat sensitive structure involving identifying a heat sensitive structure in an integrated circuit design layout, the heat sensitive structure characterized by a nominal temperature, identifying a heat generating structure within a thermal coupling range of the heat sensitive structure, calculating an operating temperature of the first heat generating structure; calculating a temperature increase or the heat sensitive structure induced by thermal coupling to the heat generating structure at the operating temperature; and performing an electromigration (EM) analysis of the heat sensitive structure at an evaluation temperature obtained by adjusting the nominal temperature by the temperature increase induced by the heat generating structure.

Abstract: In a simulation device (100), a calculation section (113) calculates an execution processing time required for executing each instruction code (221) of a plurality of instruction codes. A storage section (140) stores change setting information (230) in which a change rule that changes execution processing times of the plurality of instruction codes included in the processing unit is set. A change section (115) changes the execution processing time into a changed processing time according to the change rule being set in the change setting information (230). The change section (115) also includes the changed processing time of each instruction code of the plurality of instruction codes, in an entire time point (240). A simulation execution section (116) executes a simulation of a target program (210) using the entire time point (240). A monitoring section (120) monitors a status of a target model during execution of the simulation.

Abstract: A method of generating an integrated circuit includes: placing a plurality of electronic components on a layout floor plan to generate a placing layout of the integrated circuit; forming a clock tree upon the placing layout to generate a synthesis layout of the integrated circuit; routing the synthesis layout to generate a routed layout of the integrated circuit; performing a DRC process upon the routed layout to obtain a layout region with a systematic DRC violation; generating a plurality of prediction gains of the layout region according to a plurality of placement recipes respectively; and generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in the plurality of placement recipes.

Abstract: A method and system for improved design verification for a data processing device when performing a logic simulation. The system identifies certain corresponding coverpoints at different points in results of a logic simulation for a design. Using coverage results obtained for the design, a merging of the results is performed for the certain corresponding coverpoints in the design. In the merged results, a coverpoint is considered as covered if at least one corresponding coverpoint is covered during the logic simulation.

Abstract: In the context of electronic design automation and in particular coverage-driven verification, each of a number of integrated coverage models to be merged for coverage analysis are divided between a code coverage model and a functional coverage model. During a coverage model generation phase, new code coverage models or functional coverage models are created only if they are not already in a coverage model database repository; otherwise, they are copied. During a merging phase, code coverage models or functional coverage models are loaded only if they have not already been loaded. Signatures that can be based on checksums can be used to determine whether the models are unique or duplicates of those already created or loaded. Selectivity in the creation and re-use of the respective coverage models provides computational time savings in each of the creation and loading phases.

Abstract: A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs.

Abstract: A structure analysis device includes a memory and a processor configured to obtain model information, evaluate a size of a model in accordance with the model information, select, in accordance with the evaluated size, either a direct method or an iterative method as a first algorithm of a simultaneous linear equation of a structure analysis solver that uses a finite element method, and execute structure analysis of the model by using the first algorithm.

Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation.

Abstract: A method includes: identifying a timing path of a logic circuit; determining a Boolean expression at an internal node in the timing path; providing a DC vector having a plurality of forms; determining a Boolean value at the internal node for each of the forms based on the Boolean expression; determining a quantity of stressed transistors in the timing path for each of the forms separately based on the respective Boolean value; and determining a best-case form, associated with an aging effect of the logic circuit, and a worst-case form, associated with the aging effect, out of the forms based on the quantities of stressed transistors.

Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.

Abstract: A method of 3D circuit conception comprising: providing, to a circuit conception tool, circuit design files representing a 3D circuit design including one or more first circuit elements attributed to a first tier of the 3D circuit and one or more second circuit elements attributed to a second tier of the 3D circuit; modifying, by the circuit conception tool, a property of the one or more first and/or second circuit elements to permit any of the second circuit elements to superpose, or be superposed by, any of the first circuit elements; and performing, by the circuit conception tool, placement and routing of the 3D circuit design based on a 2D circuit representation, interconnection nodes of the one or more second circuit elements being defined in one or more interconnection levels of the 2D circuit representation.

Abstract: In the context of electronic design automation and particularly circuit layout design software tools, systems and methods for incremental chaining of circuit devices (or, more generally, “figures,” which can include instances and pins) permit user-interactive abutment and placement. Selection of one or more anchor figures highlights chaining candidates which can be automatically chained to the anchor figure(s) upon selection, as with a single mouse click. As compared to manual interactive abutment or automatic batch-mode chaining, incremental chaining offers improved usability, reduced manual effort, and the opportunity for user interaction as a chain is constructed, because the user is permitted interventions at any point in the chaining process for altering device parameters or characteristics.

Abstract: Object automated determination of monitors associated with a component (i.e., application/software, middleware, hardware or the like) that has yet to be implemented within a computing environment infrastructure. Such a determination of the monitors relies on deploying one or more probes that scan through various, if not all, layers of the computing environment infrastructure, such as the hardware, the network, storage, operating systems, virtual layer, middleware, database, application layer, and/or the application to identify possible monitoring requirements. In this regard, the probes scan the environment to determine downstream services that effect the component and the upstream services effected by the component and the set-up/configurations associated with those services. Once the services and corresponding configurations have been identified, the appropriate monitors can be determined.

Abstract: A method, and apparatus and a computer program product for determining coverage in hardware verification based on relations between coverage events. The method comprises generating an over-approximation model of the hardware being verified to perform formal verification thereof with respect to a target coverage event being utilized in the verification process along with a set of coverage events. A score indicating an estimated conditional probability to hit the target coverage event in the verification process, given that the coverage event is hit in the verification process, may be determined for each coverage event based on the formal verification. The method further comprises selecting test suits to be executed in the verification process based on the scores and the test suits probability to hit each coverage event. The verification process may be the performed the selected test suits in order to cover the target coverage event.

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).

Abstract: A node type of a plurality of distributed nodes to which a table to be added to a distributed database should be assigned can be identified by applying a set of placement rules defined for the table. The set of placement rules can also be applied to determine whether the table should be partitioned into more than one partition. A table group name associated with the table can be obtained and used in conjunction with the node type and determination of whether to partition the table to store the table in the distributed database on at least one node of the plurality of nodes as one or more partitions.

Abstract: A design assistance device assists design of a processing device to execute processing and includes an acquirer, divider, communication code generator, and outputter. The acquirer acquires processing code describing content of the processing. The divider divides the processing code into modules and determines, for each of the modules, an execution environment in which the module is to be executed, from among a plurality of execution environments provided on the processing device. The communication code generator generates, when a module of the plurality of modules includes partial processing prioritized for execution in a second execution environment other than a first execution environment determined for execution of the module, a communication code for communication between the first execution environment and the second execution environment to execute the partial processing in the second execution environment.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.

Abstract: Generating an abstract model of the behavior of a hardware and/or software design. A learning framework learns an unknown regular language that represents the behaviors of the hardware and/or software logic which do not violate a specified property that the abstract model is required to satisfy. The framework receives input data including the specified property, concrete models of the behavior of the hardware and/or software; and an alphabet of all symbols that are allowed to occur in any string that can be defined in the unknown regular language, each symbol representing an event in the hardware and/or software. The framework generates an abstract model of the behavior of the hardware or software design by checking whether a sequence of events in a concrete model satisfies the specified property and outputs the generated abstract model.

Abstract: A neural network based learning system for designing a circuit, the design system including at least one memory, at least one processor in communication with said at least one memory, said at least one processor configured to generate a mathematical model of the circuit, determine a structural definition of the circuit from the mathematical model, define a mapping of a plurality of components of the circuit to a plurality of neurons representing the plurality of components of the circuit using at least the structural definition, synthesize, on a hardware substrate, the plurality of neurons, and execute, using the synthesized plurality of neurons on the hardware substrate, at least one test using at least one optimization constraint to determine an optimal arrangement of the plurality of components.

Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: A method and/or system is disclosed for pre-silicon verification of a first integrated circuit design modified to a second integrated circuit design to avoid a hit of property P where property P has a known counterexample. The method/system includes applying a first implication check in an equivalence testbench on the first integrated circuit and on the second integrated circuit to determine whether the second integrated circuit hits property P in the same way as the first integrated circuit hits property P. Additionally or alternatively applying a second implication check to determine whether the second integrated circuit hits property P at a different timestep than the first integrated circuit hits property P. Additionally or alternatively applying a third implication check to determine whether the second integrated circuit hits property P further along a path than the first integrated circuit hits property P.

Abstract: A computer implemented method of passive verification of an electronic design, includes the steps of receiving a first electronic design file of a first electronic design comprised at least in part of a mixed signal or analog system, the first electronic design file including at least one first system and first subsystem, collecting first input data from at least one first system input and first subsystem input, analyzing a first parameter of the first input data, receiving a second electronic design file of a second electronic design comprised at least in part of a mixed signal or analog system, the second electronic design file including at least one second system and second subsystem that are comparable in function to the at least one first system and first subsystem of the first electronic design file, collecting second input data from at least one second system input and second subsystem input of the second design file, analyzing the first parameter of the second input data, comparing the analysis of the

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

Abstract: The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.

Abstract: A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.

Abstract: An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following: receiving or retrieving a circuit design, analyzing the circuit design to identify errors and warnings, and displaying identified errors and warnings where errors and warnings matching a registered condition set are waived. This approach provides for a 1-to-many relationship between identification of a waiver and application of waivers.

Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

Abstract: Electrostatic discharge (ESD) protection for an electronic circuit includes a timer circuit that controls multiple clamp circuits. In this way, less circuit area may be used for the timer circuit as compared to conventional ESD protection schemes. In some embodiments, the ESD protection circuit is employed in a data storage apparatus that includes a non-volatile memory array (e.g., NAND devices).

Abstract: Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.

Abstract: A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.

Abstract: Aspects of the present disclosure address systems and methods for functional coverage in integrated circuit (IC) designs utilizing arbitrary expression to define irrelevant domains in coverage item definitions. A coverage item definition is determined to include an arbitrary expression that defines an irrelevant domain for a coverage item in a functional coverage analysis of an IC design. Based on determining if the item definition comprises the arbitrary expression, a verification the arbitrary expression satisfies one or more analyzability conditions is performed. Based on verifying the arbitrary expression satisfies the one or more analyzability conditions, the irrelevant domain for the coverage item is calculated based on the arbitrary expression. An enhanced functional coverage model that excludes the irrelevant domain for the coverage item is generated and used to perform the functional coverage analysis on the IC design.