Abstract: Object automated determination of monitors associated with a component (i.e., application/software, middleware, hardware or the like) that has yet to be implemented within a computing environment infrastructure. Such a determination of the monitors relies on deploying one or more probes that scan through various, if not all, layers of the computing environment infrastructure, such as the hardware, the network, storage, operating systems, virtual layer, middleware, database, application layer, and/or the application to identify possible monitoring requirements. In this regard, the probes scan the environment to determine downstream services that effect the component and the upstream services effected by the component and the set-up/configurations associated with those services. Once the services and corresponding configurations have been identified, the appropriate monitors can be determined.

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).

Abstract: A node type of a plurality of distributed nodes to which a table to be added to a distributed database should be assigned can be identified by applying a set of placement rules defined for the table. The set of placement rules can also be applied to determine whether the table should be partitioned into more than one partition. A table group name associated with the table can be obtained and used in conjunction with the node type and determination of whether to partition the table to store the table in the distributed database on at least one node of the plurality of nodes as one or more partitions.

Abstract: A method, and apparatus and a computer program product for determining coverage in hardware verification based on relations between coverage events. The method comprises generating an over-approximation model of the hardware being verified to perform formal verification thereof with respect to a target coverage event being utilized in the verification process along with a set of coverage events. A score indicating an estimated conditional probability to hit the target coverage event in the verification process, given that the coverage event is hit in the verification process, may be determined for each coverage event based on the formal verification. The method further comprises selecting test suits to be executed in the verification process based on the scores and the test suits probability to hit each coverage event. The verification process may be the performed the selected test suits in order to cover the target coverage event.

Abstract: A design assistance device assists design of a processing device to execute processing and includes an acquirer, divider, communication code generator, and outputter. The acquirer acquires processing code describing content of the processing. The divider divides the processing code into modules and determines, for each of the modules, an execution environment in which the module is to be executed, from among a plurality of execution environments provided on the processing device. The communication code generator generates, when a module of the plurality of modules includes partial processing prioritized for execution in a second execution environment other than a first execution environment determined for execution of the module, a communication code for communication between the first execution environment and the second execution environment to execute the partial processing in the second execution environment.

Abstract: Generating an abstract model of the behavior of a hardware and/or software design. A learning framework learns an unknown regular language that represents the behaviors of the hardware and/or software logic which do not violate a specified property that the abstract model is required to satisfy. The framework receives input data including the specified property, concrete models of the behavior of the hardware and/or software; and an alphabet of all symbols that are allowed to occur in any string that can be defined in the unknown regular language, each symbol representing an event in the hardware and/or software. The framework generates an abstract model of the behavior of the hardware or software design by checking whether a sequence of events in a concrete model satisfies the specified property and outputs the generated abstract model.

Abstract: A method and/or system is disclosed for pre-silicon verification of a first integrated circuit design modified to a second integrated circuit design to avoid a hit of property P where property P has a known counterexample. The method/system includes applying a first implication check in an equivalence testbench on the first integrated circuit and on the second integrated circuit to determine whether the second integrated circuit hits property P in the same way as the first integrated circuit hits property P. Additionally or alternatively applying a second implication check to determine whether the second integrated circuit hits property P at a different timestep than the first integrated circuit hits property P. Additionally or alternatively applying a third implication check to determine whether the second integrated circuit hits property P further along a path than the first integrated circuit hits property P.

Abstract: A neural network based learning system for designing a circuit, the design system including at least one memory, at least one processor in communication with said at least one memory, said at least one processor configured to generate a mathematical model of the circuit, determine a structural definition of the circuit from the mathematical model, define a mapping of a plurality of components of the circuit to a plurality of neurons representing the plurality of components of the circuit using at least the structural definition, synthesize, on a hardware substrate, the plurality of neurons, and execute, using the synthesized plurality of neurons on the hardware substrate, at least one test using at least one optimization constraint to determine an optimal arrangement of the plurality of components.

Abstract: Invention disclosed herein is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of the integrated circuit device. The method can further include determining target gates referred to as trace signals within the integrated circuit device. The method can further include creating a hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving scalability of the connectivity verification by utilizing hierarchical decomposition embodiment of the invention.

Abstract: Data is received that characterizes a chip in the package system (CPS) having a plurality of wires and vias. Thereafter, using the received data, a chip power calculation is performed. The chip power calculated is used to generate a thermal-aware power map. Further, package and system level thermal analysis is performed using the power map to generate a tile-based CPS thermal profile. A plurality of chip finite element sub-models are then generated that each correspond to a different tile. A thermal field solution is solved for each sub-model so that, for each wire, wire temperature rises are extracted from the corresponding the chip sub-model analysis and combined with temperature values from the CPS thermal profile. This extracting and combining is then used to generate a back-annotation file covering each metal wire and via in the CPS.

Abstract: A computer implemented method of passive verification of an electronic design, includes the steps of receiving a first electronic design file of a first electronic design comprised at least in part of a mixed signal or analog system, the first electronic design file including at least one first system and first subsystem, collecting first input data from at least one first system input and first subsystem input, analyzing a first parameter of the first input data, receiving a second electronic design file of a second electronic design comprised at least in part of a mixed signal or analog system, the second electronic design file including at least one second system and second subsystem that are comparable in function to the at least one first system and first subsystem of the first electronic design file, collecting second input data from at least one second system input and second subsystem input of the second design file, analyzing the first parameter of the second input data, comparing the analysis of the

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

Abstract: Disclosed examples include methods for verifying mixed-signal circuit design, in which an executable specification file is generated including integration abstractions that represent an intended integration of ports and digital circuit blocks of the mixed-signal design, a formal properties file is automatically generated from the executable specification file, an analog circuit component of the mixed-signal circuit design is modeled as a digital circuit component in a model file, at least one analog circuit block of the mixed-signal circuit design is modeled as one or more ports in the model file, and correspondence of connections of the formal properties file and the model file is verified with the mixed-signal circuit design to generate a coverage report file.

Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

Abstract: The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.

Abstract: A method of detecting a circuit malfunction in a register transfer level, RTL, design stage is disclosed. The method comprises obtaining signal points of each register from a circuit model based on the RTL design stage, generating a property list according to the signal points of each register, wherein the property list includes a property to be verified for each signal point, performing a formal verification operation according to the circuit model and the property list, to determine whether the property of the property list for each signal point in the circuit model is true, and generating a circuit malfunction result according to the signal point whose property is not true.

Abstract: An approach is described for determining waiver applicability conditions and applying the conditions to multiple errors or warnings in physical verification tools. According to some embodiments, the approach includes identification of a waiver of an error or warning, registration of one or more condition sets for waiver of an error or warning, waiver of multiple errors or warnings that match the registered one or more condition sets, and further comprise any or all of the following: receiving or retrieving a circuit design, analyzing the circuit design to identify errors and warnings, and displaying identified errors and warnings where errors and warnings matching a registered condition set are waived. This approach provides for a 1-to-many relationship between identification of a waiver and application of waivers.

Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

Abstract: Electrostatic discharge (ESD) protection for an electronic circuit includes a timer circuit that controls multiple clamp circuits. In this way, less circuit area may be used for the timer circuit as compared to conventional ESD protection schemes. In some embodiments, the ESD protection circuit is employed in a data storage apparatus that includes a non-volatile memory array (e.g., NAND devices).

Abstract: Aspects include parsing, by a computer system, a design file of an integrated circuit including a plurality of stages to extract a plurality of inputs and outputs of a plurality of latches. The computer system can sort the latches based on latch locations in the stages and build a plurality of ordered vectors of signals before and after the latches based on the sorting. The computer system can build a plurality of parity vectors for each of the ordered vectors of signals before and after the latches, build a latch bank for each of the parity vectors before the latches, and build a parity vector comparison to detect a parity failure based on comparing the parity vectors after the latches with an output of the latch bank.

Abstract: A system and method of verifying hardware that includes software configured to control its operation, the method comprising providing an abstracted version of hardware to be tested; verifying the functionality of the hardware; writing test bench software using physical-layer routines; drafting hybrid verification intellectual property modules, wherein the hybrid verification intellectual property modules comprise both synthesizable and non-synthesizable code and are configured to stimulate the abstracted hardware and to test software anticipated to be used in connection therewith; and creating network-level routines that can be passed to physical-layer routines as part of a hardware verification process.

Abstract: Aspects of the present disclosure address systems and methods for functional coverage in integrated circuit (IC) designs utilizing arbitrary expression to define irrelevant domains in coverage item definitions. A coverage item definition is determined to include an arbitrary expression that defines an irrelevant domain for a coverage item in a functional coverage analysis of an IC design. Based on determining if the item definition comprises the arbitrary expression, a verification the arbitrary expression satisfies one or more analyzability conditions is performed. Based on verifying the arbitrary expression satisfies the one or more analyzability conditions, the irrelevant domain for the coverage item is calculated based on the arbitrary expression. An enhanced functional coverage model that excludes the irrelevant domain for the coverage item is generated and used to perform the functional coverage analysis on the IC design.

Abstract: The present disclosure relates to a method for probabilistic simulation of a microelectronic device, said method being implemented automatically by an electronic processing device and including the following steps: a) defining a plurality of first samples of the device from a probability distribution of at least one physical parameter of the device; b) for each first sample, determining, through an electrical simulation method, the value of at least one operating variable of the device; c) defining, by regression from values of the physical parameters and operating variables of the first samples simulated in step b), a mathematical model approximating the response of the electrical simulation method.

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

Abstract: Example systems and methods are disclosed for estimating power consumption by a clock tree in a register-transfer level (RTL) circuit design based on a previously generated reference gate-level circuit design. A plurality of regions within the clock tree structure of the reference gate-level circuit design are identified, where the plurality of regions are demarcated by one or more clock gating structures. A region-based clock model is generated that includes at least one clock constraint model for each identified region. The region-based clock model is used to synthesize the clock tree in the RTL circuit design for estimating power consumption.

Abstract: An automated method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The method operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The invention inspects the various devices and automatically traces DC circuit paths to DC power rails. The invention then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The method generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.

Abstract: Described herein is a hybrid approach to error reporting, using a combination of hardware and software, for peripheral component interconnect (PCI) express devices. The device hardware detects an error on a packet, where the packet is for a transaction and received from a host computer. Upon detecting the error, the device hardware generates an interrupt that is processed in software. In certain embodiments, the software based processing involves determining, based on the packet, that the transaction is directed to an address space of an emulated configuration register. The software based processing further involves identifying a function as being associated with the error, determining attributes associated with the error, and storing the attributes and an identifier associated with the function in a location available to the device hardware, thereby enabling the device hardware to report the attributes and identifier to the host computer.

Abstract: A method of verifying a circuit design, includes, in part, identifying a first groups of signals associated with the circuit, selecting a signal sampling window depth, performing a first verification of the circuit using a first test bench adapted to cause transitions in the first group of signals, storing values of the signals in the first group during each of the cycles defined by the sapling window depth to generate a first functional coverage, performing a second verification of the circuit design using a second test bench to generate a second functional coverage, comparing the second functional coverage to the first functional coverage, and automatically generating one or more cover property statements if the second functional coverage is less than the first functional coverage. The one or more cover property statements cause the second functional coverage to become equal to or greater than the first functional coverage.

Abstract: A data analysis engine is implemented in a testbench to improve coverage convergence during simulation of a device-under-validation (DUV). During a first simulation phase initial stimulus data is generated according to initial random variables based on user-provided constraint parameters. The data analysis engine then uses a time-based technique to match coverage variables sampled from simulation response data with corresponding initial random variables, determines a functional dependency (relationship) between the sampled coverage variables and corresponding initial random variables, then automatically generates revised constraint parameters based on the functional dependency. The revised constraint parameters are then used during a second simulation phase to generate focused random variables used to stimulate the DUV to reach additional coverage variables. In one embodiment, the functional dependency is determined by cross-correlating sampled coverage variables and corresponding initial random variables.

Abstract: Aspects determine optimal physical attribute values for defining a grip form factor on a microfluidic grip panel of a digital pen as a function of a correlation of the optimal physical attribute values to an intended use of the digital pen, wherein the optimal physical attribute values include a width dimension, a surface texture attribute, and shape pattern attribute that is defined as a function of the width dimension; and drive the microfluidic grip panel into a grip form corresponding to the determined optimal physical attribute values during use of the digital pen by a user.

Abstract: Systems and methods are provided for simulating quantile behavior of a physical system. A plurality of parameter samples to a physical system are accessed and a subset of the parameter samples are identified, each of the plurality of parameter samples including a variation of parameters for the physical system. The physical system is simulated based on the subset of the parameter samples to generate simulation results, each of the subset of the parameter samples corresponding to a respective one of the simulation results. A neural network is trained to predict the simulation results based on the subset of the parameter samples.

Abstract: Described is a method for implementing a snap to capability that enables the manufactured of a valid pattern in a semiconductor device, based upon an originally invalid pattern.

Abstract: A model-based tuning method for tuning a first lithography system utilizing a reference lithography system, each of which has tunable parameters for controlling imaging performance. The method includes the steps of defining a test pattern and an imaging model; imaging the test pattern utilizing the reference lithography system and measuring the imaging results; imaging the test pattern utilizing the first lithography system and measuring the imaging results; calibrating the imaging model utilizing the imaging results corresponding to the reference lithography system, where the calibrated imaging model has a first set of parameter values; tuning the calibrated imaging model utilizing the imaging results corresponding to the first lithography system, where the tuned calibrated model has a second set of parameter values; and adjusting the parameters of the first lithography system based on a difference between the first set of parameter values and the second set of parameter values.

Abstract: A computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Abstract: In one embodiment, a method may receive, by a compiler of a host computing system, source code for a computer application. The method may also include separating a first portion of the source code and a second portion of the source code that are to be compiled for execution by an accelerator operatively coupled to the host computing system. The method may also include compiling the first portion of the source code to generate hardware description language code. A logic block is to be generated on the accelerator in view of the hardware description language code. The method also includes compiling the second portion of the source code to generate softcore processor code, and adding instructions to the softcore processor code to cause the softcore processor code to interact with the logic block during execution of the softcore processor code and the logic block.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior between one or more excitation points and one or more observation points for a given circuit design characteristic. Sensitivities of that given circuit design characteristic to each constituent parasitic (or a group of parasitics that might be, for example, associated with a given structural element such as a layer) are then computed. The computer/software tool generates a visual display based on the relative sensitivities; for example, in one embodiment, relative sensitivities can be color-coded to permit a designer to visualize sources of problems in the IC design. In other embodiments, the sensitivities can be filtered and/or processed, e.g., so as to provide EDA driven assistance to changes to reduce excessive sensitivities or sensitivities to certain parasitics.

Abstract: A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.

Abstract: The present specification is related to analysis of digital circuits for assessing a fault sensitivity of a digital logic circuit. An example method includes: obtaining a set of input vectors that represent possible inputs to the digital logic circuit; for each output gate of the plurality of digital logic gates: (i) for each input vector of the set of input vectors, determining a cumulative output delay for the output gate, and (ii) determining an averaged cumulative output delay for the output gate by averaging the cumulative output delays for the output gate that were determined for multiple input vectors of the set of input vectors; generating a fault sensitivity score for the digital logic circuit based on the averaged cumulative output delays for the output gates of the digital logic circuit; and providing the fault sensitivity score.

Abstract: An unobservable cycle for at least one latch in a circuit design is detected. The unobservable cycle indicates that the at least one latch is not observable to downstream logic in the circuit design. A coverage event is generated to identify the unobservable cycle for the at least one latch. The coverage event is tracked to detect a state associated with the unobservable cycle and a state change cycle. The state change cycle is determined based on a simulation technique. A redundant switching of the at least one latch based on the state associated with the unobservable cycle and the state change cycle is determined. Furthermore, manufacturing of a circuit based on the circuit design is at least initiated. The circuit design is modified to prevent the redundant switching of the at least one latch.

Abstract: A method for simulating semiconductor devices includes running ensemble Monte Carlo (EMC) simulations of a plurality of semiconductor devices having a first plurality of configurations in a Design of Experiment (DoE) space to produce EMC results. Mobility parameters are extracted across the DoE space from the EMC results. A response-surface mobility model is constructed using the extracted mobility parameters. The response-surface mobility model is used to run a drift-diffusion simulation of a semiconductor device with a different configuration from the first plurality of configurations.

Abstract: A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include power switches inside the block, related supplies of logic ports, supply power states, system power states, power management devices such as isolation logic and level shifters, feed-through and floating ports. The power model may be expressed either in UPF or as a combination of liberty model and UPF. After replacing modules with abstracted models the HPVS can quickly verify an entire SoC with a small memory footprint.

Abstract: An illustrative system may comprise a plurality of distributed network nodes hosting a two-dimensional distributed digital ledger. The distributed digital ledger may have a plurality of chains of digital blocks in the two-dimensions, wherein each chain may be associated with a particular functionality (e.g., a first set of integrated circuit processes) and a corresponding level of security. For example, a first chain in the first direction may contain digital blocks containing code differentials of the hardware description language code forming the integrated circuit design. A second chain in a second direction may contain digital blocks containing simulation data records generated during the simulation of the integrated circuit design. The first chain and the second chain may be based upon different cryptographic protocols and therefore may be cryptographically separate from each other.

Abstract: Systems and methods are provided for identifying a wire of a plurality of wires to be adjusted to mitigate effects of electromigration. A segment electromigration stress value for each segment of a wire is determined for a wire of a circuit in a circuit design. A wire electromigration stress value for the wire is determined as a function of the segment electromigration stress values of segments of the wire. A ranked list of two or more wires of the circuit is displayed according the wire electromigration stress values of the two or more wires.

Abstract: Disclosed are a process design kit (PDK) for integrated circuit (IC) designs and a computer-aided design (CAD) system that employs the PDK. The PDK includes a design scan script. When the script is executed by the CAD system, previously generated and stored IC designs are scanned and a report with cell use information (CUI) is generated. The CUI indicates the different parameterized cells (pcells) and different configurations thereof contained in the IC designs. Also disclosed is a PDK development system, which receives CUI reports from CAD system(s), compiles the CUI, and revises the PDK (i.e., develops an update or upgrade) based, in part, on the complied CUI. For example, the complied CUI can indicate critical targets that require a regression analysis during the PDK revision process. By limiting regression analyses to identified critical targets, the turn around time and costs associated with revising the PDK are significantly reduced.

Abstract: A method for optimizing a multi die implementation flow that is aware of mix-and-match die integration for implementing multi-die integrated circuits includes partitioning a netlist into partitions comprehending mix-and-match die integration, wherein each partition will be assigned to a die. Each partition is placed into a corresponding die. A clock tree of the integrated circuit is synthesized. Nets of the integrated circuit in are routed in accordance the placing and synthesizing.

Abstract: A method for evaluating a test suite for a software library includes generating a mutated software library by adding a fault to the software library, while the software library is used by a testing tool to evaluate a test suite. The method further includes loading the mutated software library, then executing a test in the test suite on the mutated software library to obtain a test result. The method further includes analyzing the test result.

Abstract: The present disclosure relates to a computer-implemented method for use in design for manufacturing associated with a die or package. Embodiments may include providing, using a processor, an electronic design and displaying, at a graphical user interface, at least a portion of a layout associated with the electronic design. Embodiments may also include determining an expected thermal or centrifuge force manufacturing variation associated with the electronic design. Embodiments may further include allowing a user to insert, at the graphical user interface prior to signoff, a copper pillar bump or solder bump on at least a portion of the layout based upon, at least in part, the determined expected thermal or centrifuge force manufacturing variation. Embodiments may further include displaying the copper pillar bump or the solder bump on the layout at the graphical user interface.

Abstract: Pre-silicon fairness evaluation to detect fairness issues pre-silicon. Drivers drive a plurality of commands on one or more interfaces of a device under test to test the device under test. State associated with the device under test is checked. Based on the state, a determination is made as to whether the drivers are to continue driving commands against the device under test. Based on determining that the drivers are to continue driving the commands, a further determination is made as to whether a predefined limit has been reached. Based on determining the predefined limit has been reached, ending the test of the device under test in which the test fails.

Abstract: The generation of reversible circuits from high-level code is desirable in a variety of application domains, including low-power electronics and quantum computing. However, little effort has been spent on verifying the correctness of the results, an issue of particular importance in quantum computing where such circuits are run on all inputs simultaneously. Disclosed herein are example reversible circuit compilers as well as tools and techniques for verifying the compilers. Example compilers disclosed herein compile a high-level language into combinational reversible circuits having a reduced number of ancillary bits (ancilla bits) and further having provably clean temporary values.

Abstract: The present disclosure relates to a method for electronic design. Embodiments may include receiving, using a processor, an electronic design and performing formal verification upon at least a portion of the electronic design for a specific problem statement. Embodiments may further include generating a plurality of traces associated with the formal verification satisfying the specific problem statement and displaying, at a graphical user interface, an option to select at least one of the plurality of traces for display at the graphical user interface while the formal verification is performed.