Abstract: A method for designing an optimal wiring topology for electromigration avoidance is disclosed. The wiring topology includes multiple sources, multiple sinks and multiple wires. The method includes the following steps: A feasible wire, a wire of the shortest length connecting each pair of source and sink, is calculated, and the capacity of each feasible wire is decided. An initial feasible topology is found. A flow network is created based on the initial topology. Negative cycles are iteratively checked and removed until no more negative cycles.

Abstract: A layout method of a semiconductor integrated circuit includes five steps. The first step is of extracting a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements is carried out. The second step is of generating routing prohibition regions where a routing is prohibited in an area including the wiring crowding place. The third step is of carrying out a routing by bypassing the routing prohibition regions. The fourth step is of deleting the routing prohibition regions. The fifth step is of carrying out a re-routing. The generating step includes: calculating a size and an interval of the routing prohibition regions based on a rate for generating a routing prohibition region in the area in each wiring layer, and generating the routing prohibition regions in the area on the basis of the calculating result.

Abstract: A layout method, upon performing layout of layer blocks each including internal elements, with respect to mounting area where internal element resources, to which internal elements can be assigned, are arranged, comprises: arranging, when first layer block and second layer block overlap in overlapping area, first layer block and the second layer block such that sum of number of first internal elements included in the overlapping area, among internal elements of first layer block, and number of second internal elements included in the overlapping area, among internal elements of second layer block, is not greater than number of internal element resources included in the overlapping area; and assigning the internal element resources included in the overlapping area to first layer block and second layer block, in accordance with ratio of number of first internal elements to number of second internal elements.

Abstract: A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region (e.g., a channel), and a set of contacts to the active region. The field-controlling element can be coupled to one or more of the contacts in the set of contacts. The field-controlling element can be formed of a low conducting layer of material and have a lateral resistance that is both larger than an inverse of a minimal operating frequency of the device and smaller than an inverse of a maximum control frequency of the device.

Abstract: The present invention provides a design method for circuit layout and a rapid thermal annealing method for a semiconductor apparatus. The design method includes: establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length; obtaining a difference between distributing densities of STI patterns in a particular region and in a target region; obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship; obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and adjusting a gate pattern length in the particular region according to the gate pattern length difference.

Abstract: To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

Abstract: In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network.

Abstract: A semiconductor device for layout has first and second power supply domains and has wiring connected to and from cells belonging to a second power supply domain. A wiring inhibited/allowed area setting unit sets an exclusive wiring inhibited area and a pass-through wiring allowed area within the first power supply domain based on a repeater wire maximum length being a maximum wire length which a repeater buffer can drive. A wiring setting unit modifies wiring based on the exclusive wiring inhibited area and the pass-through wiring allowed area. A repeater insertion unit sets a repeater buffer to be inserted on a wire according to the repeater wire maximum length. The exclusive wiring inhibited area allows wiring connecting cells within the first power supply domain and inhibits pass-through wiring. The pass-through wiring allowed area, being the first power supply domain excluding the exclusive wiring inhibited area, allows pass-through wiring.

Abstract: A floorplan creation information generating method according to this embodiment includes setting a group to a plurality of circuit modules based on a netlist and group setting information, calculating a distance that satisfies a timing constraint between the set groups, and generating floorplan creation information for creating a floorplan including the calculated distance between the groups.

Abstract: A design support apparatus includes: a circuit-data generation unit to generate circuit data based on layout information of a semiconductor integrated circuit; and a parameter determination unit to set a first parameter relating to mechanical stress exerted on a transistor including at least one of a plurality of gates in a diffusion region, wherein the circuit-data generation unit obtains a mobility of the transistor based on the first parameter and reflects the mobility in the circuit data.

Abstract: Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.

Abstract: A method of adapting a layout of a standard cell of an integrated circuit is provided. A current collection path in the standard cell is selected which connects components within the standard cell to an output connection, wherein the current collection path is arranged to collect current from the components at a plurality of current collection points arranged along its length. A maximum current location on the current collection path is determined at which a maximum possible current flow in the current collection path will occur if the output connection is connected there, the maximum possible current flow being a sum of current contributions from the current collection points. A maximum width of the current collection path at the maximum current location is determined such that the maximum width satisfies a minimum path width requirement with respect to the maximum possible current flow.

Abstract: Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.

Abstract: Configurable analog input circuits are provided. An analog input circuit may include a plurality of configurable input channels, at least one analog-to-digital converter, and at least one processor. Each input channel may include a plurality of switches utilized to select a type of input signal received via the input channel and a set of input terminals selectively utilized to correspond with the selected type of input signal. The at least one analog-to-digital converter may be configured to convert, for each of the plurality of input channels, the selected type of input signal into a digital output. The at least one processor may be configured to control operation of the plurality of switches associated with each of the plurality of configurable input channels.

Abstract: A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each standard cell, edge labels can be assigned based on colors of objects within a predetermined distance from each edge. A truth table, which indicates legal spacing between pairs of standard cells based on their edge labels, can be accessed. A plurality of standard cells of a design can then be placed based on the truth table.

Abstract: Methods and software for placing or re-placing integrated circuit cells and routing or re-routing nets between the cells in an integrated circuit layout. The method includes selecting a region of the cells in the integrated circuit layout, selecting a cell within the selected region, locating a border point where a net coupled to the selected cell crosses a border of the selected region, and moving the selected cell within the selected region to improve a timing characteristic (e.g., a wire length, capacitance, or other characteristic of the net that affects timing or delay) of the net. The method and software advantageously improve the placement of cells and routing of wires around congested or reserved regions after global routing has been performed, without causing timing violations in other signal paths on the integrated circuit device, in a computationally efficient manner.

Abstract: Some embodiments provide systems and techniques to facilitate construction of a canonical representation (CR) which represents a logical combination of a set of logical functions. During operation, the system can receive a CR-size limit. Next, the system can construct a set of CRs based on the set of logical functions, wherein each CR in the set of CRs represents a logical function in the set of logical functions. The system can then combine a subset of the set of CRs to obtain a combined CR. Next, the system can identify a problematic CR which when combined with the combined CR causes the CR-size limit to be exceeded. The system can then report the problematic CR and/or a logical function associated with the problematic CR to a user, thereby helping the user to identify an error in the set of logical functions.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.

Abstract: Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.

Abstract: An integrated circuit design apparatus includes a macro signal terminal position determination unit that determines temporary arrangement positions of a scan-in terminal and a scan-out terminal of each of a number of macros. The unit updates layout information of an integrated circuit based on the temporary arrangement positions. The apparatus includes an initial scan path route determination unit that updates scan path connection information, such that one of the macros arranged in a closest distance is connected in turn starting with a scan-in external terminal, with reference to the updated layout information and the scan path connection information. The apparatus include a scan path re-routing unit that determines a scan path connection order, such that a scan path total wiring length becomes shortest, with reference to the updated layout information and the updated scan path connection information. This unit updates the scan path connection information based on this determined order.

Abstract: An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

Abstract: An embodiment of a method for enabling a high level modeling system for implementing a circuit design in an integrated circuit device includes: receiving a high-level characterization of the circuit design; receiving a portable location constraint associated with elements of the circuit design; and generating, by a computer, a low-level characterization of the circuit design based upon the high-level characterization and the portable location constraint.

Abstract: Techniques are described for increasing the density of structures in a layout circuit design, while reducing undesired total interconnect capacitance that might otherwise be created by the increase in structure density. Data representing a pattern of fill structures is added to the fill regions of the design for one of the layers. Data representing a pattern of fill structures then is added to the fill regions of the design for another of the layers adjacent to the first layer. In the design for the second conductive layer, however, the pattern of fill structures is offset from the pattern of fill structures added to the design for the first layer in a direction substantially parallel to the layers. The offset may be selected to minimize or otherwise reduce the amount of overlap between the fill structures along a direction substantially perpendicular to the layers, thereby reducing the total interconnect capacitance associated with the layers.

Abstract: A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.

Abstract: A method, system and computer program product are provided for implementing routing first for rapid prototyping and improved wiring of heterogeneous hierarchical integrated circuit chips. Placement for each of a plurality of random logic macros (RLMs) is identified. Predefined wiring shapes are created for each of the identified RLMs. Full chip wire routing is defined responsive to the created predefined wiring shapes for each of the identified RLMs.

Abstract: A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints.

Abstract: A circuit design assist system that receives a user instruction for registering an interface section of at least two circuits as a template, and generates a plurality of circuit patterns of the interface section, each pattern having a different combination of electrical properties of at least one device included in the interface section for evaluation. When an evaluation result indicates that the interface section operates normally for each of the circuit patterns, the circuit design assist system registers the interface section as the template.

Abstract: A method, system, and computer usable program product for equation based retargeting of design layouts are provided in the illustrative embodiments. A set of desirable combination of values of a set of layout parameters of the design layout is determined. A desirable region that includes the set of the desirable combination of values is determined. An equation is computed to determine a retargeting value for a first combination of values of the set of layout parameters with respect to the desirable region. Instructions are generated to adjust a value in the first combination to generate a second combination of values of the set of layout parameters such that the second combination falls in the desirable region. A shape in the design layout is retargeted such that the retargeted shape uses the second combination of values of the set of layout parameters. The IC is manufactured using the retargeted shape.

Abstract: A skewed placement grid for an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a placement grid which includes a plurality of cells. Each of the plurality of cells includes one of a corresponding plurality of circuits. A center point of each of the cells is located at a unique coordinate along a first axis and a second axis with respect to each of the other ones of the plurality of cells. The IC further includes a first plurality of signal interconnections, wherein each of the plurality of signal interconnections is coupled to a corresponding one of the first plurality of circuits.

Abstract: A system includes a memory and a controller. The controller may include a group of pads and an allocation register. The controller is configured to receive input signals corresponding to the group and allocate each one of the pads to output one of the input signals based on a configuration of pins of the memory. The controller is also configured to redirect the input signals, within the controller, based on the allocation of the pads and output the input signals from the controller into the pads.

Abstract: A disclosed packaging design supporting device for a semiconductor integrated circuit includes a selection data acquisition unit inputting a change of the selected logic cell; a bulk fix data generation unit generating bulk fix data in which a bulk layer of the semiconductor substrate of the semiconductor integrated circuit has been fixed, arranging a design-change dummy logic cell in a region where no logic cell is arranged in the bulk layer, and generating a design-change logic cell by wiring the design-change dummy logic cell; and a selection cell move determination unit prohibiting the change with respect to the selected logic cell.

Abstract: A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.

Abstract: In one embodiment, a design methodology is described in which a functional description of each macro may be synthesized along with the other logic in a block. The resulting circuitry, including synthesized circuitry corresponding to each macro, may be placed within an area designated for the integrated circuit. The result may be analyzed, determining a location for the macro based on the location of the corresponding synthesized circuitry. For example, the geometric center of the synthesized circuitry may be located, and the geometric center of the custom circuitry associated with the macro may be placed at the same point as the geometric center of the synthesized circuitry. Because the macros are not placed in advance, the location of the macro may be controlled by other factors such as timing, space, wiring congestion, etc.

Abstract: Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for example, Simultaneous Dynamical Integration, wherein the morphable-devices correspond to nodes influenced by forces, including timing forces. The timing forces are derived, for example, from a timing graph; path delay; slack; and drive resistance of the elements. The timing closure uses timing-driven buffering and timing-driven resizing to reduce maximum delay and/or transition time, and/or to fix hold time. Nets having high capacitance and/or fanout, and timing critical nets are preferentially processed. Timing-driven buffering applies buffering solutions to segments of route trees, combines solutions of adjoining segments, and prunes sets of solutions. Timing-driven resizing morphably replaces selected elements with upsized versions thereof.

Abstract: Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout.

Abstract: According to various embodiments of the invention, a system and method for editing process rules for circuit design through a graphical editor is provided. In some embodiments, the graphical editor is a circuit design tool that provides the user of the tool, such as a circuit designer or process engineer, the ability to visualize, modify, create, or remove process rules through a graphical user interface (“GUI”). These process rules, also known as constraints or circuit design constraints, relate to the layout of circuits and is grouped into constraint groups (also known as “circuit design constraint groups”) that can be associated to specific circuit design objects.

Abstract: Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connection. An approach that is disclosed comprises a method, system, and article of manufacture for implementing metal-fill having an elongated shape that corresponds to the length of whitespace. Also disclosed is the aspect of implementing metal-fill that matches the routing direction. Yet another disclosure is an implementation of a place & route tool incorporating an integrated metal-fill mechanism.

Abstract: A circuit and methods for placing a circuit block on an integrated circuit (IC) are disclosed. An embodiment of the disclosed method includes dividing the IC into multiple regions based on pre-determined value. This pre-determined value may be a voltage drop value measured on specific regions on the IC. The performance requirement for the circuit block is determined and placed in one of the regions on the IC. In one embodiment, the placement of the circuit block is based on the performance requirement and the measured value at specific regions on the IC. The measured value may be a voltage drop value and a circuit block with a higher performance may be placed in a region with a lower voltage drop value.

Abstract: A variable gain amplifier device (100) with improved gain resolution is achieved. The device includes a programmable gain amplifier (PGA) (110), an analog-to-digital converter (ADC) (160), an automatic level control (ALC) algorithm means (176), and a delta-sigma modulator (180). The PGA (110) is capable to receive and to amplify an analog input signal (154) to thereby generate an analog output signal (164). The PGA (110) includes an amplifier (160) and a switchable resistor network (120). The ADC (170) is coupled to the PGA (110) and is capable to convert the analog output signal (164) to a digital signal (174). The ALC algorithm means (176) is coupled to the ADC (170) and is capable to generate a control code (178) by processing the digital signal (174). The delta-sigma modulator (186) is coupled to the ALC algorithm means (186) and is capable to generate a pulse-density modulated (PDM) signal (182) by processing the control code (178).

Abstract: The present invention relates to a method for optimizing power/ground pads in a power/ground distribution network. A power/ground distribution network is created for each of multiple voltage domains and a load current source of each node of the power/ground distribution network is modeled in consideration of the actual shapes and areas of functional blocks. A local optimization method is developed to solve problems generated when a conventional optimization method is applied to optimization of power/ground pads in a bump shape used for a flip chip, and a combination of global optimization and local optimization is applied to layouts using bump bonding, which is discriminated from the conventional optimization method restrictively applicable to layouts using wire bonding.

Abstract: A functional circuit is coupled to a power supply conductor by at least one power gating transistor. A switching device applies a gate drive voltage to a gate terminal of the power gating transistor via a resistive element. The power gating transistor provides a Miller capacitance between its drain and gate terminals. The Miller capacitance, the resistance of the resistive element, and the drive strength of the switching device are configured such that, in response to the switching device switching the gate drive voltage to allow more current to pass through the power gating transistor, the Miller capacitance provides a feedback mechanism competing against the switching device to reduce the slew rate of the gate drive voltage such that the current passing between the power gate supply conductor and the functional circuit through the power gating transistor is less than the saturation current of the power gating transistor.

Abstract: A method of forming an integrated circuit structure on a chip includes extracting an active layer from a design of the integrated circuit structure, forming a guard band conforming to the shape of the active layer, the guard band surrounds the active layer, and the guard band is spaced from the active layer at a first spacing in the X-axis direction and at a second spacing in the Y-axis direction, removing any part of the guard band that violates design rules, removing convex corners of the guard band, and adding dummy diffusion patterns into the remaining space of the chip outside the guard band. The first and second spacing can be specified as the same spacings in a Spice model characterization of the integrated circuit structure. The dummy diffusion patterns with different granularities can be added so that the diffusion density is substantially uniform over the chip.

Abstract: Some embodiments of the invention provide a method for placing circuit modules in an integrated circuit (“IC”) layout. The method computes a placement metric for the IC layout. In some embodiments, computing the placement metric includes partitioning a region the IC layout into several sub-regions by using a cut graph, where the cut graph is an approximation of a diagonal cut line. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut graph. In some embodiments, the cut graph is a staircase cut graph. These staircase cut graphs include several horizontal and vertical cut lines. In some embodiments, the cut graph is a cut arc.

Abstract: The chip area of a semiconductor device having a plurality of standard cells is to be made smaller. A semiconductor device includes first and second standard cells. The first standard cell includes a diffusion region, a functional device region opposed to the diffusion region, and a metal layer. The second standard cell includes another diffusion region continuous with the diffusion region, another functional device region opposed to the other diffusion region, and further another diffusion region formed between the other diffusion region and the other functional device region. The metal layer and the other functional device region are coupled together electrically through the diffusion regions.

Abstract: An improved method and system for stitching one or more islands of an integrated circuit design is disclosed. Multiple connected island objects in the IC design are first identified. At least one of the multiple identified connected island objects is then modified to form a modified island object. The modified island object may then be stitched into the multiple identified connected island objects. In some embodiments, stitching a modified island object may be implemented by tracking the endpoint(s), port(s), or node(s) of the connected island object being modified and stitched.

Abstract: A system for connecting an interface of an electronic device between first and second fabrics includes a constraint generator that associates first and second conditions with the interface, a first equation solver that solves one or more first equation to select a first plurality of connectors in the first fabric and a second plurality of connectors in the second fabric that satisfy the first condition based on an optimality criterion for the interface; and a second equation solver that solves one or more second equation to select one of the first plurality of connectors in the fabric and one of the second plurality of connectors in the second fabric that satisfy the second condition based on the optimality criterion for the interface.

Abstract: Disclosed are methods, systems, and structures for implementing interconnect modeling by using a test structure which include a variation of physical wire structures between local interconnects and distant interconnects. According to one approach, the impact of variations of the physical properties for neighborhood wires are considered for the electrical modeling of interconnects. This variation between the local and distant wire characteristics allows more accurate and robust interconnect modeling to be created.

Abstract: A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from predetermined design options for custom circuit boards. The hardware description language (HDL) module generates HDL corresponding to the design specifications and outputs the HDL to a circuit board producer.

Abstract: A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other.

Abstract: An access pad is used to provide access to a functional block of an integrated circuit (IC) device. The access pad is formed using dummy metal in an open space in a metallization level that is between a top metallization level and a base level on which the functional block is formed in the IC device. The access pad at the metallization level provides a contact to access an underlying circuit of the functional block so that the functional integrity of the functional block of the IC device can be verified during probing.