Abstract: A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.

Abstract: A system and method for optimizing a design layout by identifying features for abutment where the shapes that trigger the abutment are overlapping, within a predefined proximity of each other, or are interface elements for features having a short circuit. The abutment process may identify shapes for abutment that are not connected to a netlist of the design or are otherwise not associated with a connection pin. The abutment process may adjust a shape or feature including, for example by resizing, moving, inserting, or removing one or more shapes from the layout in accordance with predefined layout rules. After the shapes and features have been adjusted abutments may be formed between the features.

Abstract: Management of controls in a graphical user interface (GUI) of a computer system. In one aspect, a command is received to create and display a window in the GUI, the window including one or more controls, each control operative to perform a function of an application in response to selection. An associated scope for each control is determined and indicates an extent of shared use of the control within the GUI. It is determined if a different instance of the control already exists within the scope for the control. If so, resources of the different instance are referenced to be shared for use with the control and new resources are not created for the control. If no different instance exists within the scope, new resources for the control are created and stored. The window and the controls in the GUI are displayed.

Abstract: A computer-implemented method for interconnect redundancy of a circuit design comprises the steps of setting Manhattan distance being less than or equal to three pitches; placing a plurality of dummy micro bumps on at least one side of a die including a signal bump formed on the at least one side; determining an interconnecting candidate by selecting from the dummy micro bumps, which is distant from the signal bump by the Manhattan distance; and providing a routing path between the at least one interconnecting candidate and the signal bump.

Abstract: A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

Abstract: Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.

Abstract: Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a net comprising a set of pins, a first wire for routing the net is generated, the set of pins comprising the net is partitioned into one or more groups based at least in part on a cost function, a second wire that connects to the first wire is generated for each group of the net, and a third wire that connects each pin to the second wire of its group is generated for each pin of each group of the net.

Abstract: A hierarchical design flow generator for designing integrated circuits is disclosed. In one embodiment, the hierarchical design flow generator includes: (1) a partitioner configured to partition a hierarchical design flow for designing an IC into a late design flow portion and an early design flow portion, (2) a timing budgeter configured to provide a timing budget for the IC design based on initial timing constraints and progressive time constraints generated from the late design flow portion and the early design flow portion and (3) a modeler configured to develop a model for a top level implementation of the IC design based on the timing budget and block implementations generated during the late design flow portion.

Abstract: An integrated circuit is described. The integrated circuit, comprising: a central processor; a memory; and an electromigration compensation system associated with a plurality of leads within the integrated circuit, wherein the electromigration compensation system causes the plurality of leads to have interlocking, horizontally tapered ends that substantially reduces electromigration divergence and consequently lead resistance and circuit shorting.

Abstract: Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit.

Abstract: Software for designing and testing types of nanoelectronic circuits and larger scale electronics renderings is described. The software designs circuits comprising only a chain/leapfrog topology. The chain/leapfrog topology permits a wide range of circuits and circuit modules to be implemented on a common shared carbon nanotube, graphene nanoribbon, or strips of other types of semiconducting material, for example as rendered in traditional printed electronics and nanoscale printed electronics or as employing semiconducting polymers. In one approach a chain/leapfrog topology circuit design software tool accesses information in a library of chain/leapfrog circuits data, and creates descriptive data pertaining to a number of approaches to rendering electronics components using a library of component data. The chain/leapfrog circuits data library includes designs for a number of different types of chain/leapfrog circuit modules.

Abstract: A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit.

Abstract: An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints.

Abstract: A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.

Abstract: A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers.

Abstract: A disclosed method for evaluating placement context sensitivity in the design of an integrated circuit includes accessing a standard cell library comprising a database of standard cells and determining generating boundary data for each of the standard cells. The boundary data for a standard cell indicates the layout of features located within boundary regions of the standard cell. The method includes merging or consolidating boundary data for any two standard cells if their boundary data is the same to determine a canonical or minimal set of boundary regions. The disclosed method further includes enumerating and evaluating all combinations of pairs of the canonical boundary regions and, responsive to identifying of a proximity-based sensitivity or exception, modifying, notating, or otherwise remediating the applicable one or more standard cells that correspond to the boundary region combination that raised the exception.

Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

Abstract: Gating clocks has been a widely adopted technique for reducing dynamic power. The clock gating strategy employed has a huge bearing on the clock tree synthesis quality along with the impact to leakage and dynamic power. This invention is a technique for clock gate optimization to aid the clock tree synthesis. The technique enables cloning and redistribution of the fanout among the existing equivalent clock gates. The technique is placement aware and hence reduces overall clock wire length and area. The technique involves employing the k-means clustering algorithm to geographically partition the design's registers. This invention improves the clock tree synthesis quality on a complex design.

Abstract: A semiconductor device is disclosed to include a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.

Abstract: The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

Abstract: A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages.

Abstract: A method and system for designing and implementing a reconfigurable Doherty amplifier system are disclosed. In one embodiment, a design method includes determining, using a processor, a first set of ABCD transmission parameters of a first output compensation network in a main path of a Doherty amplifier for the case where an auxiliary amplifier of the Doherty amplifier is off. The method further includes determining, using a processor, a second set of ABCD transmission parameters of a second output compensation network in an auxiliary path of the Doherty amplifier based on the first set of ABCD transmission parameters.

Abstract: An integrated circuit (IC) design includes configurable circuits arranged in a mesh structure to facilitate routing of signals between different platforms or logic blocks within the design. Each configurable circuit has a semiconductor element with input and output terminals in a first semiconductor layer, input/output (I/O) ports corresponding to directions of the mesh structure in a second semiconductor layer, configurable input vias to allow a signal traveling in a first direction to be received, and configurable output vias that allow an output signal to be output from the configurable circuit in a second direction.

Abstract: A method reduces coupling noise and controls impedance discontinuity in ceramic packages by: providing at least one reference mesh layer; providing a plurality of signal trace layers, with each signal layer having one or more signal lines and the reference mesh layer being adjacent to one or more of the signal layers; disposing a plurality of vias through the at least one reference mesh layer, with each via providing a voltage (Vdd) power connection or a ground (Gnd) connection; selectively placing via-connected coplanar-type shield (VCS) lines relative to the signal lines, with a first VCS line extended along a first side of a first signal line and a second VCS line extended along a second, opposing side of said first signal line. Each of the VCS lines interconnect with and extend past one or more vias located within a directional path along which the VCS lines extends.

Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

Abstract: A method of assisting in the design of a logic circuit enabling the placement and wiring of cells (logic operation elements) to be optimized on an IC substrate in a short period of time even when the logic circuit has multiple levels, to provide a device assisting in the design of a logic circuit using this method, and to provide a computer program executable by this device. The cells of all levels are placed in a placement area formed on a grid, and a port enabling connection to a cell in another level is placed in a boundary portion between the placement area having cells already placed and a placement area enabling placement of new cells. Cells in the same level are wired between cells and cells in another level are wired between a cell and a port so that the sum total of the wiring lengths may be minimized.

Abstract: Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results.

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

Abstract: An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction may be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of interest to identify neighboring objects and generate an electrical model. The extraction approach can be taken for Islands, Nets, as well as other granularities within the design. Re-extraction of a design can occur at granularities smaller than a net. Some approaches utilize Island-stitching to replace an island within a net. An approach is also described for improving cross-references for cross-coupled objects.

Abstract: A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (?{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 ?m2).

Abstract: Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology.

Abstract: A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: (1) a cell placement EDA tool configured to transform a logical circuit representation into a physical circuit representation by placing cells from mixed cell libraries into clusters corresponding to the mixed cell libraries and (2) an interconnect routing EDA tool associated with the cell placement EDA tool and configured to route interconnects in buffer zones separating the clusters.

Abstract: A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions.

Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.

Abstract: A method includes converting an active region in a layout of an integrated circuit into a fin-based structure that has a fin. The active region belongs to an integrated circuit device, and has a planar layout structure. The method further includes extracting a Resistance-Capacitance (RC) loading of the integrated circuit device using the parameters of the fin-based structure. The steps of converting and extracting are performed by a computer.

Abstract: A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.

Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

Abstract: A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations.

Abstract: A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, post-route information of nets in the circuit design is analyzed. The post-route information includes, for each of the nets, a predicted route property, a post-route property, and a set of physical and/or timing attributes for that net. For each of the attributes, a set of attribute ranges is derived for the corresponding attribute to bin the nets into a Gaussian distribution for that attribute. Net routing constraints are generated for the circuit design based on the attribute ranges derived. The net routing constraints are applied to one or more of the nets during subsequent placement-based optimizations of the circuit design.

Abstract: A cell library is automatically designed. An emphasis of a design methodology is on automatic determination of the desired or needed cell sizes and variants. This method exploits different variants on drive strengths, P/N ratios, topology variants, internal buffering, and so forth. The method allows generating libraries that are more suitable for efficient timing closure.

Abstract: Methods for producing layout data for devices are described. One method includes using a genetic algorithm to determine a structure of a thermally-operated actuator. Another method includes receiving a three-dimensional model of a device, a design-rule set, and parameter ranges. Layout data are produced for devices having various combinations of parameter values in the parameter ranges.

Abstract: Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are provided by user-defined plug-ins, thereby allowing users to annotate circuit designs with constraints for proprietary layout and fabrication processes without exposing the constraints to tool vendors or competitors. The constraints are re-created from the template types whenever the circuit design is loaded into the EDA tool, so that the constraints are based upon the latest version of the template type. The constraints are also re-created when validation fails. Constraint groups are reusable in different designs, technology nodes, and processes because they automatically expand to provide the specific constraints to achieve a goal.

Abstract: Embodiments of systems and methods for leakage reduction of a cell are presented herein. According to one embodiment, a path module can identify each rail-to-rail path in a cell. In the embodiment, a transistor set module can select one or more transistors that are coupled to a rail of the cell and, if removed, no rail-to-rail path would exist in the cell. A layout modification module can transform the cell by upsizing a gate length of each transistor of the selected transistors to create a low-leakage version of the cell.

Abstract: A method is provided for exporting design constraints from a circuit design. In response to a first user command indicating a design constraint and a pattern, the design constraint is assigned to each object in the circuit design that matches the pattern, and the pattern is stored in a database. In response to a second user command to export design constraints of the circuit design, for each design constraint assigned to a respective set of objects of the circuit design, a pattern stored in the database that matches the respective set of the objects is determined and the design constraint is added to an export file in a format that uses the determined pattern. Design constraints on individual ones of the set of the objects indicated by the determined pattern are omitted from the export file.

Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit.

Abstract: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

Abstract: An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads.

Abstract: A surge protection circuit having an open circuit voltage surge protector, such as a gas discharge tube (GDT), a closed circuit current surge protector, such as a thermistor, and a thyristor. The GDT has a breakdown voltage that is at least a first defined amount higher than an anticipated highest peak voltage. The thermistor has a series resistance associated with a series resistance of electrical equipment being protected and a breakdown voltage that is at least a second defined amount higher than an impulse voltage (voltage required to excite the GDT based on the breakdown voltage) for the GDT. The thyristor has a rated peak current at least a third defined amount greater than a peak current for the thermistor.

Abstract: An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints.

Abstract: An electronic design automation system combines features of discrete EDA/CAD systems and manufacturing systems into a monolithic system to enable a layperson to efficiently design, construct and have manufactured a specific class of custom electronic device, namely a computer processing unit with embedded software. A Graphical User Interface (GUI) is provided as the front-end to a Computer Aided Design (CAD) server that generates sophisticated control and manufacturing instructions that are delivered to a fabrication supply chain, which produces a specified device that is then transported via managed logistics into inventory and ordering systems at vendors for delivery to a designated customer.