Abstract: Provided is a system, deployment and program for resource allocation unit queuing in which an allocation unit associated with a task is classified. An allocation unit freed as the task ends is queued for use by another task in a queue at a selected location within the queue in accordance with the classification of said allocation unit. In one embodiment, an allocation unit is queued at a first end of the queue if classified in a first class and is queued at a second end of the queue if classified in said second class. Other embodiments are described and claimed.

Abstract: An apparatus for context-based contact information management may include a processor. The processor may be configured to receive contact information and associated sender-based context information. In this regard, the contact information and sender-based context information may have been transmitted from a sending device. The processor may also be configured to associate receiver-based context information with the contact information and identify a historical context within a historical multi-dimensional context environment based at least in part on the sender-based context information and the receiver-based context information. Further, the processor may be configured to link the contact information to the historical context. Associated methods and computer program products may also be provided.

Abstract: When a CPU is processing a first task by using an accelerator for use in image processing, if a request for allocating the accelerator to a process of a second task is issued, the CPU sets an interruption flag when the process of the second task is prioritized over a process of the first task, and the accelerator is allowed to be used for the process of the second task when a state in which the interruption flag is set is detected at a timing predetermined in accordance with a process stage of the accelerator for the first task. Since the timing of detecting the set interruption flag is determined in accordance with a progress state of the process of the task to be interrupted, task switching can be made at a timing of reducing overhead for save and return for the process of the task to be interrupted.

Abstract: A real-time operating system (RTOS) for use with minimal-memory controllers has a kernel for managing task execution, including context switching, a plurality of defined tasks, individual ones of the tasks having subroutines callable in nested levels for accomplishing tasks. In the RTOS context switching is constrained to occur only at task level, and cannot occur at any lower sub-routine level. This system can operate with a single call . . . return stack, saving memory requirement. The single stack can be implemented as either a general-purpose stack or as a hardware call . . . return stack. In other embodiments novel methods are taught for generating return addresses, and for using timing functions in a RTOS.

Abstract: An information processing apparatus includes a thread management unit managing thread information on a per data processing unit basis, and a memory area management unit managing a memory area. The thread management unit stores a thread list containing entry time information that is recorded on a per thread basis as function call time of an operating system from a data processing program. The memory area management unit stores a release queue containing release request time that is recorded on an area unit basis concerning an unreleased memory area in response to a release request, compares the release request time set in each queue component contained in the release queue with the oldest entry time of each queue component in the thread list during a memory area allocation process, and allocates the memory area to the queue component having the release request time set prior to the oldest entry time.

Abstract: According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities.

Abstract: In an embodiment of the invention, a method for a memory-mapped lazy preemption control, the method includes: incrementing a counter value if an operating system attempts to involuntarily context switch out a thread and fails to context switch out the thread because the thread has a flag set; checking a counter value to determine a degree of abusiveness of a thread; and based upon the degree of abusiveness, determining if a voluntary contact switch out should be performed or should not be performed on the thread.

Abstract: A logic system in a data packet processor is provided for selecting and releasing one of a plurality of contexts. The selected and released context is dedicated for enabling the processing of interrupt service routines corresponding to interrupts generated in data packet processing and pending for service. The system comprises, a first determination logic for determining control status of all of the contexts, a second determination logic for determining if a context is idle or not, a selection logic for selecting a context and a context release mechanism for releasing the selected context. Determination by the logic system that all contexts are singularly owned by an entity not responsible for packet processing and that at least one of the contexts is idle, triggers immediate selection and release of an idle one of the at least one idle contexts to an entity responsible for packet processing.

Abstract: A method for providing access arbitration for an integrated circuit in a wireless device is provided. The method includes receiving a command from a processing element coupled to the integrated circuit. A preempt signal associated with the command is generated. The preempt signal is operable to identify a priority for the command as one of high and low. The preempt signal is provided to an access arbiter for use in providing access arbitration for the command.

Abstract: A plurality of sub-processors and a management processor process the first task. A graphic processor unit executes image processing corresponding to the first task processed by the management processor. One of the sub-processors performs a second task different from the first task. An image process related to the first task and originated in the sub-processor is accepted by the graphic processor unit and associated first rendering data is transferred to the graphic processor unit. Meanwhile, when the need arises in the one of the sub-processors for a second image process related to the second task, the one of the sub-processor saves second rendering data for the second image process in a main memory. Subsequently, when the graphic processor unit starts the second image process corresponding to the second task, the second rendering data is transferred from the main memory to a graphic memory.

Abstract: Methods and systems are disclosed for providing the integration of different Web applications into an online workflow. The methods and systems allow suspension of a first Web application, initiation of interaction with a second Web application, and subsequent resumption of the first Web application, while maintaining the state of the first Web application.

Abstract: In one aspect, a data race condition is detected based on an address of a variable shared by at least first and second threads for executing the program code, the shared variable address being stored in a hardware table. Detection of the data race condition in the program code is reported. In another aspect, at least first and second threads for executing the program code are synchronized based on an address of a variable shared by the threads and stored in a hardware table.

Abstract: In some embodiments, the invention involves a system to deprivilege components of a virtual machine monitor and enable deprivileged service virtual machines (SVMs) to handle selected trapped events. An embodiment of the invention is a hybrid VMM operating on a platform with hardware virtualization support. The hybrid VMM utilizes features from both hypervisor-based and host-based VMM architectures. In at least one embodiment, the functionality of a traditional VMM is partitioned into a small platform-dependent part called a micro-hypervisor (MH) and one or more platform-independent parts called service virtual machines (SVMs). The micro-hypervisor operates at a higher virtual machine (VM) privilege level than any SVM, while the SVM and other VMs may still have access to any instruction set architecture (ISA) privilege level. Other embodiments are described and claimed.

Abstract: Briefly, techniques to reduce the impact of interrupts and swaps on the completion time of tasks. In an embodiment, a code segment within a task adjusts the priority of the task. Other embodiments are also disclosed.

Abstract: Executing a monitor on a platform, the monitor capable of providing exclusive, secure access to an audio I/O device of the platform, executing a first partition on the platform, providing an audio device model in the first partition by directly mapping the audio I/O device from the monitor to the first partition for applications executing in the first partition, and providing exclusive, secure access to the audio I/O device to a program performing an audio function in a secure mode in the first partition.

Abstract: The present invention pertains to the field of onboard flight management systems embedded in aircraft. The invention relates to a reconfiguration device (1) for reconfiguring a task processing context. The reconfiguration device (1) according to the invention notably comprises: a module for managing the tasks to be carried out (2), performing a sorting of the tasks according to a priority criterion; a module for managing a current task (3), managing the state of progress of the current task; a module for managing a context (4), saving contexts relating to the current task, to a highest priority task and restoring one of the contexts saved on order of an operator. The present invention notably finds its application in the management of tasks for piloting an aircraft, for example the management of tasks originating from a system for managing alerts and procedures.

Abstract: A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an interrupt handler class that extends the execution flow class. The execution flow class defines an execution flow execution method and a constructor that creates an execution flow context. The interrupt handler class defines a handler method for an interrupt and an execution flow execution method that overrides the execution flow execution method of the execution flow class. An interrupt handler object is instantiated using the interrupt handler class, the constructor creates an execution flow context for the handler method, and when the interrupt is signaled, the JVM invokes a native execution flow activation method in the execution flow scheduler to switch to the handler execution flow context and the execution flow execution method to initiate execution of the handler method.

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as a static value. A second field of the save instruction encodes whether a value in a register of a processor is saved as an argument value. A third field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: Systems and methods start a process in an operating system. Additionally, a plurality of program units associated with the process are started. When a context shifting event occurs, each of the plurality of program units has their scheduling synchronized and their context set so that each thread processes the context shifting event. A further aspect of the system is that some program units may be executing on more than one multiple processor unit. In the operating system selects a multiple processor unit to host all of the program units, and migrates those program units that are not currently on the selected multiple processor unit to the selected multiple processor unit.

Abstract: A method of deadlock detection is disclosed which adjusts the detection technique based on statistics maintained for tracking the number of actual deadlocks that are detected in a distributed system, and for which types of locks are most frequently involved in deadlocks. When deadlocks occur rarely, the deadlock detection may be tuned down, for example, by reducing a threshold value which determines timeouts for waiting lock requests. When it is determined that actual deadlocks are detected frequently, the processing time for deadlock detection may be reduced, for example, by using parallel forward or backward search operations and/or by according higher priority in deadlock detection processing to locks which are more likely to involve deadlocks.

Abstract: A mechanism is provided for enabling an auxiliary program to be executed in a computer system, after an operating system has been loaded and executed, without rebooting the computer system. This may be achieved by suspending execution of the operating system, executing the auxiliary program while execution of the operating system is suspended, and then resuming execution of the operating system. In suspending execution of the operating system, state information defining a current state of the computer system is saved. In resuming execution of the operating system, the saved state information is used to restore the computer system to the current state. No state information or data should be lost as a result of suspending and resuming execution of the operating system. From the viewpoint of the operating system and the applications (if any) executing within the environment provided by the operating system, execution of the auxiliary program is transparent.

Abstract: Methods and systems for parallel computation of an algorithm using a plurality of nodes configured as a Howard Cascade. A home node of a Howard Cascade receives a request from a host system to compute an algorithm identified in the request. The request is distributed to processing nodes of the Howard Cascade in a time sequence order in a manner to minimize the time to so expand the Howard Cascade. The participating nodes then perform the designated portion of the algorithm in parallel. Partial results from each node are agglomerated upstream to higher nodes of the structure and then returned to the host system. The nodes each include a library of stored algorithms accompanied by data template information defining partitioning of the data used in the algorithm among the number of participating nodes.

Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.

Abstract: Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread execution context of an error domain for a multi-threaded processing system. Other embodiments are also described and claimed.

Abstract: A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run on either or both processors. A synchronization unit coupled to the first and second processors also may be provided to synchronize the processors. Further still, a translation lookaside buffer may be included that is shared between the processors. Each entry in the translation lookaside buffer (“TLB”) may include a task identifier to permit the operating system or middle layer software to selectively flush only some of the TLB entries (e.g., the entries pertaining to only one of the processors).

Abstract: A machine readable description of a new feature of a processor is provided by a processor vendor. Control code executing on a processor, such as a traditional operating system kernel, a partitioning kernel, or the like can be programmed to receive the description of the feature and to use information provided by the description to detect, enable and manage operation of the new feature.

Abstract: One particular implementation may take the form of a system or method for tracking application identification and application context in a context-isolated computing environment. The method may store such application information to reduce redundant information being stored on a stack. More particularly, the embodiment may store the application information in a context-specific marker frame. The context-specific marker frame may be stored once on the stack or it may be stored separately from the stack to maintain a small stack size. In another implementation, an invocation handler method may be called to store the redundant information about the executing application. The invocation handler may store the necessary information in a well-known location for later use by the virtual machine. The invocation handler may also provide further benefits, such as synchronization to ensure thread safety on shareable objects.

Abstract: A data processing system (1) is programmed with objects (2) according to the object-oriented architecture. Each object (2) is for implementing an event, which for financial securities processing is often referred to as a corporate action. An object (2) has a container (3) containing a series of masks (4), all at the same level in a flat structure. Each mask has four binary bit flags, each switching on or off a pre-stored unit (5) of executable code for an asynchronous transaction. Initialization or modifications of the system involves only processing through a series of decisions and setting mask flags accordingly.

Abstract: A microprocessor that includes a random number generator (RNG) that saves and restores its own state on a task switch without operating system (OS) support. The RNG includes a control and status register (CSR) for storing control values that affect the generation of random numbers. The CSR is not saved and restored by the OS. The RNG shadows the CSR with an SSE register that is saved and restored by the OS. A new instruction loads the CSR, and also loads the shadowed SSE register. Whenever the SSE register is restored from memory, the RNG sets a flag indicating that a possible task switch occurred. Whenever the processor executes a new instruction that stores the random data to memory, it checks the flag and copies the control values from the SSE register to the CSR if the flag is true, discards previously generated bytes, and restarts random number generation.

Abstract: A real-time operating system (RTOS) for use with minimal-memory controllers has a kernel for managing task execution, including context switching, a plurality of defined tasks, individual ones of the tasks having subroutines callable in nested levels for accomplishing tasks. In the RTOS context switching is constrained to occur only at task level, and cannot occur at any lower sub-routine level. This system can operate with a single call . . . return stack, saving memory requirement. The single stack can be implemented as either a general-purpose stack or as a hardware call . . . return stack. In other embodiments novel methods are taught for generating return addresses, and for using timing functions in a RTOS.

Abstract: In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

Abstract: A multiplexed hierarchical array of interrupt controllers is configured to enable low latency task switching of a processor. The hierarchical array comprises a plurality of interrupt controllers coupled to a root interrupt controller. For each task that the processor is configured to execute, a corresponding interrupt controller is provided. To switch the processor to a task, the corresponding interrupt controller signals the root interrupt controller which, in turn, sends an interrupt and a Task Identifier to the processor. The root interrupt controller also cooperates with an access multiplexer/demultiplexer to select the corresponding interrupt controller for communication with the processor. By providing interrupt controller selection as well as task identification, the hierarchical array offloads arbitration and context switching overhead from the processor. That is, in response to the interrupt, the processor switches to the identified task and may access a memory address space dedicated to the task.

Abstract: A method, system and computer program for mapping business concepts related to the processing of requests on a database system to database system feature settings is disclosed. Rules limit the requests that will be submitted to the database system for processing and establish workload definitions that can be used to map each request submitted to the database system for processing to database feature settings, based on business concepts associated with each request.

Abstract: Embodiments for performing cooperative user mode scheduling between user mode schedulable (UMS) threads and primary threads are disclosed. In accordance with one embodiment, an asynchronous procedure call (APC) is received on a kernel portion of a user mode schedulable (UMS) thread. The status of the UMS thread as it is being processed in a multi-processor environment is determined. Based on the determined status, the APC is processed on the UMS thread.

Abstract: Methods and apparatus provide for allocating a first stack module in response to a first function call of a software program running on a processing system; and allocating a second stack module in response to a second function call of the software program, wherein the second stack module is non-contiguous with respect to the first stack module.

Abstract: A plurality of virtual machines are executed on a host computer, the host computer including graphics hardware, and a display. The virtual machines write display data to their respective virtual desktop buffers. A virtual machine is selected to output to the display of the host computer. A composition buffer on the graphics hardware is enabled with respect to the selected virtual machine. The contents of the virtual desktop buffer associated with the selected virtual machine are copied to the composition buffer by the graphics hardware. The contents of the composition buffer are rendered and displayed by the graphics hardware. In addition, read access to the compositing buffer is restricted to the graphics hardware, thus preventing malicious software applications from capturing the display data across partitions.

Abstract: Systems, methods, and devices are provided for time measurement. One embodiment includes a method for measuring time on multiprocessor systems. The method includes allocating a memory space to a thread to be used to communicate with an operating system and saving a context switch count, an offset, and a scale factor, received from the operating system, in the memory space.

Abstract: Tasking systems and methods are provided that support user interfaces for displaying objects, the displayed objects enabling user access to resources that provide for effecting tasks among the system and devices of the systems' environment. More particularly, tasking systems and methods are provided that support the foregoing features, wherein the systems and methods support clustering operations respecting such task-associated objects so as to enhance the effecting of the associated tasks, such clustering operations responding to context. The clustering operations preferably are both adaptive and dynamic. Tasking systems and methods preferably support the tracking of selected states, including, as examples, one or more of environment states, device states, and system states. Tracked states typically also include states respecting other relevant criteria, such as temporal criteria.

Abstract: A system and method for identification of the execution context of a thread is disclosed. Under an embodiment of the invention, a method comprises associating a program object with a program thread; storing information concerning the program thread in the program object; and retrieving the information concerning the program thread upon request.

Abstract: Techniques are disclosed for detecting and resolving conflicts in context information from various sources. That information may be used to automatically update one or more context sources and/or to validate or invalidate (until further notice or for a period of time) input from one or more context sources. Or, the updates can be made in response to the user's instructions. Rules are used in preferred embodiments to dictate the conflict resolution approach for individual users. Updating the context source is particularly useful when the source is an electronic calendar. Updates that may be made to the calendar include adding, deleting, or changing scheduled events and/or working hours. Invalidating data from a context source is particularly useful for lost, forgotten, misplaced, or loaned devices. Marking data from a context source as valid is preferably done when harmony among several context sources is detected. Context suppliers may be notified of errors or discrepancies in their context data.

Abstract: Method, apparatus and system embodiments provide support for multiple SoEMT software threads on multiple SMT logical thread contexts. A thread translation table maintains physical-to-virtual thread translation information in order to provide such information to structures within a processor that utilize virtual thread information. By associating a thread translation table with such structures, a processor that supports simultaneous multithreading (SMT) may be easily retrofitted to support switch-on-event multithreading on the SMT logical processors.

Abstract: The invention virtualizes a computer that includes a host computer system, which comprises a processor, memory, and physical system devices. A conventional operating system (referred to below as the “host operating system” or “HOS”) is installed on the hardware. A computer program product that is executable within the host computer system comprises computer-executable code for implementing an interface software layer, preferably a virtual machine monitor, between the host system and a virtual machine; for reading in and storing state information of the processor associated with the HOS; and for logically decoupling the HOS from the processor with respect to pre-determined functions of the interface software layer and the virtual machine by setting the processor state information to settings associated with the interface software layer.

Abstract: A processor may utilise two operating systems (Non-Secure, Secure) between which calls may be made. In order that a second operating system can track task switches made by a first operating system, each time a call is made to the second operating system, this call includes an identifier to enable discrimination between the task which was executing on the first operating system when that call was made. The identifier can be a call identifier and/or a target thread identifier and may include further parameters.

Abstract: Methods and apparatus related to context management in a networked environment are provided. According to one aspect, a technique is provided for facilitating communication between a client and a context management (CM) server, comprising establishing a network connection between the client and the CM server to enable communication, and maintaining the connection for the period of time during which the context is maintained. According to another aspect, a requested change in at least one aspect of a context is facilitated by publishing a change decision from the context management server to the participant applications. In another aspect, a technique is employed to verify that a remote application is emulated on the same client as at least one other application in a context by receiving from the client and the remote application server information that uniquely identifies the client.

Abstract: A method, apparatus, and system are provided for a multi-threaded virtual state mechanism. According to one embodiment, active thread state of a first active thread is received using a virtual state mechanism, and virtual thread state is generated in accordance with the active thread state of the first active thread, and the virtual thread state corresponding to the first active thread is forwarded to state update logic.

Abstract: In a terminal device equipped with a function of running an application program, operation of an application program is suspended when an event is detected, the type of the event is predetermined, and event data representing the detected event is stored. Then, the terminal device delivers stored event data to the application program, after the suspended application is resumed.

Abstract: System and method for direct call of a target function by a start function by means of a processor with a memory management unit (MMU) in a computer operated by an operating system. A first task with a first memory context and with the staff function as a component executes the start function to perform a context switch from the first memory context into a second memory context. The target function is a component of a second task with the second memory context. The target function is executed in the second memory context, and the context switch is reversed to return to the first memory context after executing the target function.

Abstract: A mechanism for recording a timing in which a high urgency process is started is provided, and upon entry to a critical section in the middle of a low urgency process, by referencing the record, it is inspected whether a high urgency process will be started during execution of the critical section. If it will not be started, the critical section is entered, and if it will be started, control is exerted so that entry to the critical section is postponed until the high urgency process is completed. Exclusive access control in a critical section can be performed suitably under conditions where a plurality of task execution environments exist.

Abstract: A technique for accessing a shared resource of a computerized system involves running a first portion of a first thread within the computerized system, the first portion (i) requesting a lock on the shared resource and (ii) directing the computerized system to make operations of a second thread visible in a correct order. The technique further involves making operations of the second thread visible in the correct order in response to the first portion of the first thread running within the computerized system, and running a second portion of the first thread within the computerized system to determine whether the first thread has obtained the lock on the shared resource. Such a technique alleviates the need for using a MEMBAR instruction in the second thread.

Abstract: A method and system for efficient context switching are provided. An execution entity that is to be context switched out is allowed to continue executing for a predetermined period of time before being context switched out. During the predetermined period of time in which the execution entity continues to execute, the hardware or an operating system tracks and records its footprint such as the addresses and page and segment table entries and the like accessed by the continued execution. When the execution entity is being context switched back in, its page and segment table and cache states are reloaded for use in its immediate execution.