Abstract: An actinic ray-sensitive or radiation-sensitive resin composition includes: (A) a resin capable of increasing a solubility of the resin (A) in an alkali developer by an action of an acid; and (B) a compound capable of generating an acid upon irradiation with an actinic ray or radiation, wherein (B) the compound capable of generating an acid upon irradiation with an actinic ray or radiation is contained in an amount of 10 to 30 mass % based on the entire solid content of the actinic ray-sensitive or radiation-sensitive resin composition, and a pattern forming method uses the composition.

Abstract: A semiconductor light-emitting device including a substrate, an n-type semiconductor layer formed on the substrate, an active layer laminated on the n-type semiconductor layer and capable of emitting a light, a p-type semiconductor layer laminated on the active layer, an n-electrode which is disposed on a lower surface of the semiconductor substrate or on the n-type semiconductor layer and spaced away from the active layer and p-type semiconductor layer, and a p-electrode which is disposed on the p-type semiconductor layer and includes a reflective ohmic metal layer formed on the dot-like metallic layer, wherein the light emitted from the active layer is extracted externally from the substrate side.

Abstract: Designs of extremely high efficiency solar cells are described. A novel alternating bias scheme enhances the photovoltaic power extraction capability above the cell band-gap by enabling the extraction of hot carriers. When applied in conventional solar cells, this alternating bias scheme has the potential of more than doubling their yielded net efficiency. When applied in conjunction with solar cells incorporating quantum wells (QWs) or quantum dots (QDs) based solar cells, the described alternating bias scheme has the potential of extending such solar cell power extraction coverage, possibly across the entire solar spectrum, thus enabling unprecedented solar power extraction efficiency. Within such cells, a novel alternating bias scheme extends the cell energy conversion capability above the cell material band-gap while the quantum confinement structures are used to extend the cell energy conversion capability below the cell band-gap.

Abstract: A light emitting device, a light emitting device package, and a lighting system are provided. The light emitting device includes a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first and second conductive type semiconductor layers. The active layer includes a first active layer adjacent to the second conductive type semiconductor layer, a second active layer adjacent to the first conductive type semiconductor layer, and a gate quantum barrier between the first and second active layers.

Abstract: The present invention relates to polymer-silicon composite particles using silicon having high energy density, a method of making the same, an anode and a lithium secondary battery including the same. The silicon having high energy density is used as an anode active material to provide a lithium secondary battery having large capacity. Silicon-polymer composite particles having a metal plated on the surface thereof are provided to solve the problem that silicon has low electrical conductivity and a method of preparing the same is provided to produce an electrode having improved electrical conductivity. Furthermore, silicon-polymer composite particles having a metal coated on the surface thereof through electroless plating are prepared and an electrode is formed using the silicon-polymer composite particles.

Abstract: A fuel cell separator material, comprising an alloy layer 6 containing Au and a first component containing Al, Cr, Co, Ni, Cu, Mo, Sn or Bi, or an Au single layer 8 formed on a stainless steel base 2, and an intermediate layer 2a containing 20 mass % or more of the first component, and from 20 mass % or more to less than 50 mass % of arranged between the alloy layer and the base, wherein the alloy layer has a region having a thickness of 1 nm or more from the uppermost surface toward the lower layer and containing 40 mass % or more of Au, or a region having a thickness of 3 nm or more from the uppermost surface toward the lower layer and containing 10 mass % or more to less than 40 mass % of Au.

Abstract: The present disclosure relates to a method for making a transmission electron microscope grid. The method includes: (a) providing a substrate with a graphene layer on a surface of the substrate; (b) applying a carbon nanotube film structure to cover the graphene layer; (c) removing the substrate, to obtain a graphene layer-carbon nanotube film composite structure; and (d) placing the graphene layer-carbon nanotube film composite structure on a grid.

Abstract: A method of manufacturing a proton conductive solid oxide fuel cell, the method including: forming a metallic mask layer having nanoholes on a first surface of a substrate; selectively etching the first surface of the substrate using the metallic mask layer; depositing a first membrane electrode assembly (MEA) member on the etched first surface of the substrate; etching an opposing second surface of the substrate; and forming second and third MEA members on the first MEA member.

Abstract: A method comprises creating an electrode by depositing alternating first and second layers on a substrate, and using the electrode to make a solid oxide fuel cell. The first layer comprises a metal, and the second layer comprises a non-metal, for example a ceramic material. The substrate may be moved between a first region containing the metal and substantially free of the non-metal, and a second region containing the non-metal and substantially free of the metal. The composition of the metal and/or the non-metal may be varied along the thickness of the layers. The deposited layers may be heated. A fuel cell may have a fuel cell electrode that comprises a substrate, and alternating first and second layers deposited on the substrate, where the first layer includes a metal and the second layer includes a non-metal. The fuel cell may be a solid oxide fuel cell.

Abstract: A method for forming an epitaxial wafer is provided as one enabling growth of a gallium nitride based semiconductor with good crystal quality on a gallium oxide region. In step S107, an AlN buffer layer 13 is grown. In step S108, at a time t5, a source gas G1 containing hydrogen, trimethylaluminum, and ammonia, in addition to nitrogen, is supplied into a growth reactor 10 to grow the AlN buffer layer 13 on a primary surface 11a. The AlN buffer layer 13 is so called a low-temperature buffer layer. After a start of film formation of the buffer layer 13, in step S109 supply of hydrogen (H2) is started at a time t6. At the time t6, H2, N2, TMA, and NH3 are supplied into the growth reactor 10. A supply amount of hydrogen is increased between times t6 and t7, and at the time t7 the increase of hydrogen is terminated to supply a constant amount of hydrogen. At the time t7, H2, TMA, and NH3 are supplied into the growth reactor 10.

Abstract: Provided are a light emitting device, a method of fabricating the light emitting device, and a light unit. The light emitting device includes a light emitting structure layer comprising a first conductive type semiconductor layer, an active layer under the first conductive type semiconductor layer, and a second conductive type semiconductor layer under the active layer, a first conductive layer under the second conductive type semiconductor layer and electrically connected to the first conductive type semiconductor layer, a second conductive layer under the second conductive type semiconductor layer and electrically connected to the second conductive type semiconductor layer, an insulation layer between the first conductive layer and the second conductive layer, and a tunnel barrier under the second conductive type semiconductor layer and disposed between the first conductive layer and the second conductive layer.

Abstract: A semiconductor device comprises a semiconductor substrate on an insulating layer; and a second gate, the second gate is located on the insulating layer and is embedded at least partially in the semiconductor substrate. A method for forming a semiconductor device comprises: forming a semiconductor substrate on an insulating layer; forming a void within the semiconductor substrate, with the insulating layer being exposed by the void; and forming a second gate, with the void being filled with at least one part of the second gate. It facilitates the reduction of the short channel effects, resistances of source and drain regions, and parasitic capacitances.

Abstract: An object is to provide an electrode material with high electrical conductivity and a power storage device using the electrode material. An object is to provide an electrode material with high capacity and a power storage device using the electrode material. Provided is a particulate electrode material including a core containing a compound represented by a general formula Li2MSiO4 (in the formula, M represents at least one kind of an element selected from Fe, Co, Mn, and Ni) as a main component, and a covering layer containing a compound represented by a general formula LiMPO4 as a main component and covering the core. Further, a solid solution material is provided between the core and the covering layer. With such a structure, an electrode material with high electrical conductivity can be obtained. Further, with such an electrode material, a power storage device with high discharge capacity can be obtained.

Abstract: An organic light-emitting display device that may be easily manufactured and has an excellent display quality, the organic light-emitting display device including: an active layer of a thin-film transistor (TFT) formed on a substrate and including a semiconductor material; a lower electrode of a capacitor formed on the substrate and including a semiconductor material in which impurity ions are doped; a first insulating layer formed on the substrate so as to cover the active layer and the lower electrode; a gate electrode of the TFT formed on the first insulating layer and including a first gate electrode including silver (Ag) or an Ag alloy, a second gate electrode including a transparent conductive material, and a third gate electrode including metal that are sequentially stacked in the order stated; a plurality of pixel electrodes formed on the first insulating layer and including a first pixel electrode including Ag or an Ag alloy and a second pixel electrode including a transparent conductive material tha

Abstract: A storage element structure for phase change memory (PCM) cell and a method for forming such a structure are disclosed. The method of forming a storage element structure, comprises providing a multilayer stack comprising a chalcogenide layer (206), a metal cap layer (208), and a dielectric hard mask layer (210), depositing and patterning a photo resist layer (212) on top of the multilayer stack, etching the dielectric hard mask layer using the photo resist layer as etch mask, after the dielectric hard mask layer is etched, removing the photo resist layer before etching the chalcogenide, etching the chalcogenide layer using the dielectric hard mask layer as etch mask, depositing a spacer dielectric (214) over the multilayer stack and anisotropically etching the spacer dielectric to form sidewall spacers (216) for the multilayer stack.

Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

Abstract: Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer.

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract: Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below un-etched conductive metal oxide layer(s), forming the un-etched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOx, LaSrCoOx, LaNiOx, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the un-etched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

Abstract: Methods and apparatus for improved single-mode selection in a quantum cascade laser. In one example, a distributed feedback grating incorporates both index-coupling and loss-coupling components. The loss-coupling component facilitates selection of one mode from two possible emission modes by periodically incorporating a thin layer of “lossy” semiconductor material on top of the active region to introduce a sufficiently large loss difference between the two modes. The lossy layer is doped to a level sufficient to induce considerable free-carrier absorption losses for one of the two modes while allowing sufficient gain for the other of the two modes. In alternative implementations, the highly-doped layer may be replaced by other low-dimensional structures such as quantum wells, quantum wires, and quantum dots with significant engineered intraband absorption to selectively increase the free-carrier absorption losses for one of multiple possible modes so as to facilitate single-mode operation.

Abstract: A thin film transistor is provided that includes a gate electrode, a source electrode, and a drain electrode, an oxide semiconductor active layer formed over the gate electrode, a fixed charge storage layer formed over a portion of the oxide semiconductor active layer, and a fixed charge control electrode formed over the fixed charged storage layer.

Abstract: A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes a plurality M of doped layers, where M is an integer greater than 1. The dopant sheet densities in the M doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. M-1 interleaved layers provided between the M doped layers are not deliberately doped (also referred to as “undoped layers”). Structures with M=2, M=3 and M=4 have been demonstrated and exhibit improved passivation.

Abstract: The present invention provides a method for producing an n-type Group III nitride semiconductor product having a high Si concentration and exhibiting favorable crystallinity. In the production method, specifically, an AlN buffer layer is formed on a sapphire substrate by MOCVD, and then a first layer (thickness: 2 ?m) is formed from undoped GaN on the buffer layer by MOCVD at 1,140° C. Subsequently, a second layer (thickness: 200 nm) is formed from SiO2 on the first layer by plasma CVD, and then the second layer is removed by use of BHF (buffered hydrofluoric acid). Next, a GaN layer (thickness: 50 nm) is grown, by MOCVD at 1,140° C., on the first layer exposed by removal of the second layer without supply of an n-type dopant gas. Thus, on the first layer is provided a third layer formed of n-type GaN doped with Si at a high concentration and exhibiting favorable crystallinity.

Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant.

Abstract: The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.

Abstract: Metal gate structures and methods for forming thereof are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a feature formed in a high k dielectric layer may include depositing a first layer within the feature atop the dielectric layer; depositing a second layer comprising cobalt or nickel within the feature atop the first layer; and depositing a third layer comprising a metal within the feature atop the second layer to fill the feature, wherein at least one of the first or second layers forms a wetting layer to form a nucleation layer for a subsequently deposited layer, wherein one of the first, second, or third layers forms a work function layer, and wherein the third layer forms a gate electrode.

Abstract: A normally OFF field effect transistor (FET) comprising: a plurality of contiguous nitride semiconductor layers having different composition and heterojunction interfaces between contiguous layers, a Fermi level, and conduction and valence energy bands; a source and a drain overlying a top nitride layer of the plurality of nitride layers and having source and drain access regions respectively comprising regions of at least two of the heterojunctions near the source and drain; a first gate between the source and drain; wherein when there is no potential difference between the gates and a common ground voltage, a two dimensional electron gas (2DEG) is present in the access region at a plurality of heterojunctions in each of the source and drain access regions, and substantially no 2DEG is present adjacent any regions of the heterojunctions under the first gate.

Abstract: A light enhancement device includes at least two layers disposed over the substrate, including an adhesion layer disposed closer to the substrate than a metallic layer. At least one nanocavity extends into the metallic layer. The thickness of the adhesion layer and the diameter of the cavity have a ratio that is in the range of approximately 1:4 to 1:100. Capture molecules can be disposed within the nanocavities.

Abstract: A fabrication method of light emitting diode is provided. A first type doped semiconductor layer is formed on a substrate. Subsequently, a light emitting layer is formed on the first type doped semiconductor layer. A process for forming the light emitting layer includes alternately forming a plurality of barrier layers and a plurality of quantum well layers on the first type doped semiconductor layer. The quantum well layers are formed at a growth temperature T1, and the barrier layers are formed at a growth temperature T2, where T1<T2. Then, a second type doped semiconductor layer is formed on the light emitting layer.

Abstract: An electrically pumped light emitting device emits a light when powered by a power source. The light emitting device includes a first electrode, a second electrode including an outer surface, and at least one active organic semiconductor disposed between the first and second electrodes. The device also includes a dye adjacent the outer surface of the second electrode such that the second electrode is disposed between the dye and the active organic semiconductor. A voltage applied by the power source across the first and second electrodes causes energy to couple from decaying dipoles into surface plasmon polariton modes, which then evanescently couple to the dye to cause the light to be emitted.

Abstract: A GaN-based edge emitting laser is provided comprising a semi-polar GaN substrate, an active region, an N-side waveguiding layer, a P-side waveguiding layer, an N-type cladding layer, and a P-type cladding layer. The GaN substrate is characterized by a threading dislocation density on the order of approximately 1×106/cm2. The strain-thickness product of the N-side waveguiding layer exceeds its strain relaxation critical value. In addition, the cumulative strain-thickness product of the active region calculated for the growth on a the relaxed N-side waveguiding layer is less than its strain relaxation critical value. As a result, the N-side interface between the N-type cladding layer and the N-side waveguiding layer comprises a set of N-side misfit dislocations and the P-side interface between the P-type cladding layer and the P-side waveguiding layer comprises a set of P-side misfit dislocations. Additional embodiments are disclosed and claimed.

Abstract: The present application discloses a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a semiconductor substrate; an epitaxial semiconductor layer formed on two side portions of the semiconductor substrate; a gate stack formed at a central position on the semiconductor substrate and abutting the epitaxial semiconductor layer, the gate comprising a gate conductor layer and a gate dielectric layer which is sandwiched between the gate conductor layer and the semiconductor substrate and surrounding the lateral surfaces of the gate conductor layer; and a sidewall spacer formed on the epitaxial semiconductor layer and surrounding the gate. The method for manufacturing the above semiconductor structure comprises forming raised source/drain regions in the epitaxial semiconductor layer utilizing the sacrificial gate.

Abstract: To provide a light-emitting device from which uniform light emission can be obtained by providing an auxiliary wiring; a light-emitting device in which a short circuit between electrodes or between an electrode and an auxiliary wiring, which is attributed to a step caused by the auxiliary wiring, hardly occurs; and a light-emitting device which has high reliability by preventing a short circuit. In an EL light-emitting device including an auxiliary wiring, by covering a step caused by the auxiliary wiring is covered with an insulator, a short circuit between electrodes or between an electrode and the auxiliary wiring, which is attributed to the step caused by the auxiliary wiring, is prevented. Thus, the above objects are achieved.

Abstract: Disclosed are thin film transistor devices incorporating a crosslinked inorganic-organic hybrid blend material as the gate dielectric. The blend material, obtained by thermally curing a mixture of an inorganic oxide precursor sol and an organosilane crosslinker at relatively low temperatures, can afford a high gate capacitance, a low leakage current density, and a smooth surface, and can be used to enable satisfactory transistor device performance at low operating voltages.

Abstract: The disclosed subject matter provides a method and structure for obtaining ultra-low surface recombination velocities from highly efficient surface passivation in crystalline silicon substrate-based solar cells by utilizing a bi-layer passivation scheme which also works as an efficient ARC. The bi-layer passivation consists of a first thin layer of wet chemical oxide or a thin hydrogenated amorphous silicon layer. A second layer of amorphous hydrogenated silicon nitride film is deposited on top of the wet chemical oxide or amorphous silicon film. This deposition is then followed by annealing to further enhance the surface passivation.

Abstract: A radiation converter includes a directly converting semiconductor layer, wherein the semiconductor layer includes grains whose interfaces at least predominantly run parallel to a drift direction—constrained by an electric field—of electrons liberated in the semiconductor layer. in at least one embodiment, the charge carriers liberated by incident radiation quanta are accelerated in the electric field in the direction of the radiation incidence direction and on account of the columnar or pillar-like texture of the semiconductor layer, in comparison with the known radiation detectors, cross significantly fewer interfaces of the grains that are occupied by defect sites. This increases the charge carrier lifetime/mobility product in the direction of charge carrier transport. Consequently, it is possible to realize significantly thicker semiconductor layers for the counting and/or energy-selective detection of radiation quanta.

Abstract: A microstructure has at least one bonding substrate and a reactive multilayer system. The reactive multilayer system has at least one surface layer of the bonding substrate with vertically oriented nanostructures spaced apart from one another. Regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures. A method for producing at least one bonding substrate and a reactive multilayer system, includes, for forming the reactive multilayer system, at least one surface layer of the bonding substrate is patterned or deposited in patterned fashion with the formation of vertically oriented nanostructures spaced apart from one another, and regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures.

Abstract: An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface.

Abstract: A nanocrystal electroluminescence device comprising a polymer hole transport layer, a nanocrystal light-emitting layer and an organic electron transport layer wherein the nanocrystal light-emitting layer is independently and separately formed between the polymer hole transport layer and the organic electron transport layer. According to the nanocrystal electroluminescence device, since the hole transport layer, the nanocrystal light-emitting layer and the electron transport layer are completely separated from one another, the electroluminescence device provides a pure nanocrystal luminescence spectrum having limited luminescence from other organic layers and substantially no influence by operational conditions, such as voltage. Further included is a method for fabricating the nanocrystal electroluminescence device.

Abstract: Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Abstract: Devices, methods, and techniques for frequency-dependent optical switching are provided. In one embodiment, a device includes a substrate, a first and a second optical-field confining structures located on the substrate, and a quantum structure disposed between the first and the second optical-field confining structures. The first optical-field confining structure may include a surface to receive photons. The second optical-field confining structure may be spaced apart from the first optical-field confining structure. The first and the second optical-field confining structures may be configured to substantially confine therebetween an optical field of the photons.

Abstract: A structure having air gaps between interconnects is disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.

Abstract: A polymer film comprising a gas barrier coating of SiOx directly coated onto a first side of a polymer carrier layer. The film also comprises a heat sealable polyolefin layer arranged on a second side of the polymer carrier layer. The polymer film forms a part of a packaging laminate, and a packaging container can be produced from such a packaging laminate.

Abstract: The invention is a method of forming a cadmium sulfide based buffer on a copper chalcogenide based absorber in making a photovoltaic cell. The buffer is sputtered at relatively high pressures. The resulting cell has good efficiency and according to one embodiment is characterized by a narrow interface between the absorber and buffer layers. The buffer is further characterized according to a second embodiment by a relatively high oxygen content.

Abstract: An image sensor includes a semiconductor layer that filters light of different wavelengths. For example, the semiconductor layer absorbs photons of shorter wavelengths and passes more photons of longer wavelengths such that the longer wavelength photons often pass through without being absorbed. An imaging pixel having a photodiode is formed near a front side of the semiconductor layer. A dopant layer is formed below the photodiode near a back side of the semiconductor layer. A mirror that primarily reflects photons of longer visible wavelengths is disposed on the back side of the semiconductor layer.

Abstract: In a method of making graphite devices, a thin-film graphitic layer disposed against a preselected face of a substrate is created on the preselected face of the substrate. A preselected pattern is generated on the thin-film graphitic layer. At least one functionalizing molecule is attached to a portion of the graphitic layer. The molecule is capable of interacting with ? bands in the graphitic layer.

Abstract: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.

Abstract: It is described a microfluidic device, for use in the field of analytical fluorescence based assays and, in particular, in FISH assays.

Abstract: An electrode material is created by forming a thin conformal coating of metal oxide on a highly porous carbon meta-structure. The highly porous carbon meta-structure performs a role in the synthesis of the oxide coating and in providing a three-dimensional, electronically conductive substrate supporting the thin coating of metal oxide. The metal oxide includes one or more metal oxides. The electrode material, a process for producing said electrode material, an electrochemical capacitor and an electrochemical secondary (rechargeable) battery using said electrode material is disclosed.

Abstract: This invention relates to materials and processes for thin film deposition on solid substrates. Silica/alumina nanolaminates were deposited on heated substrates by the reaction of an aluminum-containing compound with a silanol. The nanolaminates have very uniform thickness and excellent step coverage in holes with aspect ratios over 40:1. The films are transparent and good electrical insulators. This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices, particularly through materials and processes for producing semi-porous dielectric materials wherein surface porosity is significantly reduced or removed while internal porosity is preserved to maintain a desired low-k value for the overall dielectric material.