Nanosheet Or Quantum Barrier/well (i.e., Layer Structure Having One Dimension Or Thickness Of 100 Nm Or Less) Patents (Class 977/755)
  • Publication number: 20110204323
    Abstract: A source of photons resulting from a recombination of localized excitons, including a semiconductor layer having a central portion surrounded with heavily-doped regions; above said central portion, a layer portion containing elements capable of being activated by excitons, coated with a first metallization; and under the semiconductor layer, a second metallization of greater extension than the first metallization. The distance between the first and second metallizations is on the order of from 10 to 60 nm; and the lateral extension of the first metallization is on the order of from ?0/10*ne to ?0/2*ne, where ?0 is the wavelength in vacuum of the emitted light and ne is the effective refractive index of the mode formed in the cavity created by the two metallizations.
    Type: Application
    Filed: December 15, 2010
    Publication date: August 25, 2011
    Applicants: Commissariat à I'Energie Atomique et aux Energies Alternatives, Centre National de la Recherche Scientifique, STMicroelectronics (Grenoble) SAS
    Inventors: Roch Espiau de Lamaestre, Jean-Jacques Greffet, Bernard Guillaumot, Ruben Esteban Llorente
  • Publication number: 20110204430
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
  • Publication number: 20110198636
    Abstract: Disclosed herein is an organic light emitting diode device, including: an organic EL element layer; an electrode layer supplying power to the organic EL element layer; and a metal nanocluster layer which is formed by covering a plurality of metal clusters with media and which is located between the organic EL element layer and the electrode layer to induce a luminescence enhancement effect. The organic light emitting diode device is advantageous in that carriers can be easily injected, so that light output efficacy is improved, thereby enhancing fluorescent emission output.
    Type: Application
    Filed: October 7, 2009
    Publication date: August 18, 2011
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Kyung Cheol Choi, Ki Youl Yang
  • Publication number: 20110198642
    Abstract: A light emitting device includes a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; and a plurality of polarizers, wherein a distance between a polarizer and an adjacent polarizer along a first direction is different from the polarizer and an adjacent polarizer in a second direction.
    Type: Application
    Filed: November 24, 2010
    Publication date: August 18, 2011
    Applicant: LG Innotek Co., Ltd.
    Inventor: Sun Kyung Kim
  • Publication number: 20110201240
    Abstract: The present invention relates to metal coated nano-fibres obtained by a process that includes electrospinning and to the use of said metal coated nano-fibres. The process is characterised in that a polymer nano-fibre with functional groups providing the binding ability to a reducing reagent is prepared by electrospinning at ambient conditions. Then this is contacted with a reducing agent, thereby opening the epoxy ring on the surface of polymer nano-fibre and replacing with the reducing agent and the reducing agent modified film is reacted with metal solution in alkaline media. Finally the electrospun mat is treated with water to open the epoxy rings in the structure and crosslinking the chains to provide integrity.
    Type: Application
    Filed: April 25, 2011
    Publication date: August 18, 2011
    Inventors: Mustafa Muammer DEMIR, Mehmet Ali Gulgun, Yusuf Ziya Menceloglu
  • Publication number: 20110198640
    Abstract: A semiconductor light-emitting diode (10) is proposed having at least one p-doped light-emitting diode layer (4), an n-doped light-emitting diode layer (2) and an optically active zone (3) between the p-doped light-emitting diode layer (4) and the n-doped light-emitting diode layer (2), having an oxide layer (8) consisting of a transparent conductive oxide, and having at least one mirror layer (9), wherein the oxide layer (8) is disposed between the light-emitting diode layers (2, 4) and the at least one mirror layer (9), and comprises a first boundary surface (8a) which faces the light-emitting diode layers (2, 4) and a second boundary surface (8b) which faces the at least one mirror layer (9), and wherein the second boundary surface (8b) of the oxide layer (8) has less roughness (R2) than the first boundary surface (8a) of the oxide layer (8).
    Type: Application
    Filed: February 11, 2009
    Publication date: August 18, 2011
    Inventors: Magnus Ahlstedt, Johannes Baur, Ulrich Zehnder, Martin Strassburg, Matthias Sabathil, Berthold Hahn
  • Publication number: 20110198652
    Abstract: A low resistance electrode and a compound semiconductor light emitting device including the same are provided. The low resistance electrode deposited on a p-type semiconductor layer of a compound semiconductor light emitting device including an n-type semiconductor layer, an active layer, and the p-type semiconductor layer, including: a reflective electrode which is disposed on the p-type semiconductor layer and reflects light being emitted from the active layer; and an agglomeration preventing electrode which is disposed on the reflective electrode layer in order to prevent an agglomeration of the reflective electrode layer during an annealing process.
    Type: Application
    Filed: April 27, 2011
    Publication date: August 18, 2011
    Applicant: SAMSUNG LED CO., LTD.
    Inventors: Joon-seop Kwak, Tae-yeon Seong, Jae-hee Cho, June-o Song, Dong-seok Leem, Hyun-soo Kim
  • Publication number: 20110197942
    Abstract: For the thin-film thermo-electric generator and fabrication method of this invention, a P-type thermo-electric thin-film layer, an insulating thin-film layer and a N-type thermo-electric thin-film layer is deposited on a substrate to form a three-layer PN junction, multiple three-layer PN junctions in series are available, an insulating thin-film layer is provided between every to serial three-layer PN junctions, and electrodes are extracted from the substrate and the outermost thin-film layer of the last three-layer thin-film PN junctions.
    Type: Application
    Filed: December 9, 2009
    Publication date: August 18, 2011
    Applicant: SHENZHEN UNIVERSITY
    Inventors: Ping Fan, Dongping Zhang, Zhuangghao Zjemg, Guangxing Liang
  • Publication number: 20110198564
    Abstract: Provided is a light emitting device. In one embodiment, the light emitting device includes: a first conductive type semiconductor layer including a plurality of grooves; an active layer formed on a upper surface of the first conductive type semiconductor layer and along the grooves; an anti-current leakage layer having a flat upper surface on the active layer; and a second conductive type semiconductor layer on the anti-current leakage layer.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 18, 2011
    Inventor: Hyo Kun SON
  • Publication number: 20110198617
    Abstract: Disclosed is a semiconductor device comprising a p-type SiC semiconductor and an ohmic electrode having an Ni/Al laminated structure provided on the p-type SiC semiconductor. The semiconductor device simultaneously has improved contact resistance and surface roughness in the ohmic electrode. The semiconductor device comprises an ohmic electrode (18) comprising a nickel (Ni) layer (21), a titanium (Ti) layer (22), and an aluminum (Al) layer (23) stacked in that order on a p-type silicon carbide semiconductor region (13). The ohmic electrode (18) comprises 14 to 47 atomic % of a nickel element, 5 to 12 atomic % of titanium element, and 35 to 74 atomic % of an aluminum element, provided that the atomic ratio of the nickel element to the titanium element is 1 to 11.
    Type: Application
    Filed: October 6, 2009
    Publication date: August 18, 2011
    Applicants: HONDA MOTOR CO., LTD., SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Kensuke Iwanaga, Seiichi Yokoyama, Hideki Hashimoto, Kenichi Nonaka, Masashi Sato, Norio Tsuyuguchi
  • Publication number: 20110193164
    Abstract: The present application discloses a semiconductor device formed on a SOI substrate which comprises a buried insulating layer and a semiconductor layer on the buried insulating layer and a method for manufacturing the same, wherein a fin of semiconductive material having two opposing sides perpendicular to a main surface of the SOI substrate is provided in the semiconductor layer, said semiconductor device comprising: a source region and a drain region provided at two ends of the fin respectively; a channel region provided at a central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, wherein the gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the SOI substrate.
    Type: Application
    Filed: June 24, 2010
    Publication date: August 11, 2011
    Inventor: Huilong Zhu
  • Publication number: 20110193096
    Abstract: An n-type GaN layer (3), a GaN layer (7) formed over the n-type GaN layer (3), an n-type AlGaN layer (9) formed over the GaN layer (7), a gate electrode (15) and a source electrode (13) formed over the n-type AlGaN layer (9), a drain electrode (14) formed below the n-type GaN layer (3), and a p-type GaN layer (4) formed between the GaN layer (7) and the drain electrode (14) are provided.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 11, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Tadahiro IMADA
  • Publication number: 20110193187
    Abstract: Disclosed is an electrode member for specific detection of an analyte using a photocurrent. The electrode member has at least a conductive substrate and an electron-accepting substance provided on said conductive substrate. The aforementioned electron-accepting substance consists at least of a first substance layer that is made of a semiconductor and a second substance that is made of a semiconductor of a kind different from that of the aforementioned semiconductor, a metal or a metal oxide, and is carried on the surface of said first substance layer. With the electrode member, improved detection sensitivity for the test substance and improved measurement precision can be achieved with specific detection of an analyte using a photocurrent.
    Type: Application
    Filed: September 1, 2009
    Publication date: August 11, 2011
    Applicant: TOTO LTD.
    Inventors: Masako Nakamura, Makoto Bekki, Jyunya Narita, Shuji Sonezaki, Hitoshi Ohara
  • Patent number: 7993780
    Abstract: This invention provides a process for producing a lithium secondary battery. The process comprises: (a) providing a positive electrode; (b) providing a negative electrode comprising a carbonaceous material capable of absorbing and desorbing lithium ions, wherein the carbonaceous material is obtained by chemically or electrochemically treating a laminar graphite material to form a graphite crystal structure having an interplanar spacing d002 of at least 0.400 nm as determined from a (002) reflection peak in powder X-ray diffraction; and (c) providing a non-aqueous electrolyte disposed between the negative electrode and the positive electrode to form the battery structure. This larger interplanar spacing (greater than 0.400 nm, preferably no less than 0.55 nm) implies a larger interstitial space between two graphene planes to accommodate a greater amount of lithium. The resulting battery exhibits an exceptionally high specific capacity, an excellent reversible capacity, and a long cycle life.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: August 9, 2011
    Assignee: Nanotek Instruments, Inc.
    Inventors: Bor Z. Jang, Aruna Zhamu
  • Publication number: 20110189287
    Abstract: The present invention relates to methods and compositions for wound healing. In particular, the present invention relates to promoting and enhancing wound healing by utilizing cross-linker covalent modification molecules to attach and deliver wound active agents to a wound. In addition, the present invention provides methods and compositions utilizing oppositely charged polyelectrolytes to form a polyelectrolyte layer on a wound surface. The invention further relates to incorporating wound active agents into a polyelectrolyte layer for delivery to a wound.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 4, 2011
    Inventors: Nicholas L. Abbott, Ankit Agarwal, Christopher J. Murphy, Jonathan F. McAnulty
  • Publication number: 20110188283
    Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 4, 2011
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Christophe J. Chevallier, Seow Fong Lim, Chang Hua Siau
  • Publication number: 20110186919
    Abstract: An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.
    Type: Application
    Filed: July 14, 2009
    Publication date: August 4, 2011
    Applicant: NXP B.V.
    Inventors: Wibo D. Van Noort, Theodore J. Letavic, Francis Zaato
  • Publication number: 20110190435
    Abstract: Disclosed is a method of exfoliating a layered material (e.g., graphite and graphite oxide) to produce nano-scaled platelets having a thickness smaller than 100 nm, typically smaller than 10 nm, and often between 0.34 nm and 1.02 nm. The method comprises: (a) subjecting the layered material in a powder form to a halogen vapor at a first temperature above the melting point or sublimation point of the halogen at a sufficient vapor pressure and for a duration of time sufficient to cause the halogen molecules to penetrate an interlayer space of the layered material, forming a stable halogen-intercalated compound; and (b) heating the halogen-intercalated compound at a second temperature above the boiling point of the halogen, allowing halogen atoms or molecules residing in the interlayer space to exfoliate the layered material to produce the platelets.
    Type: Application
    Filed: January 4, 2011
    Publication date: August 4, 2011
    Inventors: Bor Z. Jang, Aruna Zhamu
  • Publication number: 20110189081
    Abstract: A method for synthesizing high quality crystalline anatase titanium dioxide having a substantial occurrence of (001) facets. Including the steps of combining a source of fluoride anions with a titanium precursor and subjecting the mixture to hydrolysis. A solvent can be combined with the source of fluoride anions and the titanium precursor prior to hydrolysis. The crystalline anatase titanium dioxide can be produced to have the highly reactive (001) facets predominant by area in a variety of crystal structures, such as nanosheets.
    Type: Application
    Filed: March 25, 2009
    Publication date: August 4, 2011
    Inventors: Gao Qing Lu, Shizhang Qiao, Huagui Yang
  • Publication number: 20110181936
    Abstract: Optical modulator having wide bandwidth based on Fabry-Perot resonant reflection is disclosed. The optical modulator includes: a bottom Distributed Bragg Reflector (DBR) layer; a top DBR layer including at least one layer, and a modified layer; and an active layer disposed between bottom and top DBR layers, wherein the at least one layer includes at least one pair of a first refractive index layer having a first refractive index and a second refractive index layer having a second refractive index, the modified layer includes at least one pair of a third refractive index layer having a third refractive index and a fourth refractive index layer having a fourth refractive index, the third and the fourth refractive indexes being different, and at least one of the third and the fourth refractive index layers has a second optical thickness that is not ?/4 or that is not an odd multiple thereof.
    Type: Application
    Filed: November 2, 2010
    Publication date: July 28, 2011
    Applicants: SAMSUNG ELECTRONICS CO., LTD., GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yong-Chul CHO, Yong-Tak LEE, Yong-Hwa PARK, Byung-Hoon NA, Kwang-Mo PARK, Chang-Soo PARK
  • Publication number: 20110180124
    Abstract: A photovoltaic cell comprises an electrode layer (1b) of a transparent, electrically conductive oxide which is deposited upon a transparent carrier substrate (7b). There follows a contact layer (11b) which is of first type doped amorphous silicon and has a thickness of at most 10 nm. There follows a layer (26) of first type doped amorphous silicon compound which has a bandgap which is larger than the bandgap of the material of the addressed contact layer (11b). Subsequently to the first type doped amorphous silicon compound layer (2b) there follows a layer of intrinsic type silicon compound (3b) and a layer of second type doped silicon compound (5b).
    Type: Application
    Filed: July 8, 2009
    Publication date: July 28, 2011
    Applicant: OERLIKON SOLAR AG, TRUEBBACH
    Inventors: Hanno Goldbach, Tobias Roschek, Stefano Benagli, Bogdan Mereu
  • Publication number: 20110180905
    Abstract: A multilayer film stack containing germanium, antimony and tellurium that can be annealed to form a GST product material of homogeneous and smooth character, wherein at least one antimony-containing layer is isolated from a tellurium-containing layer by an intervening germanium layer, and the multilayer film stack comprises at least two intervening germanium layers. The multilayer film stack can be formed by vapor deposition techniques such as chemical vapor deposition or atomic layer deposition. The annealable multilayer film stack can be formed in high aspect ratio vias to form phase change memory devices of superior character with respect to the stoichiometric and morphological characteristics of the GST product material.
    Type: Application
    Filed: June 8, 2009
    Publication date: July 28, 2011
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Jun-Fei Zheng, Jeffrey F. Roeder, Philip S.H. Chen
  • Publication number: 20110177678
    Abstract: A method for manufacturing a nitride semiconductor device includes forming an n-type nitride-based semiconductor layer on a substrate; forming an active layer of a nitride-based semiconductors including In on the n-type nitride-based semiconductor layer using ammonia and a hydrazine derivative as group-V element source materials and a carrier gas including hydrogen; and forming a p-type nitride-based semiconductor layer on the active layer using ammonia and a hydrazine derivative as group-V element source materials.
    Type: Application
    Filed: September 24, 2010
    Publication date: July 21, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihito Ohno, Masayoshi Takemi, Takahiro Yamamoto
  • Publication number: 20110175110
    Abstract: A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.
    Type: Application
    Filed: March 23, 2010
    Publication date: July 21, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiji Wada, Shin Harada, Takeyoshi Masuda, Misako Honaga
  • Publication number: 20110176204
    Abstract: An edge photo-pumped semiconductor slab amplifier including an undoped semiconductor slab. A first gain structure is formed on an upper surface of the slab and a second gain structure is formed on a lower surface of the slab. The gain structures can be resonant periodic gain structures including a plurality of stacked quantum well layers. Confining layers are coupled to the gain structures to confine a signal beam within the semiconductor slab. Heat sinks are thermally coupled to the confining layers. Optical pump sources are provided along the side edges or coupled to the end edges of the slab so that pump light is introduced into the slab through the edges to provide gain for the quantum well layers.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 21, 2011
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Robert Rex Rice, Derek Evan Schulte, Elizabeth Twyford Kunkee
  • Publication number: 20110170208
    Abstract: The present invention in one aspect relates to a low-cost, nano-graphene based broadband optical limiter with limiting properties superior to current standards, carbon fullerenes (C60) solutions and carbon black suspensions. The broadband optical limiter includes a plurality of graphene nano-sheets, and a base material in which the plurality of graphene nano-sheets is distributed. The base material can be liquid or gel matrix.
    Type: Application
    Filed: April 23, 2010
    Publication date: July 14, 2011
    Applicant: Board of Trustees of the University of Arkansas
    Inventors: Wei Zhao, Boshan Zhao
  • Publication number: 20110170568
    Abstract: A surface emitting semiconductor laser includes a substrate, an n-type lower DBR, an n-type cavity extending region formed on the lower DBR, an active region formed on the cavity extending region, and an upper DBR formed on the active region. A difference in refractive index between a relatively high refractive index layer and a relatively low refractive in the upper DBR is smaller than that in the lower DBR.
    Type: Application
    Filed: July 8, 2010
    Publication date: July 14, 2011
    Applicant: FUJI XEROX CO., LTD.
    Inventor: Takashi Kondo
  • Publication number: 20110169167
    Abstract: A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results.
    Type: Application
    Filed: March 25, 2011
    Publication date: July 14, 2011
    Inventors: Munehiro Toyama, Siew Fong Tai, Kian Sin Sim, Charan K. Gurumurthy, Selvy Tamil Selvamuniandy
  • Publication number: 20110169006
    Abstract: Example embodiments are directed to oxide thin film transistors and methods of manufacturing the oxide thin film transistors. The oxide thin film transistor includes an active region in a gate insulation layer and under a source and a drain in a bottom gate structure, thus improving electrical characteristics of the oxide thin film transistor.
    Type: Application
    Filed: January 12, 2011
    Publication date: July 14, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Joon Seok Park, Tae Sang Kim
  • Publication number: 20110164632
    Abstract: An ultrashort pulse/ultra-high power laser diode with a simple structure and configuration. The laser diode can be driven by a pulse current which is 10 or more times higher than a threshold current value. The width of the pulse current is preferably 10 nanoseconds or less, and the value of the pulse current is specifically 0.4 amperes or over.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Applicant: SONY CORPORATION
    Inventors: Hiroyuki Yokoyama, Shunsuke Kono, Tomoyuki Oki, Masao Ikeda, Takao Miyajima, Hideki Watanabe
  • Publication number: 20110163339
    Abstract: A light-emitting element includes a first electrode, an organic layer with a light-emitting layer made of organic light-emitting material, a half-transmitting/reflecting film, a resistance layer, and a second electrode, which are sequentially laminated on top of the other. The first electrode reflects light from the light-emitting layer, the second electrode transmits light from the light-emitting layer. The half-transmitting/reflecting film includes a first half-transmitting/reflecting film and a second half-transmitting/reflecting film which are laminated in this order from a side of the organic layer. Also, the half-transmitting/reflecting film on the organic layer has an average thickness of 1 nm to 6 nm.
    Type: Application
    Filed: November 24, 2010
    Publication date: July 7, 2011
    Applicant: SONY CORPORATION
    Inventors: Eisuke Negishi, Jiro Yamada, Mitsuhiro Kashiwabara, Hirofumi Nakamura, Seonghee Noh
  • Publication number: 20110162180
    Abstract: A method for manufacturing a laminated ceramic capacitor includes a step of preparing a laminate which has a first principal surface, a second principal surface, a first end surface, a second end surface, a first side surface, and a second side surface and which includes insulating layers and internal electrodes having end portions exposed at the first or second end surface; a step of forming external electrodes on the first and second end surfaces such that plating deposits are formed on the exposed end portions of the internal electrodes so as to be connected to each other; and a step of forming thick end electrodes electrically connected to the external electrodes such that a conductive paste is applied onto edge portions of the first and second principal surfaces and first and second side surfaces of the laminate and then baked.
    Type: Application
    Filed: March 18, 2011
    Publication date: July 7, 2011
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Akihiro MOTOKI, Kenichi KAWASAKI, Makoto OGAWA, Shigeyuki KURODA, Shunsuke TAKEUCHI, Hideyuki KASHIO
  • Publication number: 20110164639
    Abstract: A two terminal semiconductor device for producing light emission in response to electrical signals, includes: a terminal-less semiconductor base region disposed between a semiconductor emitter region and a semiconductor collector region having a tunnel junction adjacent the base region; the base region having a region therein exhibiting quantum size effects; an emitter terminal and a collector terminal respectively coupled with the emitter region and the collector region; whereby application of the electrical signals with respect to the emitter and collector terminals, causes light emission from the base region. Application of the electrical signals is operative to reverse bias the tunnel junction. Holes generated at the tunnel junction recombine in the base region with electrons flowing into the base region, resulting in the light emission. The region exhibiting quantum size effects is operative to aid recombination.
    Type: Application
    Filed: December 31, 2010
    Publication date: July 7, 2011
    Inventors: Nick Holonyak, JR., Milton Feng, Gabriel Walter, Adam James
  • Publication number: 20110163421
    Abstract: Semiconductor micro- and nanotubes allow the incorporation of ordered structures such as quantum wells and quantum dots into them providing the potential for ultralow threshold micro- and nanoscale lasers for use in applications such as future ultrahigh-speed photonic systems as well as quantum information processing. According to the invention a means of manufacturing these with high reproducibility, low processing complexity, and at high densities is provided. Also provided is a means of releasing these micro- and nanotubes with low stress and a method of “pick-and-place” allowing micro- and nanotubes to be exploited in devices integrated on substrates that are either incompatible with the manufacturing technique or where the area of substrate required to manufacture them is detrimental to the cost or performance of the circuit.
    Type: Application
    Filed: January 4, 2011
    Publication date: July 7, 2011
    Applicant: The Royal Institution for the Advancement of Learning / McGill University
    Inventor: Zetian Mi
  • Publication number: 20110155211
    Abstract: Solar system for converting solar radiation into electric energy, the system comprising: a refraction array and a converting array, the refracting array including at least one refraction sub array, each of the refraction sub arrays including a plurality of refraction sites, each of the refraction sites refracting variable approach angle collimated solar radiation into a plurality of solar rays, each of the solar rays being of a different waveband, each of the refraction sites directing each of the solar rays, refracted thereby, in a different direction, the different direction being at least dependent on the approach angle of the solar radiation, the converting array including a plurality of broadband converting cells, positioned such that light refracted by the refraction array impinges on the converting array, wherein at any given moment, each of the converting cells receives solar rays of a specific waveband originating from different refraction sites and arriving from different directions thereto.
    Type: Application
    Filed: April 5, 2009
    Publication date: June 30, 2011
    Inventor: Moshe Einav
  • Publication number: 20110155295
    Abstract: An apparatus for applying carbon nanotube film is provided. The apparatus includes a supplier, a film application device, a cutter and at least one mechanical arm. The supplier is configured for locating a carbon nanotube array, which can supply a continuous carbon nanotube film to the film application device. The film application device includes a rotation axis and a rotator moving about the rotation axis. The rotator has a plurality of support surfaces opposite to the rotation axis. The plurality of support surfaces are used for applying at least one pre-laid supporter. The cutter is configured for cutting the carbon nanotube film. A method for applying carbon nanotube films using the apparatus is also provided.
    Type: Application
    Filed: July 30, 2010
    Publication date: June 30, 2011
    Applicants: TSINGHUA UNIVERSITY, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: SHOU-SHAN FAN, LIANG LIU, LI QIAN
  • Publication number: 20110154648
    Abstract: This invention provides for an apparatus and a method for detecting the presence of pathogenic agents with sensors containing functionalized nanostructures integrated into circuits on silicon chips. The nanostructures are functionalized with molecular transducers that recognize and bind targeted analytes which are diagnostic of the pathogenic agent of interest. The molecular transducer includes a receptor portion, which binds the analyte, and an anchor portion that attaches to the nanostructure. Upon binding of the analyte, a change in molecular configuration represented by the newly formed receptor-analyte complex creates a force that is transmitted to the nanostructure via the anchor portion of the transducer. The effect of the force transmitted to the nanostructure is to alter its conductivity. The change in conductivity of the nanotube thus represents a signal that indicates the presence of the pathogenic agent of interest.
    Type: Application
    Filed: March 14, 2011
    Publication date: June 30, 2011
    Applicant: NANOMIX, INC.
    Inventors: Jean Christophe Gabriel, George Gruner, Philip Collins, Basil Swanson, Fred Wudl
  • Publication number: 20110155990
    Abstract: A structure for a memory device including a plurality of substantially planar thin-film layers or a plurality of conformal thin-film layers is disclosed. The thin-film layers form a memory element that is electrically in series with first and second cladded conductors and operative to store data as a plurality of conductivity profiles. A select voltage applied across the first and second cladded conductors is operative to perform data operations on the memory device. The memory device may optionally include a non-ohmic device electrically in series with the memory element and the first and second cladded conductors. Fabrication of the memory device does not require the plurality of thin-film layers be etched in order to form the memory element. The memory element can include a CMO layer having a selectively crystallized polycrystalline portion and an amorphous portion. The cladded conductors can include a core material made from copper.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 30, 2011
    Applicant: UNITY SEMICONDUCTOR CORPORATION
    Inventors: Robin Cheung, Darrell Rinerson, Travis Byonghyop Oh, Jon Bornstein, David Hansen
  • Publication number: 20110156005
    Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Inventors: Ravi Pillarisetty, Been-Yih Jin, Benjamin Chu-Kung, Matthew V. Metz, Jack T. Kavalieros, Marko Radosavljevic, Roza Kotlyar, Willy Rachmady, Niloy Mukherjee, Gilbert Dewey, Robert S. Chau
  • Publication number: 20110156048
    Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.
    Type: Application
    Filed: June 4, 2009
    Publication date: June 30, 2011
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Ryou Kato
  • Publication number: 20110147712
    Abstract: A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: MARKO RADOSAVLJEVIC, GILBERT DEWEY, NILOY MUKHERJEE, RAVI PILLARISETTY
  • Publication number: 20110151260
    Abstract: It is an object of the present invention to provide a silica nanoparticle structure and a process for producing the same, which allow silica nanoparticles to be order-controlled to thereby make it possible to extend the application field of the silica nanoparticles ever more markedly. Silica nanoparticle structure components 2 can be prepared in which the silica nanoparticles 3 conventionally staying dispersed in a colloid solution can be converted into one-dimensionally ordered ones, and then adjacent silica nanoparticles are so firmly coupled as to be unable to disperse even if external force is applied thereto. Thus, the silica nanoparticles 3 become available for a variety of applications with the silica nanoparticles 3, conventionally staying dispersed in a colloid solution, order-controlled. Hence, the silica nanoparticle structure 1 can be provided which can extend the application field of the silica nanoparticles 3 still more markedly.
    Type: Application
    Filed: August 24, 2009
    Publication date: June 23, 2011
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Tatsuya Okubo, Atsushi Shimojima, Masashi Fukao, Ayae Sugawara, Gunsei Ou
  • Publication number: 20110150018
    Abstract: Provided is a laser device. In the laser device, an active layer is connected to a stem core of a 1×2 splitter on a substrate, a first diffraction grating is coupled to a first twig core of the 1×2 splitter, and a second diffraction grating is coupled to a second twig core of the 1×2 splitter. An active layer-micro heater is designed to supply heat to the active layer. First and second micro heaters are designed to supply heats to the first and second diffraction gratings, respectively, thereby varying a Bragg wavelength.
    Type: Application
    Filed: August 13, 2010
    Publication date: June 23, 2011
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Kyung Hyun PARK, Namje Kim, Young Ahn Leem, Sang-Pil Han, Chul-Wook Lee, Jaeheon Shin, Eundeok Sim, Yongsoon Baek
  • Publication number: 20110150960
    Abstract: It is an object of the present invention to provide a hazardous substance removing material, which efficiently captures hazardous substances derived from microorganisms such as bacteria or viruses and rapidly inactivates them, so as to minimize the their influences on human bodies, and which is able to allow an antibody to be supported on a carrier by a simple method, and which has an improved antibody use efficiency. The present invention provides a hazardous substance removing material consisting of a carrier on which an antibody and a sugar chain affinity substance having an affinity for a sugar chain in the Fc region of the antibody are supported.
    Type: Application
    Filed: July 29, 2009
    Publication date: June 23, 2011
    Inventor: Hiroshi Iwanaga
  • Publication number: 20110139730
    Abstract: The present invention is directed to the preparation and use of aromatic polyimide nanowebs with amide-modified surfaces. Uses include as a filtration medium, and as a separator in batteries, particularly lithium-ion batteries. The invention is also directed to a method comprising the aromatic polyimide nanoweb with amide-modified surface. The invention is further directed to a multi-layer article comprising the aromatic polyimide nanoweb with amide-modified surface, and to an electrochemical cell comprising the multi-layer article.
    Type: Application
    Filed: December 9, 2010
    Publication date: June 16, 2011
    Applicant: E. I. DU PONT DE NEMOURS AND COMPANY
    Inventors: T. JOSEPH DENNES, STEPHEN MAZUR
  • Publication number: 20110143088
    Abstract: Method for preparing a NiO nanosheet structure possessing (111) crystallographic planes as a primary surface with hexagonal holes, comprising the following steps: a) preparing a methanol solution of a nickel salt selected from the group consisting of nickel nitrate, nickel sulphate, nickel chlorate, nickel acetate, and nickel phosphate or a mixture thereof; b) adding benzyl alcohol (BZ), optionally substituted with alkyl, nitro, halo or amino, or a mixture thereof and urea to the solution of (a) in a ratio of Ni to BZ or substituted BZ of at least 1; c) solvent removal and calcination in air of the mixture, plate-like NiO nanosheet precursors therefore, NiO nanosheet structures obtainable by that method as well as various novel uses thereof.
    Type: Application
    Filed: March 10, 2008
    Publication date: June 16, 2011
    Applicant: Jacobs University Bremen gGmbH
    Inventors: Ryan Richards, Juncheng Hu
  • Publication number: 20110133168
    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
  • Publication number: 20110133088
    Abstract: A light detection system which comprises an active region between a back contact layer and a front contact layer is disclosed. The active region comprises a quantum well structure having a quantum well between quantum barriers, wherein the quantum well comprises foreign atoms that induce an excited bound state at an energy level which is above an energy level characterizing the quantum barriers.
    Type: Application
    Filed: August 19, 2010
    Publication date: June 9, 2011
    Applicant: Technion Research & Development Foundation Ltd.
    Inventors: Asaf ALBO, Gad Bahir, Dan Fekete
  • Publication number: 20110136280
    Abstract: A method of manufacturing an optoelectronic light emitting semiconductor device is provided where a Multi-quantum Well (MQW) subassembly is subjected to reduced temperature vapor deposition processing to form one or more of n-type or p-type layers over the MQW subassembly utilizing a plurality of precursors and an indium surfactant. The precursors and the indium surfactant are introduced into the vapor deposition process at respective flow rates with the aid of one or more carrier gases, at least one of which comprises H2. The indium surfactant comprises an amount of indium sufficient to improve crystal quality of the p-type layers formed during the reduced temperature vapor deposition processing and the respective precursor flow rates and the H2 content of the carrier gas are selected to maintain a mole fraction of indium from the indium surfactant to be less than approximately 1% in the n-type or p-type layers.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 9, 2011
    Inventor: Rajaram Bhat
  • Publication number: 20110130550
    Abstract: A protein polymer having a larger molecular weight is provided by regularly arranging a protein having a large molecular weight. The protein polymer having a large molecular weight can be obtained using a protein monomer represented by formula (I) or a salt thereof: wherein R1, R2, R3, R4, Y, and X are as defined in the specification.
    Type: Application
    Filed: March 10, 2009
    Publication date: June 2, 2011
    Applicant: OSAKA UNIVERSITY
    Inventors: Takashi Hayashi, Hiroaki Kitagishi, Koji Oohora, Akira Onoda, Yasuaki Kakikura