Abstract: A method of fabricating a semiconductor-on-insulator device including: providing a first semiconductor wafer having an about 500 angstrom thick oxide layer thereover; etching the first semiconductor wafer to raise a pattern therein; doping the raised pattern of the first semiconductor wafer through the about 500 angstrom thick oxide layer; providing a second semiconductor wafer having an oxide thereover; and, bonding the first semiconductor wafer oxide to the second semiconductor wafer oxide at an elevated temperature.

Abstract: Embodiments of the invention generally provide methods for forming a multilayer rear surface passivation layer on a solar cell substrate. The method includes forming a silicon oxide sub-layer having a net charge density of less than or equal to 2.1×1011 Coulombs/cm2 on a rear surface of a p-type doped region formed in a substrate comprising semiconductor material, the rear surface opposite a light receiving surface of the substrate and forming a silicon nitride sub-layer on the silicon oxide sub-layer. Embodiments of the invention also include a solar cell device that may be manufactured according methods disclosed herein.

Abstract: A semiconductor structure includes an n-channel field effect transistor (NFET) nanowire, the NFET nanowire comprising a film wrapping around a core of the NFET nanowire, the film wrapping configured to provide tensile stress in the NFET nanowire. A method of making a semiconductor structure includes growing a film wrapping around a core of an n-channel field effect transistor (NFET) nanowire of the semiconductor structure, the film wrapping being configured to provide tensile stress in the NFET nanowire.

Abstract: A process for treating the surface of a metal substrate comprising a constituent metal selected from the group consisting of Cr, Cu, Mn, Mo, Ag, Au, Pt, Pd, Rh, Pb, Sn, Ni, Zn, in some cases Fe, and alloys of these metals. An anodic potential is applied to the metal surface in an electrolytic circuit comprising the metal surface, a cathode, and an electrolytic solution that is in contact with the metal surface and in electrically conductive communication with the cathode. The electrolytic solution may contain an electrolyte comprising anions of phosphate, phosphonate, phosphite, phosphinate, nitrate, borate, silicate, molybdate, tungstate, carboxylate, oxalate and combinations thereof. The anion may comprise a polymer having a pendent moiety selected from the group consisting of phosphate, phosphonate, phosphite, phosphinate, sulfate, sulfonate, carboxylate and combinations thereof.

Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.

Abstract: A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations.

Abstract: Disclosed are a variety of porous and non-porous wire-like structures of microscopic and nanoscopic scale. For instance, disclosed are structures that comprise a porous object that comprises: (i) a first region; and (ii) a second region adjacent to the first region along an axis of the object, where the first region has at least one porous property different from that of the second region. Also disclosed are structures that include: (i) a high resistivity silicon; and (ii) a cross-section that is substantially perpendicular to an axis of the object. Also disclosed are methods of making and using such structures.

Abstract: A separator includes a porous body, and a particle membrane that is formed on at least one principal surface of the porous body. The particle membrane is made of inorganic particles, and has a void formed therein by the inorganic particles. The particle membrane has a porosity that is non-uniform in the thickness direction thereof.

Abstract: An infrared sensing element is provided and includes a substrate, a supporting electrical insulating layer formed on the substrate; a first electrode formed on the supporting electrical insulating layer, a pyroelectric layer formed on the first electrode, and a second electrode formed on the pyroelectric layer. The pyroelectric layer has a light receiving area of 1×102 to 1×104 ?m2, has a thickness of 0.8 to 10 ?m, and contains therein a compound expressed as Pb(ZrxTi1-x)O3, where 0.57<x<0.93 as a principal component.

Abstract: An integrated sensor is capable of detecting analytes using electrochemical (EC), electrical (E), and optical (O) signals or EC and O signals. The sensor introduces synergetic new capabilities and enhances the sensitivity and selectivity for real-time detection of an analyte in complex matrices, including the presence of high concentration of interferences in liquids and in gas phases.

Abstract: A microporous organic-inorganic hybrid membrane based on silica of the invention has an average pore diameter of less than 0.6 nm, and comprises bridging organosilane moieties of the formula ?O1.5Si—CHR—SiO1.5? or ?O1.5Si—CH(CH3)—SiO1.5?. The membrane can be used in the separation of hydrogen from mixtures comprising hydrogen and CH4, CO2, CO, N2, and the like, and in the separation of water from alcohols having 1-3 carbon atoms, optionally in the presence of an inorganic or organic acid.

Abstract: Disclosed is a fabrication method of a metal nanoplate using metal, metal halide or a mixture thereof as a precursor, wherein the single crystalline metal nanoplate is fabricated on a single crystalline substrate by performing heat treatment on a precursor including metal, metal halide or a mixture thereof and placed at a front portion of a reactor and the single crystalline substrate placed at a rear portion of the reactor under an inert gas flowing condition.

Abstract: An apparatus and method for low-power sensing, for example, sensing of chemical or biochemical analytes in a gas or liquid phase are disclosed. One aspect relates to the use of a thin continuous film without grain boundaries as a sensing layer in devices for sensing a predetermined analyte and to low power devices having such sensing layer. The sensing layer has a surface exposed to the analyte. The electrical impedance of the sensing layer changes upon adsorption of the predetermined analyte on the exposed surface of the sensing layer. The sensing layer may have a thickness in the range between about 1 nm and 100 nm, such as between about 1 nm and 30 nm. The sensing layer may be an amorphous layer.

Abstract: An optoelectronic semiconductor chip (1) is herein described which comprises a non-planar growth layer (2), which contains at least one first nitride compound semiconductor material, and an active zone (5), which contains at least one second nitride compound semiconductor material and is arranged on the growth layer (2), and a top layer (7), which is arranged on the active zone (5), the growth layer (2) comprising structure elements (4) at a growth surface (3) facing the active zone (5).

Abstract: The invention is directed to apparatus and chips comprising a large scale chemical field effect transistor arrays that include an array of sample-retaining regions capable of retaining a chemical or biological sample from a sample fluid for analysis. In one aspect such transistor arrays have a pitch of 10 ?m or less and each sample-retaining region is positioned on at least one chemical field effect transistor which is configured to generate at least one output signal related to a characteristic of a chemical or biological sample in such sample-retaining region.

Abstract: The present invention relates to a thermal transfer ribbon containing exfoliated layered inorganic nanoparticles or exfoliated layered double hydroxides and a manufacturing method thereof, and more particularly to a sublimation thermal transfer ribbon wherein a second adhesive layer, a transfer ink layer and a transfer protective layer are formed on one surface of a base film having a lubricating heat-resistant layer and a first adhesive layer formed on the other surface thereof, in which the lubricating heat-resistant layer, the transfer ink layer and the transfer protective layer contain exfoliated layered inorganic nanoparticles or exfoliated layered double hydroxide nanoparticles to improve the heat resistance, image uniformity and abrasion resistance of the thermal transfer ribbon.

Abstract: A semiconductor laser element includes a first electrode, a second electrode, a first reflecting mirror, a second reflecting mirror, and a resonator. The resonator includes an active layer, a current confinement layer, a first semiconductor layer having a first doping concentration formed at a side opposite to the active layer across the current confinement layer, and a second semiconductor layer having a second doping concentration higher than the first doping concentration formed between the first semiconductor layer and the current confinement layer. The first electrode is provided to contact a part of a surface of the first semiconductor layer. The first semiconductor layer has a diffusion portion into which a component of the first electrode diffuses. The second semiconductor layer contacts the diffusion portion. The second semiconductor layer is positioned at a node of a standing wave at a time of laser oscillation of the semiconductor laser element.

Abstract: A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility.

Abstract: The present invention provides a MOS device, which comprises: a substrate; an interface layer thin film formed on the substrate; a high k gate dielectric layer formed on the interface layer thin film; and a metal gate formed on the high k gate dielectric layer. The metal gate comprises, upwardly in order, a metal gate work function layer, an oxygen absorption element barrier layer, a metal gate oxygen absorbing layer, a metal gate barrier layer and a polysilicon layer.

Abstract: A semiconductor device for preventing the leaning of storage nodes and a method of manufacturing the same is described. The semiconductor device includes support patterns that are formed to support a plurality of cylinder type storage nodes. The support patterns are formed of a BN layer and have a hexagonal structure. The BN layer forming the support patterns has compressive stress as opposed to tensile stress and can therefore withstand cracking in the support patterns.

Abstract: A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

Abstract: In accordance with one embodiment of the present disclosure, a process of manufacturing a semiconductor laser diode comprising a gain section, a QWI output window, and QWI waveguide areas is provided. The QWI waveguide areas are fabricated using quantum well intermixing and define a QWI waveguide portion in the QWI output window of the laser diode. The QWI output window is transparent to the lasing wavelength ?L. The QWI waveguide portion in the QWI output window is characterized by an energy bandgap that is larger than an energy bandgap of the gain section such that the band gap wavelength ?QWI in the QWI waveguide portion and the QWI output window is shorter than the lasing wavelength ?L. The QWI output window is characterized by a photoluminescent wavelength ?PL. The manufacturing process comprises a ?PL screening protocol that determines laser diode reliability based on a comparison of the lasing wavelength ?L and the photoluminescent wavelength ?PL of the QWI output window.

Abstract: The present invention is a circuit connecting material used for the mutual connection of a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, and a circuit member in which electrodes and insulating layers are formed adjacent to each other on the surface of a board, with the edge parts and of the insulating layers being formed with a greater thickness than the electrodes on the basis of the main surfaces, wherein this circuit connecting material contains a bonding agent composition and conductive particles that have a mean particle size of 1 ?m or greater but less than 10 ?m and a hardness of 1.961 to 6.865 GPa, and this circuit connecting material exhibits a storage elastic modulus of 0.5 to 3 GPa at 40° C. and a mean coefficient of thermal expansion of 30 to 200 ppm/° C. at from 25° C. to 100° C. when subjected to the curing treatment.

Abstract: Concepts of the present disclosure may be employed to optimize optical pumping and ensure high modal gain in the active region of an optically pumped laser source by establishing an optical coupling gap such that the pump waveguide mode field overlaps the active gain region associated with the signal waveguide. The optical coupling gap is tailored to be sufficiently large to ensure that a significant active gain region length is required for absorption and sufficiently small to ensure that the pump waveguide mode field P overlaps the active gain region. In accordance with one embodiment of the present disclosure, the pump waveguide core is displaced from the signal waveguide core by an optical coupling gap g in a lateral direction that is approximately perpendicular to the optical pumping axis.

Abstract: Methods and devices of the invention perform an optical concentration by an expansion of usable spectral width of the incident energy. Preferred methods and devices of the invention concentrate optical energy by tuning it into a narrow spectral width to match the bandgap of another system component, such as an optical fiber, an optical sensor or a photovoltaic device that converts the optical energy. Embodiments of the invention include methods and devices for the spectral concentration of multi-wavelength light and subsequent transport of the concentrated output light.

Abstract: An organic light emitting diode (OLED) display includes a substrate including a plurality of pixels defined thereon, a thin film transistor (TFT) positioned at each pixel, a negative electrode electrically connected to the TFT, an organic emission layer positioned on the negative electrode, and a positive electrode positioned on the organic emission layer, the positive electrode including an auxiliary layer positioned on the organic emission layer, a conductive layer positioned on the auxiliary layer, and an insulation layer positioned on the conductive layer.

Abstract: Disclosed herein is a light emitting device. The light emitting device includes a support member and a light emitting structure on the support member and including a first conductive semiconductor layer, a second conductive semiconductor layer and an active layer interposed between the first and second conductive semiconductor layers, and the active layer includes at least one quantum well layer and at least one barrier layer, at least one potential barrier layer located between the first conductive semiconductor layer and a first quantum well layer, closest to the first conductive semiconductor layer, out of the at least one quantum well layer, and an undoped barrier layer formed between the at least one potential barrier layer and the first quantum well layer and having a thickness different from that of the at least one barrier layer. Thereby, brightness of the light emitting device is improved through effective diffusion of current.

Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

Abstract: Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less.

Abstract: A method for fabricating a phase change memory device including memory cells includes patterning a via to a contact surface of a substrate corresponding to each of an array of conductive contacts to be connected to access circuitry, lining each via with a conformal conductive seed layer to the contact surface, forming a dielectric layer covering the conductive seed layer, and etching a center region of each via to the contact surface to expose the conformal conductive seed layer at the contact surface. The method further includes electroplating phase change material on exposed portions of the conformal conductive seed layer, recessing the phase change material within the center region forming a conductive material that remains conductive upon oxidation, on the recessed phase change material, oxidizing edges of the conformal conductive seed layer formed along sides of each via, and forming a top electrode over each memory cell.

Abstract: Provided are a light emitting device, a method for fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a first conductive type semiconductor layer having a first top surface and a second top surface under the first top surface, an active layer on the first top surface of the first conductive type semiconductor layer, a second conductive type semiconductor layer on the active layer, a first electrode on the second top surface of the first conductive type semiconductor layer, an intermediate refractive layer on the second top surface of the first conductive type semiconductor layer, and a second electrode connected to the second conductive type semiconductor layer.

Abstract: Disclosed is a light-emitting device including: a support member; and a light-emitting structure on the support member, the light-emitting structure including a first semiconductor layer, at least one intermediate layer, an active layer and a second semiconductor layer, wherein the intermediate layer is on at least one of upper and lower regions of the active layer and comprises at least four layers, wherein the layers have different band gaps, and wherein, among the layers, a layer having the largest band gap contacts a layer having the smallest band gap. Based on this configuration, it is possible to reduce crystal defects and improve brightness of the light-emitting device through effective diffusion of current.

Abstract: The present invention concerns an intermediate reinforced composite part composed of an assembly of at least two composite members (1,2,4,5) each comprising reinforcing fibres or fabrics and an impregnation matrix, said assembly comprising a bonding agent (3) ensuring a mechanical bond between said members, characterised in that the bonding agent (3) comprises at least one carbon nanotube (“Bucky Paper”) sheet.

Abstract: Disclosed is a light-emitting device including a substrate, a light-emitting structure on the substrate, the light-emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer, a light-transmitting electrode layer on the second semiconductor layer, and a first reflective layer on the light-transmitting electrode layer, wherein the first reflective layer comprises a first layer having a first index of refraction and a second layer having a second index of refraction different from the first index of refraction. Based on this configuration, it is possible to protect the light-emitting device and improve luminous efficiency thereof.

Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.

Abstract: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

Abstract: The present application provides a protected solid adsorbent that includes a solid adsorbent substrate and a surface layer at least partially coating the solid adsorbent substrate, the surface layer being generally permeable to an active agent. Additionally, a process for protecting a solid adsorbent and an adsorption system that includes a vessel containing the protected solid adsorbent is provided.

Abstract: An electrode for silicon carbide includes a silicide region which is provided in contact with a surface of a silicon carbide (SiC) layer and a carbide region which is provided on the silicide region. The silicide region contains a silicide of a first metal in more amount than a carbide of a second metal whose free energy of carbide formation is less than that of silicon (Si). The carbide region contains the carbide of the second metal in more amount than the silicide of the first metal.

Abstract: The present invention refers to an electrode comprised of a first layer which comprises a mesoporous nanostructured hydrophobic material; and a second layer which comprises a mesoporous nanostructured hydrophilic material arranged on the first layer. In a further aspect, the present invention refers to an electrode comprised of a single layer which comprises a mixture of a mesoporous nanostructured hydrophobic material and a mesoporous nanostructured hydrophilic material; or a single layer comprised of a porous nanostructured material wherein the porous nanostructured material comprises metallic nanostructures which are bound to the surface of the porous nanostructured material. The present invention further refers to the manufacture of these electrodes and their use in metal-air batteries, supercapacitors and fuel cells.

Abstract: In one embodiment, a transistor includes: a substrate; a source electrode formed on the substrate; a drain electrode formed on the substrate; a graphene film formed between the source electrode and the drain electrode, the graphene film having a semiconductor region including a source side end and a conductor region including a drain side end, a width of the source side end of the graphene film in a channel width direction being narrower than a width of the drain side end of the graphene film in the channel width direction; and a gate electrode formed via a gate insulating film on the semiconductor region of the graphene film and the conductor region of the graphene film. The source electrode is connected to the source side end of the graphene film with a Schottky contact, and the drain electrode is connected to the drain side end of the graphene film with an ohmic contact.

Abstract: A transfer process for silicon nanomembranes (SiNM) may involve treating a recipient substrate with a polymer structural support. After treating the recipient substrate, a substrate containing the intended transferable devices may be brought in direct contact with the aforementioned polymer layer. The two substrates may then go through a Deep Reactive Ion Etch (DRIE) to remove at least a portion of the substrate containing the devices. Oxide may be selectively removed with a buffered oxide wet etch, leaving the transferred SiNM on the recipient substrate with the Underlying polymer layer.

Abstract: The present invention provides a semiconductor device including a memory that has a memory cell array including a plurality of memory cells, a control circuit that controls the memory, and an antenna, where the memory cell array has a plurality of bit lines extending in a first direction and a plurality of word lines extending in a second direction different from the first direction, and each of the plurality of memory cells has an organic compound layer provided between the bit line and the word line. Data is written by applying optical or electric action to the organic compound layer.

Abstract: A silicon light-emitting element includes a first conductivity type silicon substrate 10 having a first surface 10a and a second surface 10b on a side opposite to the first surface 10a, an insulating film 11 provided on the first surface 10a of the silicon substrate 10, a silicon layer 12 provided on the insulating film 11, and having a second conductivity type different from the first conductivity type, a first electrode 13 provided on the silicon layer 12, and a second electrode 14 provided on the second surface of the silicon substrate, and the silicon substrate 10 has a carrier concentration of 5×1015cm?3 to 5×1018cm?3, the silicon layer 12 has a carrier concentration of 1×1017cm?3 to 5×1019cm?3, and that is larger by one digit or more than the carrier concentration of the silicon substrate 10, and the insulating film 11 has a film thickness of 0.3 nm to 5 nm. Accordingly, a silicon light-emitting element that is applicable to a silicon photonics light source is realized.

Abstract: A driving TFT for an organic light-emitting display device includes a gate electrode on a portion of a substrate, a gate insulation layer on an entire surface of the substrate including the gate electrode, a semiconductor layer on the gate insulation layer and covering the gate electrode, the semiconductor layer including an n-type impurity layer, and source and drain electrodes overlapping portions of the semiconductor layer at respective sides thereof.

Abstract: A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.

Abstract: Provided is a detecting element that detects a parameter for a predetermined gas or liquid in a surrounding atmosphere by being excited by excitation light and generating light corresponding to the surrounding atmosphere, the detecting element including: a substrate; and nanoscale crystal structures formed on the substrate and constituted by a compound semiconductor light emitting element having a heterostructure well layer, wherein when the nanoscale crystal structures adsorb atoms or molecules of the predetermined gas or liquid, there is distortion of a band of a structure with a smaller bandgap width in the well layer, this distortion brings about a change in transition energy, and this change brings about a change in at least one of an intensity and a wavelength of light generated by the well layer, thereby indicating the parameter for the gas or the liquid.

Abstract: Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.

Abstract: A radiation image pickup apparatus allowed to restore a change in characteristics in a pixel transistors caused by radiation, and a method of driving the same are provided. The radiation image pickup apparatus includes: a pixel section including a plurality of unit pixels and generating an electrical signal based on incident radiation, each of the unit pixels including one or more pixel transistors and a photoelectric conversion element; a drive section for selectively driving the unit pixels of the pixel section; and a characteristic restoring section including a first constant current source for annealing and a selector switch for changing a current path from the unit pixels to the first constant current source at the time of non-measurement of the radiation, and allowing an annealing current to flow through the pixel transistor, thereby restoring characteristics of the pixel transistor.

Abstract: A symmetrical quantum well active layer provides enhanced internal quantum efficiency. The quantum well active layer includes an inner (central) layer and a pair of outer layers sandwiching the inner layer. The inner and outer layers have different thicknesses and bandgap characteristics. The outer layers are relatively thick and include a relatively low bandgap material, such as InGaN. The inner layer has a relatively lower bandgap material and is sufficiently thin to act as a quantum well delta layer, e.g., comprising approximately 6 ? or less of InN. Such a quantum well structure advantageously extends the emission wavelength into the yellow/red spectral regime, and enhances spontaneous emission. The multi-layer quantum well active layer is sandwiched by barrier layers of high bandgap materials, such as GaN.

Abstract: A composite article includes a substrate and a ceramic nanocomposite layer disposed on the substrate. The ceramic nanocomposite layer has a composition that includes silicon, boron, carbon and nitrogen.